Alinco DJ-S40T/E Service Manual

							DJ-S40T / E
Service Manual
CONTENTS
SPECIFICATIONS
1) GENERAL................................................................ 2
2) TRANSMITTER........................................................ 2
3) RECEIVER............................................................... 2
CIRCUIT DESCRIPTION
1) Receiver system ....................................................... 3
2) Terminalmitter system............................................... 4
3) PLL, VCO  Circuit....................................................... 4
4) M38224M6M............................................................ 5
SEMICONDUCTOR DATA
1) M64082A (XA0543) .................................................. 7
2) NMJ2070MT1 (XA210)............................................. 8
3) NJM2904V (XA0573)................................................ 8
4) NJM2902V-TE1 (XA0596)........................................ 9
5) TA31136FN (XA0404)............................................... 9
6) UPC2771T (XA0545).............................................. 10
7) CAT24WC16JITE13 (XA0855)................................ 10
8) S-816A30AMC (XA0848)........................................ 10
9) S-80827ALNP (XA0857)......................................... 11
10) MRF9745T1 (XE0034)............................................ 11
11) Transistor, Diode and LED Outline Drawings........... 12
12) LCD Connection ..................................................... 13
EXPLODED VIEW
1) Front View ............................................................... 14
2) Bottom View ............................................................ 15
PARTS LIST
MAIN Unit......................................................... 16~20
SW Unit.................................................................. 20
Mechanical Par ts .................................................... 20
Packing ................................................................... 20
ADJUSTMENT...................................................... 21~22
PC BOARD VIEW
1) UP0433(1/2) side A................................................ 23
2) UP0433(1/2) side B................................................ 24
3) PTT Unit WIRING................................................... 25
SCHEMATIC DIAGRAM............................................. 26
BLOCK DIAGRAM...................................................... 27
ALINCO,INC. 
						

							2
SPECIFICATIONS
1) GENERAL
Frequency coverage T : TX 430 ~ 449.995MHz  RX 410 ~ 470MHz
E : TX 430 ~ 439.995MHz  RX 430 ~ 439.995MHz
TA : TX 410 ~ 470MHz  RX 410 ~ 470MHz
Mode F3E (FM)
Channel steps 5, 10, 12.5, 15, 20, 25, 30 & 50kHz
Memory channels 99 channels+1 CALL channel
Antenna connector SMA (50Ω unbalanced)
Frequency stability ±5 ppm
Microphone impedance 2kΩ nominal
Power supply 4.5 ~ 16.0V DC (EXT.termonai)
3.6 ~ 16.0V DC (BATT terminal)
Current 600mA (typical) Transmit high at 1W
150mA (typical) Receive at 280mW
40mA (typical) standby
15mA (typical) Battery save on
Usable temperature range -10 ~ +60° C (14 ~ 140°F)
Dimensions 56 (W) × 102 (H) × 30 (D) mm (with EDH-31)
2.2(W) × 4.0(H) × 1.18(D) inches (with EDH-31)
(Projections not included)
Weight Approx. 160g (5.6oz) (with EBP-53N)
Approx. 95g (3.3oz) (without Battery)
Sub audible Tone(CTCSS) encoder/decoder installed (38tones)
2) TRANSMITTER
Output power Approx. 1.0W EBP-53N installed
Approx. 1.0W 13.8V DC
Approx. 0.6W EDH-31 installed
Approx. 0.2W (LOW)
Modulation system Variable reactance frequency modulation
Spurious emissions -60dB or less
Max. frequency deviation ±5kHz
3)  RECEIVER
Receive system Double conversion superheterodyne
Intermediate frequencies 1st 21.7MHz / 2nd 450kHz
Sensitivity(12dB SINAD) -14.0µdB (0.2uV) or less [430 ~ 450MHz]
Selectivity -6dB : 12kHz or more
-60dB : 28kHz or less
Audio output power 280mW or higher( 8Ω load)
200mW (8Ω10% THD) 
						

							3
CIRCUIT DESCRIPTION
1) Receiver System
     The receiver system is a double superheterodyne system with a 21.7MHz first IF and
     a 450kHz second IF.
1. Front End
     The signal from the anntena is pssed through low-pass filter and input to RF coil L24
     and L17(band pass filter).
     The signal from L24 and L17 is amplified by Q9,Q10 and led to the band pass filter,
     and let to the first mixer base of Q11.
2. First Mixer
     The amplified signal (f0) by Q9,Q10 is mixed eith the first local oscillator signal(f0-21.7MHz)
     from the PLL circuit by the first stage mixer Q11 and so is conver ted into the first IF signal.
     The unwanted frequency band of the first IF signal is eliminated by the monolithic
     crystal filter FL3,and led to IF amplifier Q8.
3. IF Circuit
     The first IF signal is amplified by Q8, and input to pin 16 of IC3, where it is mixed withthe
     second local oscillator signal(21.25MHz)and so is converted into the second IF signal(450kHz).
     The second IF signal is output from pin3 of IC3, and unwanted frequency band of second IF
     signal is eliminated by a ceramic filter FL2.
     The resulting signal is then amplified by the second IF limiting amplifier, and detected
     by quadrature circuit. the audio signal is output from pin9 of IC3
4.Audio Circuit
     The demodulated signal in IF IC3 contains the audio signal and CTCSS signal .
     CTCSS signal is passed through the low-pass filter of IC5 and led to TIN port of CPU
     to be decoded. The audio signal is input to the main volume VR3 passing through
     de-emphasis circuit and high-pass filter circuit of Q19.The signal of which level is
     adjusted at the main volume VR3 is input to IC6 of AF amp, then it is amplified to the
     level that can drive the speaker.
5.Squelch Circuit
    The noise in the audio signal from IC3 is passed through the noise-filter and input to pin8 of IC3.
    IC3 includes filter amplifier,high-pass filter and rectifier.
    The rectified voltage level from pin14 of IC3 is deliverd to the comparator of the CPU.
    The voltage is led to pin1 of CPU and compared with the setting voltage.The squelch
    will open if the input voltage is lower than the setting voltage.
    During open squelch ,pin11(AFS)of CPU becomes”H”level and pin9(AFP)of CPU
    becomes”L”level, AF control signal is being controlled and sounds is outputted from
    the speaker. 
						

							4
2)Transmitter System
  1.Microphone Amplifier
       The input signal from built-in or external microphone is led to the microphone mute
       circuit Q15,pre-emphasis circuit ,IDC circuit IC4,the signal is input to the maximum
       deviation adjustment volume VR2.Then mixed at the add VR2 with the CTCSS tone
       signal which is generated by CPU,Then it is input to VCO as the modulation signal.
  2.Power Amplifier
      The signal from VCO is amplified by IC1 and then passed through the low-pass filter,
       the antenna switch circuit and the output low-pass filter.
      The unwanted harmonics frequency signal is eliminated by the low-pass filter and
      input to the antenna.
 3)PLL,VCO Circuit
       Output frequency of PLL circuit is set by the serial data from microprocessor.
       PLL circuit consists of VCO Q2,buffer amplifier Q6.
       The pulse wave output of chage pump is converted to DC voltage by PLL loop filter
       circuit,snd supplied to D2,D15 of varicap diode in VCO unit.
       The frequency modulation is executed when audio signal voltage is supplied to the
       varicap D3.
       When PLL is unlocked,pin10 of IC2 goes to “High”. 
						

							5
4) M38224M6M
CPU
Terminal Connection
(TOP VIEW) 
						

							6
Terminal function of CPU
No. Pin Name Function I/O LogicDescriptionNo. Pin Name Function I/O LogicDescription1 P67 SQL I A/DNoise level input for squelch2 P66 KEY I A/DKey input ( , ,V/M)3 P65 VOX O Activ highPower cont.4 P64 EXTDC I A/DExt voltage input 5 P63 BP1 I A/DBand plan 16 P62 TIN I A/DCTCSS tone input7 P61 SMT I A/DS-meter input8 P60 BATT I A/DBatt voltage input9 P57 AFP O Activ lowAudio Amp ON/OFF10 P56 BEEP I/O PulseBeep sound out11 P55 AFS O Activ highAudio signal ON/OFF12 CNTR0 TBST I/O PulseArt tone output13 P53 BP3 IBand plan 314 P52 MONI I Activ lowMonitor key input15 P51 PSW I Activ lowPower switch input16 P50 STB O PulseStrobe for PLL17 P47 DATA I/O PulseData for PLL18 P46 CLK O PulseClock for PLL19 TxD CTX O PulseUART data transmission output20 RxD CRX I PulseUART data reception input21 P43 SCR I Activ highAlarm signal input22 INTO BU I Activ lowBack up signal detection input23 P41 PTTK I Activ highPTT signal input24 P40 BP4 I Activ highBand plan 425 RESET RESET I Activ lowReset input26 P71 SCL O PulseSerial clock for EEPRPM27 P70 SDA I/O PulseSerial data for EEPRPM28 Xin XIN I
29 Xout XOUT O
30 Vss GND
CPU GND31 P27 MMUTE O Activ highMicrophone mute output32 P26 H/L O Activ highPower control high=H33 P25 EXP O Activ lowEXP terminal control34 P24 FUNC I Activ lowFunc key input35 P23 PTTC O Activ highBeep sound level control36 P22 P3C O Activ lowPower supply control for VCO output37 P21 C3C O Activ highPower supply control38 P20 R3C O Activ lowPower supply control for RX39 P17 T3C O Activ lowPower supply control for TX40 P16 TON4 O Activ highTone output 4
41 P115 TON3 O Activ highTone output 342 P14 TON2 O Activ highTone output 243 P13 TON1 O Activ highTone output 144 SEG26 SEG22 OLCD SEG 2245 P115 SHIFT O Activ highVCO shift output TX=H46 P10 LAMPC O Activ highLamp ON/OFF output47 SEG23 SEG21 OLCD SEG 2148 SEG22 SEG20 OSEG 2049 SEG21 SEG19 OSEG 1950 SEG20 SEG18 OSEG 1851 SEG19 SEG17 OSEG 1752 SEG18 SEG16 OSEG 1653 P01 CHG O Activ highBattery charge control54 P00 MICC O Activ lowTX mic amp power supply outout55 SEG15 SEG15 OSEG 1556 SEG14 SEG14 OSEG 1457 SEG13 SEG13 OSEG 1358 SEG12 SEG12 OSEG 1259 SEG11 SEG11 OSEG 1160 SEG10 SEG10 OSEG 1061 SEG9 SEG9 OSEG 962 SEG8 SEG8 OSEG 863 SEG7 SEG7 OSEG 764 SEG6 SEG6 OSEG 665 SEG5 SEG5 OSEG 566 SEG4 SEG4 OSEG 467 SEG3 SEG3 OSEG 368 SEG2 SEG2 OSEG 269 SEG1 SEG1 OSEG 170 SEG0 SEG0 OSEG 071 Vcc VDD
72 Vref VDD
73 Avss GND
74 COM3 COM3 O
LCD COM 375 COM2 COM2 OLCD COM 276 COM1 COM1 OLCD COM 177 COM0 COM0 OLCD COM 078 VL3 VL3 ILCD power supply79 VL2 VL2 ILCD power supply80 VL1 VL1 ILCD power supply 
						

							7
SEMICONDUCTOR DATA
1) M64082AGP (XA0543)
DUAL PLL FREQUENCY SYNTHESIZER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
M64082AGP
SIXin
Xout
GND
CONT
Fin2 Vcc
PD1 RST CPS
Lock
XBo
Vss
PD2 Vc1
Fin1
1121413
9
10
8
7
15
16
11
6
2
3
45
Vcc Fin1CONT
Xin XoutXBo
SI
RST CPS
Fin2GND Vc1
PD2
Vss Lock
PD1
Programmable divider
for local oscillator 1
Data latch (17 bits)
latch
Phase
comparator
21 pulse counter OSC
1/2 divider1/4 divider
through
2-modulus
prescaler
(1/128, 1/129)
2-modulus
prescaler
(1/128, 1/129)
Shift register (21 bits)
Buffer
Programmable divider
for local oscillator 2
Data latch (17 bits) Data latch (11 or 17 bits)Programmable divider
for reference  frequency
Phase
comparator
Charge
pump
Lock
detection
Charge
pump 
						

							8
2) NJM2070MT1 (XA210)
Low Voltage  Power  Amplifier
Equivalent Circuit
3) NJM2904V-TE1 (XA0573) 
						

							9
4) NJM2902V-TE1 (XA0596)
Quad Single Supply Operational Amplifier
5) TA31136FN (XA0404)
Low Power FM IF 
						

							10
6) UPC2771T(XA0545)
Terminal Connection
(Top View)
C2H
3
2
14
5
61: INPUT
2: GND
3: GND
4: OUTPUT
5: GND
6: Vcc
7) CAT24WC16JITE13 (XA0855)
A0
A1
A2
Vss SDASCL WP VccName
Function
VssGround A0..A2User Configurable Chip Selects
SDASerial Address/Data I/O
SCLSerial Clock
WP Write Protect Input
Vcc
2.5V~6.0V Power Supply
PDIP
8) S-816A30AMC (XA0848)
41
3
25
OUT
R 
= 0.3Ω IN
CL EXT
INV
ON/OFFOUTV
SSV
S-816A
~SOT-23-5
Top view
1 54
23
 MC