Atari Asteroids Deluxe Signature Analysis Guide

							ASTEROIDS  DELUXESIGNATURE  ANALYSISGUIDE 
						

							1IntroductionThis guide is intended as an aid to troubleshooting the Asteroids Deluxe video game PCB.
The Signature Analyzer used to produce this guide was an HP5004a.  If it is found that the
signatures hold up for other makes/models of Signature Analyzers then please let me know
and I can add some kind of compatibility list to the document.  Suggestions of any kind to
improve this document are always welcome.
To get the most out of the guide you’ll need
Signature Analyzer (HP5004a)
Schematics for Asteroids Deluxe
6502 NOP card  (See the separate document 6502NOP for instructions on how to build
your own NOP card)
IC Clips
Some jumper wires (3 or 4 should be sufficient)
The scope of the guide is limited in that it will not enable you to fault find the entire PCB.  It
should, however, be good for the following sections of the PCB:
Address Bus Buffers, Address Decoding Circuitry, Clock Circuit, Program ROMs and
Data Buffer, Vector Generator Address Selector, Vector Generator RAM Select, Vector
Generator ROMs and the Vector Generator Data Buffer.
The Clock Circuit test is very limited.  The reason being is that I much prefer to check the
clock chain with a scope.  If you want to figure out the signatures for the Clock Circuit then
pass on the information and I’ll include it in the document.  If you want a detailed description
of these sections (and more) please refer to the Asteroids Deluxe schematic / drawing
package.
Using The GuideFor those of you who have used Atari Signature Analysis guides before then this should look
familiar and there’s probably no need to read through this section.  For the rest of you,
here’s a quick run down.  Every section should start with the settings for the Analyzer,
something like this
A.  SA Settings for xxxxx Test
Probe    TriggerIC Pin    Test Pt.
Start+veC2-25
Stop-veC2-25
Clock-veC2-39     f2 
						

							2The probe column refers to either the Start, Stop or Clock probes from the Signature
Analyzer.
The trigger column sets up the Start/Stop/Clock buttons on the front of the Analyzer.  I have
used –ve to indicate the negative going edge of the pulse (or the falling edge).
I have used +ve to indicate the positive going edge of the pulse (or the rising edge).
The IC Pin column refers to the point where the appropriate probe should be attached.
The Test Pt. column refers to an equivalent Test Point on the boards where the probe may
be attached.
For example, in the example above the Start probe should be connected to pin 25 of IC
C2.  The Start button on the front of the Analyzer should be in the fully out position to
indicate a positive going edge.  Similarly, the Stop probe should be connected to the same
IC/Pin as the Start probe but the Stop button on the Analyzer should be pressed in to
indicate a negative going edge.
The section immediately following the set up procedure contains the signatures for that part
of the test.  The same structure for the Set Up was employed as explained below.
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
C1-20+5V0003
C1-9AB0UUUU
C1-12AB1FFFF
Here, with the Analyzer probe on pin 20 of IC C1 you should get a reading of 0003.  On
pin 9 of IC C1 you should get a reading of UUUU. And so on.
A signature denoted by an (*) indicates that signature may be unstable.  Try taking the
signature with a 1Kohm resistor connected between the probe tip and +5V.
Down To BusinessOne of the things I like about this testing method is that you don’t need to have the PCB in
the cabinet.  If you prefer to work in the back of the cabinet then that’s fine.  If you have a
bench/test area with a +5V PSU (as I’m sure most of you have), then you can sit
comfortably at the bench.  Simply connect Ground (pins 1 and 22 on the edge connector)
and +5V (pins 2 and 21 on the edge connector) to the PCB and you’re ready to start.
Just set up the Analyzer as indicated and start probing for those signatures.  Always
remember to have the Watchdog disabled as this will lead to permanently unstable
signatures. 
						

							4What To Do When You Find An Incorrect SignatureIf you find a signature that doesn’t match the guide, check your set up first.  If your set up is
OK then you’ll need to trace the fault.  Rather than having a long winded ramble from me it
would be better to look at the following link on Al Kossow’s page.  If you haven’t already
had a look at his site then I’d definitely recommend having a look as it’s a bit of a gold mine.
http://www.spies.com/arcade/TE/SigAnalNotes.pdf
After you’ve had a look through the document then you should know enough to start tracing
the fault.  It should also give you a bit more information on Signature  Analysis in general.
Some Common FaultsThe two most common faults I’ve come across are bad sockets and shorted traces.  During
the Signature Analysis the bad socket problem is highlighted by the fact that the signatures
are unstable.  You may get some stable and some not.  When you get unstable signatures
whilst doing the ROM tests it does not necessarily indicate a bad ROM. Reseating the
ROM or replacing the socket is usually a good place to start.  The problem of shorted
traces is usually down to something being dragged across the board.  Sometimes they can
be quite hard to see but Signature Analysis shows it up quite good.
DisclaimerIf you toast yourself, your house, your dog, your family or more importantly your video
game, then it’s not my fault.  You use the information contained in this guide at your own
risk.  Good luck.
Document Author Peter Fyfe
Email (Home) [email protected]
Email (Work) [email protected]
6th
 February 2000 
						

							**  Tie the Watchdog Disable test point toground  **1.   Address Lines
A.  SA Settings for Address Buffer Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39     f2
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
C1-20+5V0003
C1-9AB0UUUU
C1-12AB1FFFF
C1-7AB28484
C1-14AB3P763
C1-5AB41U5P
C1-16AB50356
C1-3AB6U759
C1-18AB76F9A
B1-18AB87791
B1-14AB96321
B1-9AB1037C5
B1-5AB116U28
B1-7AB124FCA
C2-23A134868
C2-24A149UP1
C2-25A1500012.   Address Decoding
A.  SA Settings for Address Decoder Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39     f2
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
E3-4SINP0AF76
E3-5SINP16913
E3-6OPTS13HP
E3-9PMEM3282
E3-10VMEMAH63
E3-117APA
E3-12ZPAGEP508
D5-10PKYDCD3H01
C5-83H02
L2-4PROM0P933
L2-5PROM1UH4P
L2-6PROM2A04H
L2-7PROM386C1
C.  SA Settings for Address Decoder Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC3-14     6MHz
**  Tie R/W test point to ground  **
D.  Signatures
Logic ProbeSignalSignature
On IC/PinName
D5-14+5V00UP 
						

							2D5-40066 (*)
E4-87U7C
L5-1DMAGO383U
L5-2EAADDRLP759
L5-3WDCLR90P8
L5-4EXPLODEUA0P
L5-5A43F
L5-6EACONTROLU5FA
L5-7AUDIO81F6
L5-9NOISERESET1A35
B8-1300UP
B8-12A43F
B8-11DMARESETA43F
**  Remove jumper from R/W test point  **
3..Watchdog Circuit
A.  SA Settings for Watchdog Circuit Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39     f2
**  Tie L5-12 to ground  **
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
C5-14+5V0003
C5-6752C
D4-60398
D4-80000
**  Remove jumper from L5-12  **4..Clock Circuit
A.  SA Settings for Clock Circuit Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39     f2
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
B3-6763H
B3-83KHz8A4U
B3-1012KHz9720
5  ROM And Data Lines
A.  SA Settings for ROM0 Test (D1)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-4
Stop+veL2-4
Clock-veC2-39    f2
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
D1-24+5V826P
D1-9DB04869
D1-10DB1995C
D1-11DB2F0AH
D1-13DB3UF20
D1-14DB4A17H
D1-15DB5232H
D1-16DB64590
D1-17DB799P1 
						

							3C.  SA Settings for ROM1 Test (E/F1)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-5
Stop+veL2-5
Clock-veC2-39    f2
D.  Signatures
Logic ProbeSignalSignature
On IC/PinName
E/F1-9DB0UOF3
E/F1-10DB10UCU
E/F1-11DB20CA5
E/F1-13DB3A391
E/F1-14DB47F79
E/F1-15DB5U77P
E/F1-16DB6H494
E/F1-17DB7052H
E.  SA Settings for ROM2 Test (F/H1)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-6
Stop+veL2-6
Clock-veC2-39    f2
F.  Signatures
Logic ProbeSignalSignature
On IC/PinName
F/H1-9DB0P65C
F/H1-10DB16FH0
F/H1-11DB27C88
F/H1-13DB3PC19
F/H1-14DB494HP
F/H1-15DB5CP77
F/H1-16DB64AF2
F/H1-17DB77P08G.  SA Settings for ROM3 Test (J1)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-7
Stop+veL2-7
Clock-veC2-39    f2
H.  Signatures
Logic ProbeSignalSignature
On IC/PinName
J1-9DB0373U
J1-10DB1U96F
J1-11DB276U1
J1-13DB391PP
J1-14DB49P50
J1-15DB5A126
J1-16DB610A0
J1-17DB7F002
6.   Data Buffer
A.  SA Settings for data buffer test.
Probe    TriggerIC Pin    Test Pt.
Start-veL2-7
Stop+veL2-7
Clock-veC2-39    f2
B.  Signatures
Logic ProbeSignalSignature
On IC/PinName
E2-18 (19)D0373U
E2-17 (18)D1U96F
E2-16 (17)D276U1
E2-15 (16)D391PP
E2-14 (15)D49P50
E2-13 (14)D5A126
E2-12 (13)D610A0
E2-11 (12)D7F002 
						

							4**  The numbers in brackets are the pin assignments
when an AM8304B is used as opposed to a 74LS245
**
7.   Vector Generator Address
      Selector
A.  SA Settings for VG Address Sel Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39    f2
**  Tie K2-1 to ground  **
B  Signatures
Logic ProbeSignalSignature
On IC/PinName
K2-1+5V0003
K2-4AM116U28
K2-12AM124FCA
L2-10VROM2F501
L2-11VROM1P693
L2-12VRAMAA2A
F2-9AM0UUUU
F2-7AM1FFFF
F2-4AM28484
F2-12AM3P763
H2-12AM41U5P
H2-4AM50356
H2-7AM6U759
H2-9AM76F9A
J2-9AM87791
J2-12AM96321
J2-4AM1037C58.   Vector Generator RAM
A.  SA Settings for VG RAM Test
Probe    TriggerIC Pin    Test Pt.
Start-veC2-25
Stop-veC2-25
Clock-veC2-39    f2
**  Tie K2-1 to ground  **
B  Signatures
Logic ProbeSignalSignature
On IC/PinName
M4-398H1
M4-632U8
L4-437C6
9.   Vector Generator ROM
A.  SA Settings for VG ROM1  Test (R2)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-11
Stop+veL2-11
Clock-veC2-39    f2
**  Tie K2-1 to ground  **
B  Signatures
Logic ProbeSignalSignature
On IC/PinName
R2-24+5V826P
R2-9DDMA0A13F
R2-10DDMA137H3
R2-11DDMA29F59
R2-13DDMA369HU
R2-14DDMA49277
R2-15DDMA55530 
						

							5R2-16DDMA6725P
R2-17DDMA72604
C.  SA Settings for ROM2  Test (N/P2)
Probe    TriggerIC Pin    Test Pt.
Start-veL2-10
Stop+veL2-10
Clock-veC2-39    f2
**  Tie K2-1 to ground  **
D  Signatures
Logic ProbeSignalSignature
On IC/PinName
N/P2-9DDMA06334
N/P2-10DDMA12AH5
N/P2-11DDMA23431
N/P2-13DDMA3F67C
N/P2-14DDMA45H7C
N/P2-15DDMA57FFH
N/P2-16DDMA688U2
N/P2-17DDMA7A43310.   Vector Generator Data Buffer
A.  SA Settings for VG Data Buffer test
Probe    TriggerIC Pin    Test Pt.
Start-veL2-10
Stop+veL2-10
Clock-veC2-39    f2
B  Signatures
Logic ProbeSignalSignature
On IC/PinName
P1-18 (19)DB06334
P1-17 (18)DB12AH5
P1-16 (17)DB23431
P1-15 (16)DB3F67C
P1-14 (15)DB45H7C
P1-13 (14)DB57FFH
P1-12 (13)DB688U2
P1-11 (12)DB7A433
*  The numbers in brackets are the pin assignments
when an AM8304B is used as opposed to a 74LS245
*