Hughes Jvc 220 Projector Service Manual

							Chapter 2---System Description 
CORR_ 
SYNC 
Square wave HCT level synchronous signal for horiz axis. 
HORIZONTAL/VERTICAL DEFLECTION BOARD 
OUTPUTS DESCRIPTION 
IIC_CLK IIC clock line. Unidirectional clock line for control of synchronous 
data transfer over the IIC bus interface. 
IIC_DATA IIC data line. Bidirectional serial line for synchronous data transfer 
between the SCB and the Horizontal/Vertical Deflection board. 
I=Input, O=Output. 
O    V_RED_LIN_CONTROL 
O    V_GRN_LIN_CONTROL 
O    V_BLU_LIN_CONTROL 
O    V_RED_EDGE_CONTROL 
O    V_GRN_EDGE_CONTROL 
O    V_BLU_EDGE_CONTROL 
O    L/R_KEY_CONTROL 
O    L/R_PIN_CONTROL 
O    WIDTH_CONTROL 
O    H_RED_CENT_CONTROL 
O    H_GRN_CENT_CONTROL 
O    H_BLU_CENT_CONTROL 
O    V_RED_CENT_CONTROL 
O    V_GRN_CENT_CONTROL 
O    V_BLU_CENT_CONTROL 
O    FRONT/REAR 
O    FLOOR/CEIL 
 
HIGH VOLTAGE POWER SUPPLY 
INPUT DESCRIPTION 
/HV_OK The high voltage status line. Low =  operational HVPS. 
LOW VOLTAGE POWER SUPPLY 
INPUTS DESCRIPTION 
+ 5.1V Power for digital portion of SCB 
+15V Power for the analog portions of the SCB 
-15V Power for the analog portions of the SCB  
+5.1V_Stby Standby power to the CPU and peripherals. 
/LV_OK Tells SCB status of non-standby supply (all outputs working or not) 
OUTPUTS DESCRIPTION 
FAN_ENA Signal to enable the 24V standby power 
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							  Chapter 2---System Description 
LV_ENA Signal to enable the LVPS 
ARC LAMP POWER SUPPLY 
INPUTS DESCRIPTION 
/LAMP_OK Informs SCB that the Arc Lamp is installed, temperature is within 
limits, and lamp cooling blower is working 
/LAMP_LIT Informs the SCB that the Arc Lamp is lit or not lit 
OUTPUTS DESCRIPTION 
 /LAMP_ENA Enables ALPS power 
PROJECTION LENS 
OUTPUTS DESCRIPTION 
LENS_FOCUS Signal to lens focus motor 
LENS_ZOOM Signal to lens zoom motor 
FRONT IR 
INPUTS DESCRIPTION 
/FRONT_IR Input from front infrared receiver 
/REAR_IR Input from rear infrared receiver 
  
 
2.3.7  Raster Timing Generator PCB 
The Raster Timing Generator (RTG) is located in the electronic 
card cage (Figure 5-1). The RTG I/O diagram (Figure 2-13) and 
the list of inputs and outputs (Tables 2-10 and 2-11) provide 
information to allow the technician to perform module level 
troubleshooting. 
The following functions are provided by RTG board: 
• Internal sync generation 
• Sync detection and selection 
• Serration and equalization pulse removal 
• Phase locked loop 
• Blanking pulse generation 
• Horizontal and vertical phase adjustments 
• Interlace detection and odd field pulse generation 
• Horizontal frequency band selection  
• Horizontal line count and vertical count generation 
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							Chapter 2---System Description 
• IIC interface 
• Video clamp pulse generation 
• Source change detection 
• HVPS sync generation 
• Horizontal deflection enable circuitry 
The RTG I/O Diagram (Figure 2-13) and the list of inputs and 
outputs (Tables 2-12 and 2-13) provide information for the 
technician to perform module level troubleshooting. 
Horizontal frequency band selection and LED logic. 
The RTG produces a voltage that is proportional to the horizontal 
frequency which is used by the Horiz/Vert Deflection board, 
System Controller Board, and the phase locked loop (PLL) section 
of the RTG board. This DC voltage is used to create the following 
frequency bands: 
Band A: from 15 KHZ to 24.5 KHZ. 
Band B: from 24 KHZ to 29.5 KHZ 
Band C: from 29 KHZ to 56 KHZ 
Band D: from 55.5 KHZ to 90 KHZ. 
These bands are outputted through the IIC interface to be used by 
the System Controller Board. These lines are also outputs of the 
RTG board through the Backplane Board. The Horizontal/Vertical 
Deflection Board uses these lines for proper selection of retrace 
times. 
 
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							  Chapter 2---System Description 
B3     V_SYNC
B4    H_SYNC
B5    G_SYNC
HVPS_SYNC    A14
 A5    GRN_INPUT
A32        +5.1V
A31         +15V
    B30        -15V
V_DRIVE        B15 
B19     ISYNC_CLK
B27     IIC_CLKBLANKING      B1
CLAMP            B2
ODD_FIELD        B23
SOURCE_VALID    B24
280_CLK        B21
B28     IIC_DATA
J13
J13
FROM
SCB
FROM 
VPB
FROM
LVPS
TO
SCB
TO
VPB
RASTER
TIMING
GENERATOR
H_BAND1           B8
H_BAND0           B7
H_BAND2           B9
H_F2V                 B12
/H_ENABLE        B11
H_DRIVE            B16
TO
HVDB
TO
HVPSB32        +5.1V
B31         +15V
    A30        -15V
B29        GND
A29        +5.1V_STBY
TO
CDB
 
Figure 2-13.   Raster Timing Generator, Input/Output Diagram. 
There are 9 LEDs on the RTG board (see Figure 5-2) that indicate 
frequency bands, input modes and lock mode of the phase locked 
loop. 
IIC Interface 
The RTG board uses the IIC bus interface for serial 
communication with the System Controller Board. The information 
transferred over the IIC bus is indicated below (I = input to RTG, O 
= output from RTG). The RTG board does not use the interrupt 
line of IIC bus interface: 
Table 2-12.  Raster Timing Generator IIC communication 
Input / 
Output 
No. 
of 
bits Information Description 
I 1 FORCE_INTERNALSelects internal syncs 
I 1 TRI_LEVEL Selects the tri level mode for the video clamp 
signal (for HDTV) 
I 1 SYNC_TIP Selects the Sync tip option of video clamp 
signal 
I 1 VTR_MODE Selects VTR mode of operation 
I 9 Right blanking Data for adjustment of right blanking  
I 9 Left blanking Data for adjustment of left blanking  
I 12 Top blanking Data for adjustment of top blanking 
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							Chapter 2---System Description 
I 12 Bottom blanking Data for adjustment of bottom blanking 
I 8 Horz. phase Data for adjustment of horizontal phase 
I 12 Vert. phase Data for adjustment of vertical phase 
O 3 Frequency bands The frequency band associated with the current 
signal 
O 1 /RTG_OK A low on this line indicates an operational RTG 
board 
O 2 RTG_MODEL The revision of the RTG board 
O 12 H_COUNT The number of horizontal lines associated with 
the current signal 
O 12 V_COUNT Data for V_COUNT 
O 3 INPUT_MODE Data indicating the selected sync signals 
O 1 INTERLACE High indicates interlace pattern 
 
 
Raster Timing Generator Input/Output  
This section describes the inputs to and outputs from the RTG 
board. The I/O descriptions are arranged by the source and 
destination of the signal. The assembly communicated with is 
used as the primary heading of each output. Input refers to an 
input to the RTG, output refers to an output from the RTG. 
Table 2-13.  Raster Timing Generator I/O signals 
SYSTEM CONTROLLER BOARD
INPUTS DESCRIPTION 
ISYNC_CLK 5 mHz clock used to generate the internal sync signals 
IIC_CLK IIC clock line. Unidirectional clock line for control of synchronous 
data transfer over the IIC bus interface 
IIC_DATA IIC data line. Bi directional serial line for synchronous data transfer \
between system control board and RTG board 
OUTPUTS DESCRIPTION 
/IIC_INT IIC interrupt line. This is not used by the RTG board. 
SOURCE_ 
VALID 
This signal indicates a new source (or valid). A high indicates a vali\
d 
stable signal and low indicates change in input signal 
ODD_FIELD Square wave with 50 % duty cycle which is low during the odd field 
of an interlace signal. This signal is high for noninterlaced signals 
280_CLK Square wave signal, 50 % duty cycle, 280 times the frequency of 
horizontal sync. This clock is synchronized to the horizontal sync. 
VIDEO PROCESSOR BOARD 
INPUTS DESCRIPTION 
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							  Chapter 2---System Description 
V_SYNC Input vertical sync  
H_SYNC Input horizontal or composite sync 
G_SYNC Sync on green signal which is stripped for the green video 
GRN_INPUT Buffered version of green video 
OUTPUTS DESCRIPTION 
Clamp A negative going video clamp signal with about 3 % duty cycle 
Blanking  Blanking signal composed of right, left, top and bottom blanking 
HORIZONTAL/VERTICAL DEFLECTION BOARD 
INPUTS DESCRIPTION 
/H_ 
FLYBACK 
Not used by the RTG board 
OUTPUTS DESCRIPTION 
H_BAND0 
H_BAND1 
H_BAND2 
Horizontal frequency band lines 
Band A = 000, Band  B = 001, Band C = 011 and band D = 111  
/H_ENABLE  Low = enabled deflection and high = disabled deflection 
H_F2V A DC voltage proportional to horizontal frequency 
H_DRIVE Square wave 50 % duty cycle synchronized to the selected 
horizontal sync. 
HIGH VOLTAGE POWER SUPPLY 
OUTPUT DESCRIPTION 
HVPS_ 
SYNC 
Synchronization pulse for HVPS, synchronized with the selected 
horiz. sync at either same, half or one third the frequency 
CONVERGENCEDEFLECTION BOARD 
OUTPUT DESCRIPTION 
V_DRIVE Square wave negative going pulse synchronized to the selected 
vertical sync with pulse width of about 4 horizontal periods 
LOW VOLTAGE POWER SUPPLY 
INPUTS DESCRIPTION 
+5V Power for digital portion of RTG board 
+15V Power for the phase locked loop and the supporting circuitry of RTG 
board 
-15V Power for the phase locked loop and the supporting circuitry of RTG 
board  
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							Chapter 2---System Description 
+5.1V_STBY Stand by + 5.1 V. Not used by RTG board. 
 
Interlock and protection: 
Input 
None 
Output 
The RTG will disable the Horizontal Deflection Board by placing a 
high on the /H_ENABLE line during any of following events: 
A.   During and about 2 seconds after the programming period of 
the FPGA. 
B.   During frequency band change period. 
C.   During the period that the phase locked loop is out of lock. 
2.3.8   Horizontal/Vertical Deflection PCB 
The HVD board is located on the top side of the deflection cage in 
front of the electronic card cage. 
The Horizontal/Vertical Deflection Board I/O diagram (Figure 2-14) 
and the list of inputs and outputs (Tables 2-14 and 2-15) provide 
information for the technician to perform module level 
troubleshooting. 
The following functions are provided by the HVD board: 
• Horizontal raster centering for all three colors 
• Horizontal gate drive  
• Switch mode power supply generating the required 
proportional DC supply 
• Horizontal width adjustment 
• Horizontal retrace switch network  
• Left/right pincushion and keystone correction 
• Drive main deflection coils to provide horizontal raster scan for 
all three CRTs 
• Drive main vertical coils to provide vertical raster scan for all 
three CRTs 
• Vertical linearity adjustments individually for all three colors. 
• Vertical raster centering for all three colors 
• IIC interface 
IIC Interface 
All adjustments for the HVD board are performed by the System 
Controller via the IIC serial bus interface. This three wire bus 
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							  Chapter 2---System Description 
interface consists of a clock line, a data line, and an interrupt line. \
The HVD board does not create any interrupt and the interrupt line 
is not used for this application. Table 2-14 lists the adjustments 
executed via the IIC bus interface (I = Input to HVD board , O = 
Output from HVD board): 
 
 
Figure 2-14.  Horizontal/Vertical Deflection PCB I/O Diagram. 
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							Chapter 2---System Description 
Table 2-14.  Horizontal/Vertical Deflection IIC Data Interface 
INPUT / 
OUTPUT 
NO. 
OF 
BITS INFORMATION DESCRIPTION 
I 8 V_RED_LIN_CONTROL Data for adjustment of red vertical 
linearity   
I 8 V_GRN_LIN_CONTROL Data for adjustment of green vertical 
linearity  
I 8 V_BLU_LIN_CONTROL Data for adjustment of blue vertical 
linearity  
    
I 8 V_RED_EDGE_CONTROL Data for adjustment of red vertical 
edge linearity 
I 8 V_GRN_EDGE_CONTROL Data for adjustment of green vertical 
edge linearity  
I 8 V_BLU_EDGE_CONTROL Data for adjustment of blue vertical 
edge linearity 
I 8 L/R_KEY_CONTROL Data for adjustment of left / right 
keystone correction 
I 8 L/R_PIN_CONTROL Data for adjustment of left / right 
pincushion correction 
I 8 WIDTH_CONTROL Data for adjustment of screen width 
I 8 H_RED_CENT_CONTROL Data for adjustment of red horizontal 
centering  
I 8 H_GRN_CENT_CONTROL Data for adjustment of green 
horizontal centering  
I 8 H_BLU_CENT_CONTROL Data for adjustment of blue horizontal 
centering  
I 8 V_RED_CENT_CONTROL The data for adjustment of red vertical 
centering 
I 8 V_GRN_CENT_CONTROL The data for adjustment of green 
vertical centering 
I 8 V_BLU_CENT_CONTROL The data for adjustment of blue 
centering 
O 1 FRONT/REAR Front or rear projection status line  
front = low and rear = high 
O 1 FLOOR/CEIL Floor or ceiling projection status line 
floor = low and ceiling = high 
O 1 /DEFL_OK Deflection status. Low = operational 
HVD board, High = Nonoperational 
HVD board. 
O 2 HVD_MODEL Revision of HVD board 
Horizontal/Vertical Deflection Board I/O  
This section provides a description of the inputs to and outputs 
from the HVD Board. The I/O descriptions are arranged by the 
source/destination of the signal. The assembly communicated with 
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							  Chapter 2---System Description 
is used as the primary heading of each group of signals. Those 
signals are subdivided into inputs and outputs. Input refers to an 
Input to the HVD Board, output refers to an output from the HVD 
Board. 
Table 2-15.  Horizontal/Vertical Deflection I/O signals 
SYSTEM CONTROLLER BOARD
INPUTS DESCRIPTION 
IIC_CLK IIC clock line. Unidirectional clock line for control of synchronous 
data transfer over the IIC bus interface. 
IIC_DATA IIC data line. Bidirectional serial line for synchronous data transfer 
between the System Controller Board and the HVD Board. 
OUTPUTS DESCRIPTION 
/IIC_SINT IIC interrupt line. This is not used by HVD Board. 
VIDEO PROCESSOR BOARD 
OUTPUTS DESCRIPTION 
/SWEEPOK Low = good scan. High = no scan. Signal is dependent on two 
inputs; DEFL_OK (from SRB) and /H_ENABLE (from RTG). 
SCAN REVERSAL BOARD 
INPUTS DESCRIPTION 
FRONT/REAR Front or rear projection status line. Front = low. Rear = high. 
FLOOR/CEIL Floor or ceiling projection status line. Floor = low. Ceiling = high. 
DEFL_OK Deflection OK signal. High = good (about 2 v). Low = no scan. 
H_CUR_ 
FDBK 
Horizontal current feed back. A DC voltage proportional to the output 
current. 
H_LOCK- Horizontal interlock for yoke connectors. It should be 5 V when 
closed or 0V when open. 
V_RED- Current feedback of red vertical amplifier 
V_GRN- Current feedback of green vertical amplifier 
V_BLU- Current feedback of blue vertical amplifier 
  
OUTPUTS DESCRIPTION 
H_OUT_ 
FLYBACK 
Horizontal output flyback pulse, about 800 VPP 
H_LOCK+ Horizontal interlock for yoke connectors. This should be about 5 V 
when closed  or 15 V when open. 
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