Nintendo 8 Bit Manual

 
 
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Figure 2-3. CPU memory map. 
 
2.3 Registers 
 
The 6502 has fewer registers than similar processors. There are three special purpose 
registers, the program counter, stack pointer and status register which each have a specific 
use. It also has three general purpose registers, the accumulator and the index registers, X 
and Y, which can be used to store data or control information temporarily. 
 
2.3.1 Program Counter (PC) 
 
The program counter is a 16-bit register which holds the address of...

 
 
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The stack is located at memory locations $0100-$01FF. The stack pointer is an 8-bit register 
which serves as an offset from $0100. The stack works top-down, so when a byte is pushed 
on to the stack, the stack pointer is decremented and when a byte is pulled from the stack, 
the stack pointer is incremented. There is no detection of stack overflow and the stack 
pointer will just wrap around from $00 to $FF. 
 
2.3.3 Accumulator (A) 
 
The accumulator is an 8-bit register which stores the results...

 
 
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•  Negative Flag (N) - Bit 7 of a byte represents the sign of that byte, with 0 being positive 
and 1 being negative. The negative flag (also known as the sign flag) is set if this sign bit 
is 1. 
 
The flags are arranged in the status register in the order shown in figure 2-3. Bit 5 of the 
status register is unused. 
 
 
 
Figure 2-4. Status register layout. 
 
2.4 Interrupts 
 
Interrupts prevent the standard sequential execution of code and cause the processor to 
attend to the interrupt....

 
 
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Figure 2-5. NMI (Non-Maskable Interrupt) handling. 
 
2.5 Addressing Modes 
 
The 6502 has several different addressing modes, providing different ways to access 
memory locations. There are also addressing modes which operate on the contents of 
registers, rather than memory. In total there are 13 different addressing modes on the 6502. 
Some instructions can use more than one different addressing mode. Details on the available 
addressing modes can be found in Appendix E. 
 
2.6 Instructions...

 
 
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•  Jumps / Calls - Break sequential execution sequence, resuming from a specified 
address. 
•  Branches - Break sequential execution sequence, resuming from a specified address, if a 
condition is met. The condition involves examining a specific bit in the status register. 
•  Status Register Operations - Set or clear a flag in the status register. 
•  System Functions - Perform rarely used functions. 
 
 
  

 
 
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3 - Picture Processing Unit 
 
3.1 2C02 Overview 
 
Ricoh also supplied the 2C02 to serve as PPU. The PPU’s registers are mostly located in the 
I/O registers section of CPU memory at $2000-$2007 and $4014 as described in Appendix 
B. In addition, there are some special registers used for screen scrolling. 
 
3.2 PPU Memory Map  
 
The PPU has its own memory, known as VRAM (Video RAM). Like the CPU, the PPU can 
also address 64 KB of memory although it only has 16 KB of physical RAM. The PPU’s...

 
 
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$0000
$2000
$3F00
$4000
$10000
Pattern Table 0 Pattern Table 1Mirrors
$3F00-$3F1F
Sprite Palette
Image Palette
Mirrors
$2000-$2EFF
Attribute Table 3
Name Table 3
Attribute Table 2
Name Table 2Mirrors
$0000-$3FFF
Attribute Table 1
Name Table 1
Attribute Table 0
Name Table 0
$0000
$1000
$2000
$23C0
$2400
$27C0
$2800
$2BC0
$2C00
$2FC0
$3000
$3F00
$3F10
$3F20
$4000
$10000
Name Tables
Palettes
Mirrors
$0000-$3FFF
Pattern Tables
 
Figure 3-1. PPU memory map. 
 
3.3 PPU Registers 
 
Communication between...

 
 
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only be written to. Bit 7 of £2000 can be used to disable NMIs. Remember that this type of 
interrupt is generated whenever a V-Blank occurs and is unaffected by the interrupt disable 
flag of the status register. Clearing this bit will prevent an NMI from occurring on V-Blank. 
Since the NES supports both 8x8 and 8x16 sprites, setting bit 5 of $2000 will switch to 8x16 
sprites. The next address in PPU memory to read or write from will be incremented after 
each I/O occurs. The value to increment...

 
 
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colours in each palette is 13, not 16 [5]. The total number of colours onscreen at any time is 
therefore 25 out of 52. Both palettes are also mirrored to $3F20-$3FFF. The colour palette is 
shown in Appendix F. 
 
3.5 Pattern Tables 
 
The NES has two pattern tables at $0000 and $1000. The pattern tables store the 8x8 pixel 
tiles which can be drawn on the screen. Many games store the pattern tables in CHR-ROM 
on the cartridge, however, games without CHR-ROM will use RAM for the pattern tables...

 
 
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is 33221100 where every two bits specifies the most significant two colour bits for the 
specified square. 
 
Square 0
$0 $1
$2 $3Square 1
$4 $5
$6 $7
Square 2
$8 $9
$A $BSquare 3
$C $D
$E $F
 
 
Figure 3-3. 4x4 tile group layout. Adapted from [20]. 
 
The NES only has 2 KB to store name tables and attribute tables, allowing it to store two of 
each. However it can address up to four of each. Mirroring is used to allow it to do this. There 
are four types of mirroring which are described below,...