Analog Devices Blackfin AV EZExtender Manual Rev 21

Blackfin A-V EZ-Extender Manual 1-5 A-V EZ-Extender Interfaces
J6 is a connector designated for a Micron camera sensor evaluation mod-
ule. The interface has been tested with the Micron MT9V022 camera. For 
information about Micron camera sensors and evaluation boards, go to 
http://www.micron.com.
J4 is a connector designated for an OmniVision camera sensor evaluation 
module. The interface has been tested with the OmniVision OV6630AA 
camera. For information about OmniVision camera sensors and evalua-...

Flat Panel Display Interface
1-6 Blackfin A-V EZ-Extender ManualJP4.7/8)” on page 2-11. Then set the direction of the data and frame sync 
signals, which depend on the camera’s configuration. The data must be set 
as input to the PPI port; refer to “System Architecture” on page 2-2 and 
“Jumpers” on page 2-7 for details.
Before using the camera interfaces, follow the procedure in “A-V 
EZ-Extender Setup” on page 1-2.
Flat Panel Display Interface
The flat panel display interface (FPDI) consists of a...

Blackfin A-V EZ-Extender Manual 1-7 A-V EZ-Extender Interfaces
Example Programs
Example programs are provided with the A-V EZ-Extender EZ-KIT Lite 
to demonstrate various capabilities of the product. The programs are 
included in the product installation kit and can be found in the 
Examples 
folder of the installation. Refer to a readme file provided with each exam-
ple for more information.
CCES users are encouraged to use the example browser to find examples 
included with the EZ-KIT Lite Board...

Example Programs
1-8 Blackfin A-V EZ-Extender Manual 

Blackfin A-V EZ-Extender Manual 2-1 
2 A-V EZ-EXTENDER 
HARDWARE REFERENCE
This chapter describes the hardware design of the Blackfin A-V 
EZ-Extender. 
The following topics are covered.
“System Architecture” on page 2-2
Describes the extender board configuration and explains how the 
board components interface with the processor and EZ-KIT Lite.
“Jumpers” on page 2-7
Describes the configuration jumpers. 

System Architecture
2-2 Blackfin A-V EZ-Extender Manual
System Architecture
A block diagram of the Blackfin A-V EZ-Extender is shown in Figure 2-1. 
Not shown in the diagram is the analog audio interface, which is a simple 
connection between the serial port of the processor and AD1836A audio 
codec. The audio interface connects directly to 
SPORT0 of the expansion 
interface.
In Figure 2-1, unidirectional buffers are show as triangle symbols, while 
bidirectional buffers are shown as two overlapping...

Blackfin A-V EZ-Extender Manual 2-3 A-V EZ-Extender Hardware Reference
Figure 2-1. A-V EZ-Extender Block Diagram 

System Architecture
2-4 Blackfin A-V EZ-Extender ManualTable 2-1 summarizes the signals coming and going on the expansion 
interface connectors. 
Table 2-1. Signals of Expansion Interface Connectors
Net/Bus Name
(Direction)Blackfin A-V EZ-Extender Function Relevant 
Configuration 
Jumpers 
PPI0_D[0:15]
(Bi)Connects the processor’s 
PPI0 data pins to the 
VID_IN_D[0:15] or VID_OUT_D[0:15] buses, depend-
ing on the jumper settings. This allows 
PPI0 to interface 
with all video interfaces on the board. The...

Blackfin A-V EZ-Extender Manual 2-5 A-V EZ-Extender Hardware Reference
PPI1_D10
(Bi)The multifunction net that typically functions as the 
D10 
pin of 
PPI1 but, with a jumper, also can connect to the 
PDWN input of the OmniVision and Kodak camera inter-
faces.
JP3.9/10,
JP5.3/4,
JP5.5/6
PPI1_D2
(Bi)The multifunction net typically functions as the 
D2 pin of 
PPI1 but also can function as the data signal for the pro-
cessor’s 2-wire interface (TWI). Used to program the 
internal configuration registers...

System Architecture
2-6 Blackfin A-V EZ-Extender Manual
MOSI
(Output)The SPI serial output data signal used to program the 
control register of the AD1836A audio codec.
MISO
(Output)The SPI serial input data signal used to read the control 
register of the AD1836A audio codec.
RSCLK0
(Bi)The processor’s 
SPORT0 receive clock signal connected to 
the serial clock on the digital side of the audio codec’s 
analog input. In I
2S mode, the signal can connect to the 
TSCLK0 net.
JP7.1/2
RFS0
(Bi)The...