Casio Qt 6100 Service Manual

							
— 49 —
8-3. RESET CIRCUIT
The reset circuit is as follows.
8-4. POWER SUPPLY CIRCUIT 1
  VP (DC 19V) For the drawer circuit
  VOP (DC 5.2V) For the COM2, 3 power and display ON/OFF LED
  VCC (DC 5V) For the logic circuit power
 
The power supply circuit is as follows. 
						

							
— 50 —
8-5. POWER SUPPLY CIRCUIT 2
  VBAT (DC 3.3V) For the battery
  V1.5 (DC 1.5V) For the CPU core
  V1.8 (DC 1.8V) For the PCMCIA core
 
The power supply circuit is as follows.
8-6. DRAWER I/F CIRCUIT
The drawer open circuit is as follows. 
						

							
— 51 —
8-7. CPU (IC26: SH7751)
8-7-1. Pin Assignment
193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256
XTAL2EXTAL2VDD-RTCVSS-RTCCA
NMI//MD6/
TXD
MD2/RXD2RXDTCLKMD8/SCKMD1/TXD2MD0/SCK2MD7/AUDSYNCAUDCK
AUDATA0AUDATA1
AUDATA2AUDATA3ReservedMD3/MD4/MD5
DACK0DACK1DRAK0DRAK1
STATUS0STATUS1
/BRKACKTDO
VDD-PLL2VSS-PLL2VDD-PLL1VSS-PLL1VDD-CPGVSS-CPGXTALEXTAL
1281271261251241231221211201191181171161151141131121111101091081071061051041031021011009998979695949392919089888786858483828180797877767574737271706968676665
//PCICLK
IDSEL/MD9
/MD10
//A25
A24
A23
A22
A21
A20
A19
A18
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
/DQM3/DQM2
A17
A16
A15
A14
A13
A12
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
TMS
TCK
TDI
/D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15/DQM0/DQM1
RD/CKIO
Reserved
Reserved
/
/CKEA0A1A2A3A4A5A6A7A8A9A10A11
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
C/AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
C/PARC/AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
C/AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
QFP256
(Top view)
VDD (internal)
VSS (internal)
VDDQ (IO)
VSSQ (IO)
Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, 
VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL 
circuits, crystal resonator, and RTC are used. 
						

							
— 52 —
8-7-2. Block Diagram
Lower 32-bit data
64-bit data (store)
CPG
INTC
SCI
(SCIF)
RTC
TMU
External (SH) bus interface
DMAC
32-bit data 29-bit addres
s
32-bit dataAddress
32-bit data
32-bit data
Upper 32-bit data
32-bit address (instructions)
32-bit data (instructions) 32-bit address (data)
Peripheral address bus
26-bit 
SH bus
address32-bit
PCI
address/
data
32-bit 
SH bus
data
Peripheral data bus
UBC
32-bit data (store)
32-bit data (load)
CPU
I cacheO cacheITLB
UTLB
Cache andTLB
controller
FPU
BSC: Bus state controller
CPG: Clock pulse generator
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
UTLB: Unified TLB (translation lookaside buffer)
RTC: Realtime clock
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
PCIC: PCI bus controller
32-bit data
PCIC
BSC
Address
(PCI)DMAC 
						

							
— 53 —
8-7-3. Pin Function
  NO. PIN NAME  I/O  DESCRIPTION
  1  TMS  I  Mode (H-UDI)
  2  TCK I  Clock (H-UDI)
  3  VDDQ Power  IO VDD
  4  VSSQ Power  IO GND
  5  TDI  I  Data in (H-UDI)
  6  CSO O  Chip select 0
  7  CS1 O  Chip select 1
  8  CS4 O  Chip select 4
  9  CS5 O  Chip select 5
  10  CS6 O  Chip select 6
  11  BS O  Bus start
  12  WE0/REG O  D7-D0 select signal
  13  WE1 O  D15-D8 select signal
  14  D0 I/O  Data
  15  VDDQ Power  IO VDD
  16  VSSQ Power  IO GND
  17  VDD Power  Internal VDD
  18  VSS Power  Internal GND
  19  D1
  20  D2
  21  D3
  22  D4
  23  D5 I/O  Data  24  D6
  25  D7
  26  D8
  27  D9
  28  D10
  29  VDDQ Power  IO VDD
  30  VSSQ Power  IO GND
  31  D11
  32  D12
  33  D13  I/O  Data
  34  D14
  35  D15
  36  CAS0/DQM0  O  D7-D0 select signal
  37  CAS1/DQM1 O  D15-D8 select signal
  38  RD/WR O  Read/write
  39  CKIO O  Clock output
  40  Reserved  -  Do not connect
  41  VDDQ Power  IO VDD
  42  VSSQ Power  IO GND
  43  Reserved  -  Do not connect
  44  RD/CASS/FRAME O  Read/CAS/FRAME
  45  CKE O  Clock output enable
  46  RAS O  RAS
  47  VDD Power  Internal VDD
  48  VSS Power  Internal GND
  49  CS2  O  Chip select 2
  50  CS3 O  Chip select 3
  51  A0
  52  A1 O  Address  53  A2
  54  A3 
						

							
— 54 —
  NO. PIN NAME  I/O  DESCRIPTION
  55  VDDQ  Power  IO VDD
  56  VSSQ Power  IO GND
  57  A4
  58  A5
  59  A6
  60  A7
  61  A8 O  Address  62  A9
  63  A10
  64  A11
  65  A12
  66  A13
  67  VDDQ Power  IO VDD
  68  VSSQ Power  IO GND
  69  A14
  70  A15 O  Address  71  A16
  72  A17
  73  CAS2/DQM2  O  D23-D16 select signal
  74  CAS3/DQM3 O  D31-D24 select signal
  75  D16
  76  D17 I/O  Data  77  D18
  78  D19
  79  VDDQ Power  IO VDD
  80  VSSQ Power  IO GND
  81  VDD Power  Internal VDD
  82  VSS Power  Internal GND
  83  D20
  84  D21
  85  D22
  86  D23
  87  D24 I/O  Data  88  D25
  89  D26
  90  D27
  91  D28
  92  D29
  93  VDDQ Power  IO VDD
  94  VSSQ Power  IO GND
  95  D30 I/O  Data  96  D31
  97  VDD Power  Internal VDD
  98  VSS Power  Internal GND
  99  A18
  100  A19
  101  A20 O  Address  102  A21
  103  A22
  104  A23
  105  VDDQ Power  IO VDD
  106  VSSQ Power  IO GND
  107  A24 O  Address  108  A25
  109  WE2/ICIORD  O  D23-D16 select signal 
						

							
— 55 —
  NO. PIN NAME  I/O  DESCRIPTION
  110  WE3/ICIOWR  O  D31-D24 select signal
  111  VDD Power  Internal VDD
  112  VSS Power  Internal GND
  113  SLEEP  I  Sleep
  114  PCIGNT4 O  Bus grant (host function)
  115  PCIGNT3 O  Bus grant (host function)
  116  PCIGNT2 O  Bus grant (host function)
  117  PCIREQ4  I*  Bus request (host function)
  118  PCIREQ3/MD10 I*  Bus request (host function)/mode
  119  VDDQ Power  IO VDD
  120  VSSQ Power  IO GND
  121  PCIREQ2/MD9  I*  Bus request (host function)/mode
  122  IDSEL  I  Configuration device select
  123  INTA O  Interrupt (async)
  124  PCIRST O  Reset output
  125  PCICLK  I  PCI input clock
  126  PCIGNT1/REQOUT O  Bus grant (host function)/bus request
  127  PCIREQ1/GNTIN  I  Bus request (host function)/bus grant
  128  SERR I/O  System error
  129  AD31 I/O  PCI address/data/port
  130  AD30 I/O  PCI address/data/port
  131  VDDQ Power  IO VDD
  132  VSSQ Power  IO GND
  133  AD29
  134  AD28
  135  AD27 I/O  PCI address/data/port  136  AD26
  137  AD25
  138  AD24
  139  C/BE3  I/O  Command/byte enable
  140  AD23
  141  AD22 I/O  PCI address/data/port
  142  AD21
  143  VDDQ Power  IO VDD
  144  VSSQ Power  IO GND
  145  VDD Power  Internal VDD
  146  VSS Power  Internal GND
  147  AD20
  148  AD19
  149  AD18  I/O  PCI address/data/port
  150  AD17
  151  AD16
  152  C/BE2 I/O  Command/byte enable
  153  PCIFRAME I/O  Bus cycle
  154  IRDY I/O  Initiator ready
  155  TRDY I/O  Target read
  156  DEVSEL I/O  Device select
  157  VDDQ Power  IO VDD
  158  VSSQ Power  IO GND
  159  PCISTOP  I/O  Transaction stop
  160  PCILOCK  I/O  Exclusive access
  161  PERR  I/O  Parity error
  162  PAR I/O  Parity
  163  C/BE1 I/O  Command/byte enable
  164  AD15 I/O  PCI address/data/port 
						

							
— 56 —
  NO. PIN NAME  I/O  DESCRIPTION
  165  AD14
  166  AD13 I/O  PCI address/data/port  167  AD12
  168  AD11
  169  VDDQ  Power  IO VDD
  170  VSSQ Power  IO GND
  171  AD10
  172  AD9  I/O  PCI address/data/port
  173  AD8
  174  C/BE0 I/O  Command/byte enable
  175  VDD Power  Internal VDD
  176  VSS Power  Internal GND
  177  AD7
  178  AD6
  179  AD5 I/O  PCI address/data/port  180  AD4
  181  AD3
  182  AD2
  183  VDDQ Power  I/O VDD
  184  VSSQ Power  I/O GND
  185  AD1  I/O  PCI address/data/port
  186  AD0 I/O  PCI address/data/port
  187  IRL0   I  Interrupt 0
  188  IRL1  I  Interrupt 1
  189  IRL2  I  Interrupt 2
  190  IRL3 I  Interrupt 3
  191  VSSQ Power  I/O GND
  192  VDDQ Power  I/O VDD
  193  XTAL2  O  RTC crystal resonator pin
  194  EXTAL2  I  RTC crystal resonator pin
  195  VDD-RTC Power  RTC VDD
  196  VSS-RTC Power  RTC GND
  197  CA  I  Hardware standby
  198  RESET I  Reset
  199  TRST I  Reset (H-UDI)
  200  MRESET I  Manual reset
  201  NMI I  Nonmaskable interrupt
  202  BACK/BSREQ O  Bus acknowledge/bus request
  203  BREQ/BSACK  I  Bus request/bus acknowledge
  204  MD6/IOIS16 I  Mode/IOIS16 (PCMCIA)
  205  RDY I  Bus ready
  206  TXD O  SCI data output
  207  VDDQ Power  IO VDD
  208  VSSQ Power  IO GND
  209  VDD Power  Internal VDD
  210  VSS Power  Internal GND
  211  MD2/RXD2  I  Mode/SCIF data input
  212  RXD I  SCI data input
  213  TCLK I/O  RTC/TMU clock
  214  MD8/576  I/O  Mode/SCIF data control (RTS)
  215  SCK  I/O  SCIF clock
  216  MD1/TXD2 I/O  Mode/SCIF data output
  217  MD0/SCK2 I/O  Mode/SCIF clock
  218  MD7/CTS2 I/O  Mode/SCIF data control (CTS) 
						

							
— 57 —
  NO. PIN NAME  I/O  DESCRIPTION
  219  AUDSYNC  -  AUD sync
  220  AUDCK -  AUD clock
  221  VDDQ Power  IO VDD
  222  VSSQ Power  IO GND
  223  AUDATA0 -  AUD data  224  AUDATA1
  225  VDD Power  Internal VDD
  226  VSS Power  Internal GND
  227  AUDATA2 -  AUD data  228  AUDATA3
  229  Reserved  -  Do not connect
  230  MD3/CE2A I/O  Mode/PCMCIA-CE
  231  MD4/CE2B I/O  Mode/PCMCIA-CE
  232  MD5  I  Mode MD5
  233  VDDQ Power  IO VDD
  234  VSSQ Power  IO GND
  235  DACK0  O  DMAC0 bus acknowledge
  236  DACK1 O  DMAC1 bus acknowledge
  237  DRAK0 O  DMAC0 request acknowledge
  238  DRAK1 O  DMAC1 request acknowledge
  239  VDD Power  Internal VDD
  240  VSS Power  Internal GND
  241  STATUS0 O  Status  242  STATUS1
  243  DREQ0  I  Request from DMAC0
  244  DREQ1 I  Request from DMAC1
  245  ASEBRK/BRKACK I/O  Pin break/acknowledge (H-UDI)
  246  TDO  O  Data out (H-UDI)
  247  VDDQ Power  IO VDD
  248  VSSQ Power  IO GND
  249  VDD-PLL2 Power  PLL2 VDD
  250  VSS-PLL2 Power  PLL2 GND
  251  VDD-PLL1 Power  PLL1 VDD
  252  VSS-PLL1 Power  PLL1 GND
  253  VDD-CPG Power  CPG VDD
  254  VSS-CPG Power  CPG GND
  255  XTAL  O  Crystal resonator
  256  EXTAL  I  External input clock/crystal resonator
I:  InputO:  OutputI/O:  Input/outputPower:  Power supplyNotes:  1.  Except in hardware standby mode, supply power to all power pins. In hardware standby mode, supply power to RTC as a minimum.  2.  Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not the on-chip PLL circuits are used.  3.  Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the on-chip crystal resonator is used.  4.  Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the on-chip RTC is used.  5.  For the handling of the PCI bus pins in PCI-disabled mode, see table D.4 in appendix D.  *   I/O attribute is I/O when used as a port. 
						

							— 58  —
8- 8. G/A (IC14: uPD65945GJ-093-JEU)
8- 8-1. Pin Function
PIN NO PIN NAME I / O DESCRIPTINPIN NO PIN NAME I / O DESCRIPTIN1 VDD VDD VDD 73 VDD VDD VDD
2  GD0 I/O ARC DATA (D0) 74 CLKOUT OCLOCK 8MHz
3  GD1 I/O ARC DATA (D1) 75  CLKIN I CLOCK  8MHz
4  GD2 I/O ARC DATA (D2) 76 GND I GND
5  GD3 I/O ARC DATA (D3) 77  CS I C hip Select 5
6  GD4 I/O ARC DATA (D4) 78   A0 I ADDRESS  (A1)
7 TVDD VDD VDD 79  A1 I ADDRESS (A2)
8 TGND GND GND 80  A2 I ADDRESS (A3)
9  GD5 I/O ARC DATA (D5) 81   A3 I GND
10  GD6 I/O ARC DATA (D6) 82   A23 I ADDRESS  (A23)
11  GD7 I/O ARC DATA (D7) 83   A20 I ADDRESS  (A20)
12  GD8 I/O VDD 84   A21 I ADDRESS  (A21)
13  GD9 I/O VDD 85   A22 I ADDRESS  (A22)
14 TGND GND GND 86  RD I IO READ
15  GD10 I/O VDD 87   WE I IO WRITE
16  GD11 I/O VDD 88 INT6 I INT for ARC
17  GD12 I/O VDD 89  INT7 I Int for PCMCIA
18  GD13 I/O VDD 90 TVDD VDD VDD
19  GD14 I/O VDD 91   RESET IRESET
20 TVDD VDD VDD 92  RD_WE I READ/WRITE  signal
21 TGND GND GND 93  TESTB I VDD
22  GD15 I/O VDD 94   U 1_CTSB I CST2
23  GA0 O ARC ADDRESS (A0) 95  U1_DSRB I DSR2
24  GA1 O ARC ADDRESS (A1) 96  U1_SIN I RXD2
25  GA2 O ARC ADDRESS (A2) 97  U1_DTRB O DTR2
26  GA3 O Not  used 98  U1_RTSB O RTS2
27 TGND GND GND 99  U1_SOUT O TXD2
28  D0 I/O DATA (D0) 100  U2_CTSB I CTS3
29  D1 I/O DATA (D1) 101   U2_DSRB I DSR3
30  D2 I/O DATA (D2) 102  U2_SIN I RXD3
31 TVDD VDD VDD 103  U2_DTRB O DTR3
32 TGND GND GND 104  U2_RTSB O RTS3
33  D3 I/O DATA (D3) 105  U2_SOUT O TXD3
34  D4 I/O DATA (D4) 106  U3_CTSB I CTS4
35  D5 I/O DATA (D5) 107   U3_DSRB I DSR4
36 VDD VDD VDD 108 VDD VDD VDD
3 7 GND GND GND 1 0 9 GND GND GND
3 8 GND GND GND 1 1 0 GND GND GND
39  D6 I/O DATA (D6) 111  U3_SIN I RXD4
40  D7 I/O DATA (D7) 112  U3_DTRB O DTR4
41  D8 I/O VDD 113  U3_RTSB O RTS4
42 TGND GND GND 114  U3_SOUT O TXD4
43  D9 I/O VDD 115  U4_CTSB I VDD
44  D10 I/O VDD 116  U4_DSRB I VDD
45  D11 I/O VDD 117  U4_SIN I VDD
46 TVDD VDD VDD 118  U4_DTRB O NOT USED
47 TGND GND GND 119  U4_RTSB O NOT USED
48  D12 I/O VDD 120  U4_SOUT O NOT USED
49  D13 I/O VDD 121  U5_CTSB I VDD
50  D14 I/O VDD 122  U5_DSRB I VDD
51 TGND GND GND 123  U5_SIN I VDD
52  D15 I/O VDD 124  U5_DTRB O NOT USED
53  INTC2 O INT for ARC 125   U5_RTSB O NOT USED
54  INTC1 O INT for UART 126  U5_SOUT O NOT USED
55  GCS1 O Chip Select for ARC 127 TVDD VDD VDD
56  GCS2 O EST-CS 128   PCMIN I PCMCD1
57  GRD O Read signal for ARC 129  CE1B I CE1
58  GWE O Write signal for ARC 130  CE2B I CE2
59  PCIN O PCMCIA IN/OUT signal 131  CFIN I CFCD1
60  PCMG O Enable for PCMCIA 132  CE1A I CE1
61  CFCE1A O Chip Enable1 for CF CARD 133  CFCE I ADDRESS (A23)
62  CIN O CF CARD IN/OUT signal 134   CE2A I CE2
63  CFG O Enable for CF CARD 135  BFI1 I CI1
64  CFCE2A O Chip Enable2 for CF CARD 136  BFI2 I CD1
65  ANDO1 O WAIT  signal 137  BFI3 IRXD1
66  ANDO2 O DSR 138  BFI4 I CTS1
67  BFO1 O CI 139   ANDI1 I WAIT for CF CARD
68  BFO2 O CD  140   ANDI2 I WAIT for PCMCIA
69  BFO3 O RXD 141   ANDI3 IDSR1
70  BFO4 O CTS 142   ANDI4 IDSR1
7 1 GND GND GND 1 4 3 GND GND GND
7 2 GND GND GND 1 4 4 GND GND GND