Casio Qt 6100 Service Manual
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— 79 — 2. ALVCH16245 (IC8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1DIR 1B1 1B2 GND 1B3 1B4 VCC1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 VCC2B5 2B6 GND 2B7 2B8 2DIR 1OE 1A1 1A2 GND 1A3 1A4 VCC1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC2A5 2A6 GND 2A7 2A8 2OE To Seven Other Channels 1DIR 1A1 1B1 1OE 1 47 48 2 logic diagram (positive logic) terminal assignments 1234 56 A1DIRNCNCNCNC1OE B1B21B1GNDGND1A11A2 C1B41B3V CCVCC1A31A4 D1B61B5GNDGND1A51A6 E1B81B71A71A8 F2B12B22A22A1 G2B32B4GNDGND2A42A3 H2B52B6VCCVCC2A62A5 J2B72B8GNDGND2A82A7 K2DIRNCNCNCNC2OE NC No internal connection FUNCTION TABLE (each 8-bit section) INPUTSOPERATIONOEDIROPERATION LLB data to A bus LH A data to B bus HXIsolation
— 80 — 3. BR93L46RF (IC35) Vcc NC NC GND CS SK DI DO Pin Name I/O Function Vcc - Power Supply GND - GND CS INPUT Chip Selct SK INPUT Serial Clock Input DI INP Start bit,Cord,Address,Serial data DO OUTPUT Serial data input, READY/BUSY status 4. HD74LV00 (IC29) 1 2 3 4 5 7 6 1A 1B 1Y 2A 2B GND 2Y VCC 4B 4A 4Y 3B 3Y 3A 14 13 12 11 10 8 9 5. HD74LV74 (IC25) TG C C TG C TG C C C C TG C C PRE CLK D CLR Q Q C logic diagram, each flip-flop (positive logic) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1CLR 1D 1CLK 1PRE 1Q 1Q GND VCC 2CLR 2D 2CLK 2PRE 2Q 2Q FUNCTION TABLE INPUTSOUTPUTS PRECLRCLKDQQ LHXXHL HL X X LH LL XX H*H* HH H HL HH L LH HHLXQ0Q0*This configuration is nonstable; that is, it does notpersist when PRE or CLR returns to its inactive(high) level.
— 81 — 6. HD74LVC08 (IC20) 8. HD74LVC244 (IC4,5) 11 12 13 14VCC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 78 9 10 1A GND 1B 1Y 2A 2B 2Y 3Y 11 12 13 14 VCC1 2 3 4 5 6 7 10 A GND 89 15 16 AB C Y7 G1 G2B G2A Y0 Y1 Y2 Y3 Y4 Y5 B C G2A G2B G1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Y6 7. HD74LVC138 (IC11) 11G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND Vcc 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Inputs GA H X L H L LOutput Y Z H L H : High L�: Low X�: Don’t care Z�: High impedance 1T/R A0 A1 A2 A3 A4 A5 A6 A7 GND Vcc OE B0 B1 B2 B3 B4 B5 B6 B7 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Inputs OET / R L L L H H X Output Y Bus B Data to Bus A Bus A Data to Bus B Z H : High L : Low X : Dont care Z : High impedance 9. HD74LVC245 (IC6,7)
— 82 — 10. HIN202CBNZ-T (IC24) 11. HIN211CAZ-T (IC3,9,23,27) 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 C1+V+ C1- C2+ C2- R2 IN T2OUT VCC T1OUT R1IN R1OUT T1IN T2IN R2OUT GND V- VCC +5V 2 V+ 16 T1 OUT T2OUT T1IN T2IN T1T2 11 10 14 7 +5V 400k +5V 400k R1OUTR1INR1 13 12 5k R2OUTR2INR2 895k +10V TO -10V VOLTAG E INVERTER 0.1 F6 V- C2+ C2-+ 0. 1 F4 5 +5V TO 10V VOLTAG E INVERTER C1+ C1-+ 0. 1 F1 3+0. 1 F + GND 15 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- T4 OUT R3OUT SD EN R4IN T4IN R5OUT R5IN V- C2- C2+ R3 IN R4OUT T3IN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 11VCC+5V TO 10V VOLTA GE DOUBLER +10V TO -10V VOLTAG E INVERTER T1 OUT T2OUT T3OUT T1IN T2IN T3IN T1 T2 T3 +5V + 0. 1 F +0. 1 F + 0. 1 F 7 6 2 3 20 1 12 14 13 17 V+ V - C1 + C1 - C2 + C2 - +5V 400k +5V 400k +5V400k + 0. 1 F 15 16 R1OUTR1INR1 9 5k R2OUTR2INR2 45 5k R3OUTR3INR327 26 5k R4OUTR4INR423 22 5k R5OUTR5INR518 19 5kEN24 8 T4 OUTT4IN T4 21 28 +5V 400k SD 25GND 10
— 83 — 12. IDT2305 (IC40) P LL 8C LK 1 C L K2 C L K3 C L K4 C ontrol L o g ic R EF C L K O U T 13 2 5 7 REF CLK 1 2 3 4 8 7 6 5 1 CLK2 GND CLKOUT CLK4 VDD CLK FUNCTIONALBLOCKDIAGRAM 13. M51957BFP (IC33) INPUT OUTPUT GND 1.25V 5uA 25uA + -- POWER DELAY VALUE NC INPUTNC GN D POWE R OUTPUT NC DELAY VALUE 1 2 3 45 6 7 8 14. RTC-7301DG (IC19) 1 2 3 4 5 7 6 8 VDD VDD CS1 D0 D1 D2 D3 9WR VDD CS0 IRQ A0 A1 A2 A3 RD GND FOUT 14 15 16 17 18 13 12 11 10 32.768 kHz 7301SF 7301D G OSC DIVIDER Digital Trimming REGISTER CLOCK and CALENDA R TIMER REGISTER ALAR M REGISTER CONTROL REGISTER SYSTEM REGISTER FOUT CONTROLLER INTERRUPTS CONTROLLER BUS INTERFACE CIRCUI T Temperature Sensor VTEMP FOUTFCON IRQ A0 - A3D0 - D3WRRDCS0CS1 *1 Control Line and
— 84 —
15. S-80828CLNB-B6N-T2 (IC55)
OUT
V
+
-
DD
VSS
VRF.F
*
*
2
4
1
4 3
1 2
VNC
OUTVDD
SS
16. SG-8002JFSCB14.318M (IC41): Programmable High-Frequency Crystal Oscillator (14.318 MHz)
SG-8002JFSCB33M (IC43): Programmable High-Frequency Crystal Oscillator (33 MHz)
17. SN74AHCT08 (IC49)
11
12
13
14VCC
4B
4A
4Y
3B
3A
1
2
3
4
5
6
78
9
10
1A
GND
1B
1Y
2A
2B
2Y
3Y
— 85 — 19. SN74LV04APWR (IC10) 1 2 3 4 5 6 7 8 16 15 14 13 1211 10 9 4 5 6 7 EI A2 A1 GND VCC EO GS 3 2 1 0 A0 logic diagram (positive logic) 11 A09 1 A17 A26 GS14 EO15 122 133 14 25 5EI 47 36 100 FUNCTION TABLE INPUTSOUTPUTS EI01234567A2A1A0GSEO HXXXXXXXXHHHHH LHH H H H H H H HH HHL LXX X X X X X L LL LLH LXX X X XX LH LL HLH LXX X X X L HH LH LLH LXX X X LH H H LH HLH LXX X L HH H H HL LLH LXX L H H H H H HL HLH LXL HH H H H H HH LLH LLHHHHHHHHHHLH 1A 1Y 2A 2Y 1 2 3 4 5 7 6 3A GND 3Y VCC 6A 6Y 5A 5Y 4Y 4A 14 13 12 11 10 8 9 18. SN74HC148 (IC32) 20. SSN74LV07A (IC37) AY 1A 1Y 2A 2Y 1 2 3 4 5 7 6 3A GND 3Y VCC 6A 6Y 5A 5Y 4Y 4A 14 13 12 11 10 8 9
— 86 — 21. SN74LV08APWR (IC47,57) 11 12 13 14VCC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 78 9 10 1A GND 1B 1Y 2A 2B 2Y 3Y 22. SN74LV10APWR (IC30) 11 12 13 14VCC 1C 1Y 3C 3B 3A 1 2 3 4 5 6 78 9 10 1A GND 1B 2A 2B 2C 2Y 3Y ABYC 23. SN74LV244APWR (IC22,38,39) 11G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND Vcc 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 1211 Inputs GA H X L H L LOutput Y Z H L H : High L�: Low X�: Don’t care Z�: High impedance 24. SN74LV32APWR (IC48,52~54) 11 12 13 14VCC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 78 9 10 1A GND 1B 1Y 2A 2B 2Y 3Y
— 87 — 25. SN74LV374APWR (IC16,21,50,51) 1Q 1D1DC1 CLK OE 1 2 113 1 20 2 1 9 3 1 8 4 1 7 5 1 6 6 1 5 7 1 4 8 1Q 1D 2Q 2D 3Q 3D 4Q13Vcc FUNCTION T ABLE 8Q 8D 7D 7Q 6D 6Q 5D 9 12 10 4D GND 11 5Q OE CLK OE INPUTSOUTPUT Q H L Q0 Z CLK D L L L H H L X X L X 26. SN74LVC1G08 (IC56) 11 12 13 14VCC 4B 4A 4Y 3B 3A 1 2 3 4 5 6 78 9 10 1A GND 1B 1Y 2A 2B 2Y 3Y 27. SN74LVC1G97 (IC58,59) 2 In1 GND In0 In2 VCCY3 5 6 4 1 FUNCTION TABLE INPUTSOUTPUT In2In1In0Y LLLL LL HL LH LH LH HH HL LL HL HH HH LL HHHH logic diagram (positive logic) 3 1 6In2 In1 In0 4Y
— 88 — 28. XC6206P182MR (IC34) PIN ASSIGNMENT BLOCK DIAGRAM NAMEGround VOUT Power Input VIN PIN NUMBER PIN FUNCTION 2 3 VSS 1 Output12 3 VI N VOUT VSS Cu rrent Lim it Voltage Reference VINVOUT VSS 29. XC6219B332MR (IC46) PIN ASSIGNMENT BLOCK DIAGRAM NAME Input VSS PIN NUMBER PIN FUNCTION2 VIN 1 Ground ON/OFF Control NC OutputVOUT 4 5 CE3 No Connection CurrentLimit ON/OFFControl VoltageReference each circuit CE VSS VOUT VIN R2 R1 4 2 3 1 5 CE (N C)VINVSS VOUT