Fujitsu Series 3 Manual

FUJITSU SEMICONDUCTOR LIMITED 
2.  Clock Generation Unit Configuration/Block Diagram 
This section explains configuration of the clock generation unit. 
 Source clock 
Source clock is the generic name fo r external and internal oscillation clocks of this MCU. The following 
five types of clocks are source clocks: 
  Main clock (CLKMO) 
CLKMO is generated by connecting a crystal oscillator to  the main oscillation pins (X0, X1), or input using 
an external clock. 
  Sub clock (CLKSO) 
CLKSO is...

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 APB2 bus clock (PCLK2) 
PCLK2 is a clock for peripheral macro connected to the APB2 bus. 
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. 
This clock stops in timer mode or stop mode. 
The supply of the clock can be also stopped by setting a register. 
  TPIU clock (TPIUCLK) 
TPIUCLK is a clock for TRACE. 
The clock frequency can be set to between 1/1 and 1/2 frequency of the base clock. 
This clock stops in timer mode or stop mode....

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 Block diagram 
Figure 2-1  shows the block diagram of the clock generation unit. 
Figure 2-1 Clock generation unit block diagram 
CPU
Cortex-M3
HCLK_core FCLK
SLEEPING
/
EN
x0
x1Main 
oscillation  circuit
High-speed 
CR oscillation 
circuit
Sub 
oscillation  circuit
Low-speed 
CR oscillation 
circuit
Master clock
Base clock (HCLK)
PCLK2
CLKPLLCLKMO
CLKHC
CLKSOCLKLC
K frequency  division
N frequency  division
DIV 1/1 to  1/16 
frequency
(default 1)
CLKPLL
M frequency...

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3.  Clock Generation Unit Operations 
This section explains the clock generation unit. 
3.1.  Selecting the clock mode 
 Definition of clock mode ( selecting the master clock) 
The MCU clock mode is defined by the source clock selected by the system clock mode control register. 
Five types of clock modes are provided: Main clock mode, sub clock mode, high-speed CR clock mode, 
low-speed CR clock mode, and PLL clock mode. 
 Main clock mode 
In main clock mode, the main...

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3.2.  Internal bus clock frequency division control 
This section explains the internal bus clock frequency division. 
Frequency division ratio vs. the base clock can be set independently for each internal bus clock. 
This function can set the operating frequency optimized for each circuit. 
Ta b l e  3 - 1 shows the internal bus clock. 
The fol lowing
 fi

ve types of internal bus clock frequency divisions can be selected. 
Table 3-1 Internal bus clock list 
 Internal bus...

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3.3.  PLL clock control 
This section explains the PLL clock control. 
The PLL Clock Control Circuit is used to generate the main clock. The PLL Oscillation Circuit can 
enable/disable operation (oscillation), select the input clock, set the stabilization wait time, and set the 
multiplication. 
 PLL operation 
The following explains operation of the PLL clock. 
  Configure the following settings using the PLL Clock Oscillation Stabilization Wait Time Setup Register...

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 Setting the multiplication ratio  to generate the PLL clock 
Each frequency division clock in the PLL Multiplicati on Circuit must be set using PLL Control Register 1 
(PLL_CTL1) and PLL Control Register 2 (PLL_CTL2). The following  Ta b l e  3 - 2 provides example 
frequency divisi on

 settings. 
Table 3-2 Example PLL multiplication ratio settings 
Input clock K PLLin N PLLout M CLKPLL 
4MHz  1 4MHz 20 80MHz  1 80MHz 
4MHz  1 4MHz 15 60MHz  1 60MHz 
4MHz  1 4MHz 15...

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3.4.  Oscillation stabilization wait time 
This section explains the oscillation stabilization wait time. 
An oscillation stabilization wait time is required if the source clock is not in a stable operating state. During 
the oscillation stabilization wait time, internal and external clocks stop the supply, only the internal time 
counter operates to wait until the stabilization wait time passes, a time value set in the Clock Stabilization 
Wait Time Register (CSW_TMR) or...

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3.5. Interrupt causes 
This section explains interrupt causes relevant to clocks. 
The clock generation unit has the following interrupt causes. 
 Interrupt causes 
The clock generation unit has the following four types of interrupt causes: 
  FCS interrupt (anomalous frequency detection interrupt) 
When the FCS (anomalous frequency detection) is enabled, and an anomalous frequency of the main 
clock is detected, an interrupt occurs. 
     PLL clock oscillation...

4.  Clock Setup Procedure Examples 
This section explains procedure examples of setting up clocks. 
 Setup procedure examples 
Figure 4-1 Example clock setup procedure (Power-on -> High-speed CR run mode -> Desired 
clock mode) 
 
Access the Clock Stabilization Wait Time Register 
(CSW_TMR). Set the main oscillation stabilization 
wait time. 
Access the Interrupt Enable Register (INT_ENR).  Set the oscillation stabilization wait interrupt. 
Ye s   No 
High-speed CR/low-speed CR oscillation stabilization...