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2.  Clock Generation Unit Configuration/Block Diagram 
This section explains configuration of the clock generation unit. 
 Source clock 
Source clock is the generic name fo r external and internal oscillation clocks of this MCU. The following 
five types of clocks are source clocks: 
  Main clock (CLKMO) 
CLKMO is generated by connecting a crystal oscillator to  the main oscillation pins (X0, X1), or input using 
an external clock. 
  Sub clock (CLKSO) 
CLKSO is generated by connecting a crystal oscillation to the sub oscillator pins (X0A, X1A), or input 
using an external clock. 
  High-speed CR clock (CLKHC) 
CLKHC is an output clock for the internal high-speed CR oscillator. 
  Low-speed CR clock (CLKLC) 
CLKLC is an output clock for the internal low-speed CR oscillator. 
  PLL clock (CLKPLL) 
CLKPLL is generated by multiplying an oscillation clock using the PLL Clock Multiplication Circuit (PLL 
Oscillation Circuit). 
  Master clock 
The signal selected from source clocks ar e referred to as the master clock. 
The master clock is a source for all bus clocks. 
  Internal bus clocks 
The following signals are bus clocks generated internally. 
  Base clock (HCLK/FCLK) 
HCLK and FCLK are collectively called the base clock.  Both FCLK and HCLK are supplied to the CPU. 
HCLK is a clock for macro connected to the AHB bus. 
The clock frequency can be set to between 1/1 and 1/16 frequency of the master clock. 
This clock stops in timer mode or stop mode. 
In sleep mode, the CPU stops the supply of HCLK while continuing the supply of FCLK. 
  APB0 bus clock (PCLK0) 
PCLK0 is a clock for peripheral macro connected to the APB0 bus. 
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. 
This clock stops in timer mode or stop mode. 
  APB1 bus clock (PCLK1) 
PCLK1 is a clock for peripheral macro connected to the APB1 bus. 
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. 
This clock stops in timer mode or stop mode. 
The supply of the clock can be also stopped by setting a register. 
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 APB2 bus clock (PCLK2) 
PCLK2 is a clock for peripheral macro connected to the APB2 bus. 
The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. 
This clock stops in timer mode or stop mode. 
The supply of the clock can be also stopped by setting a register. 
  TPIU clock (TPIUCLK) 
TPIUCLK is a clock for TRACE. 
The clock frequency can be set to between 1/1 and 1/2 frequency of the base clock. 
This clock stops in timer mode or stop mode. 
This clock output is enabled only for the products equipped with ETM. 
  Clocks other than source clocks and internal bus clocks 
  USB-PLL clock 
This clock runs at 48 MHz,  used for operating USB. 
The PLL clock is generated by setting the USB-PLL oscillator. 
This clock stops in timer mode or stop mode. 
This clock can be set the frequency independently without depending on the frequency of master clock 
setting. 
For USB-PLL operation settings, see Chapter USB clock generation. 
  CAN prescaler clock 
This clock is the same clock as  CLKPLL, used for CAN prescaler. 
The frequency division used  for the clock must be configured on the prescaler side. 
This clock stops in stop mode.   
The supply of the clock can be also stopped by setting a register. 
For operation settings of CAN prescaler, see Chapter CAN Prescaler. 
  Software watchdog timer c ounter clock (SWDOGCLK) 
SWDOGCLK is a clock for the software watc hdog timer connected to the APB0 bus. 
The clock frequency can be set to between 1/1 and 1/8 frequency of the APB0 bus clock. 
This clock stops in timer mode or stop mode. 
For operation settings of the software watchdog timer, see Chapter Watchdog Timer. 
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 Block diagram 
Figure 2-1  shows the block diagram of the clock generation unit. 
Figure 2-1 Clock generation unit block diagram 
CPU
Cortex-M3
HCLK_core FCLK
SLEEPING
/
EN
x0
x1Main 
oscillation  circuit
High-speed 
CR oscillation 
circuit
Sub 
oscillation  circuit
Low-speed 
CR oscillation 
circuit
Master clock
Base clock (HCLK)
PCLK2
CLKPLLCLKMO
CLKHC
CLKSOCLKLC
K frequency  division
N frequency  division
DIV 1/1 to  1/16 
frequency
(default 1)
CLKPLL
M frequency 
divisionPLL
Analog
regTPIUCLK
PCLK0DIV 1/1 to  1/8 
frequency
(default 1)
PCLK1DIV 1/1 to  1/8 
frequency
(default 1)
DIV 1/1 to  1/8 
frequency
(default 1)
FB IN OUT
USB PLL clock
DIV 1/1 to 
1/2 
frequency
(default 1)
X0A
X1A CAN prescaler clock
SWDOGCLKDIV 1/1 to 
1/8 
frequency
(default 1)
Source clock
 
 
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3.  Clock Generation Unit Operations 
This section explains the clock generation unit. 
3.1.  Selecting the clock mode 
 Definition of clock mode ( selecting the master clock) 
The MCU clock mode is defined by the source clock selected by the system clock mode control register. 
Five types of clock modes are provided: Main clock mode, sub clock mode, high-speed CR clock mode, 
low-speed CR clock mode, and PLL clock mode. 
 Main clock mode 
In main clock mode, the main clock (CLKMO) is used as a master clock. The clock runs a bus clock used to 
operate the CPU, and most peripheral functions. 
Status of the PLL clock (CLKPLL) differs depending on the setting of the PLLE bit in the System Clock 
Mode Control Register (SCM_CTL), and the sub clock (CLKSO) depends on the SOSCE bit in the System 
Clock Mode Control Register (SCM_CTL). The high-speed CR clock (CLKHC) and low-speed CR clock 
(CLKLC) cannot be stopped by user program. 
  Sub-clock mode 
In sub clock mode, the sub clock (CLKSO) is used as a master clock. The clock runs a bus clock used to 
operate the CPU, and most peripheral functions. 
The main clock (CLKMO), high-speed CR clock (CLKHC), and PLL clock (CLKPLL) are stopped by 
hardware. The low-speed CR clock (CLKLC) cannot be stopped by user program. 
  High-speed CR clock mode 
In high-speed CR clock mode, the internal high-speed  CR clock (CLKHC) is used as a master clock. The 
clock runs a bus clock used to operate the CPU, and most peripheral functions. 
Statuses of the main clock (CLKMO), PLL clock (CLKPLL), and sub clock (CLKSO) differ depending on 
the settings of MOSCE, PLLE, and SOSCE bits in the System Clock Mode Control Register (SCM_CTL). 
The high-speed CR clock (CLKHC) and low-speed CR clock (CLKLC) cannot be stopped by user program. 
  Low-speed CR clock mode 
In low-speed CR clock mode, the internal low-speed  CR clock (CLKLC) is used as a master clock. The 
clock runs a bus clock used to operate the CPU, and most peripheral functions. 
In low-speed CR clock mode, the main clock (CLKMO), high-speed CR clock (CLKHC), and PLL clock 
(CLKPLL) are stopped by hardware. Status of the su b clock (CLKSO) differs depending on the setting of 
the SOSCE bit in the System Clock Mode Control Register (SCM_CTL). 
  PLL clock mode 
In PLL clock mode, the PLL clock (CLKPLL) is used as a master clock. The clock runs a bus clock used to 
operate the CPU, and most peripheral functions. 
Status of the sub clock (CLKSO) differs depending on the setting of the SOSCE bit in the System Clock 
Mode Control Register (SCM_CTL). The high-speed CR clock (CLKHC) and low-speed CR clock 
(CLKLC) cannot be stopped by user program. 
 
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3.2.  Internal bus clock frequency division control 
This section explains the internal bus clock frequency division. 
Frequency division ratio vs. the base clock can be set independently for each internal bus clock. 
This function can set the operating frequency optimized for each circuit. 
Ta b l e  3 - 1 shows the internal bus clock. 
The fol lowing
 fi

ve types of internal bus clock frequency divisions can be selected. 
Table 3-1 Internal bus clock list 
 Internal bus clock name Source clock  Maximum operating 
frequency 
1  Base clock (HCLK/FCLK)  1/1 to 1/16 frequency of the master clock 80 MHz 
2 APB0 bus clock (PCLK0)  1/1 to 1/8 frequency of the base clock  40 MHz 
3 APB1 bus clock (PCLK1)  1/1 to 1/8 frequency of the base clock  40 MHz 
4 APB2 bus clock (PCLK2)  1/1 to 1/8 frequency of the base clock  40 MHz 
5 TRACE clock (TPIUCLK)  1/1 to 1/2 frequency of the base clock  80 MHz 
 
To set the frequency division ratio of internal bus clocks, use the Base Clock Prescaler Register (BSC_PSR), 
APB0 Prescaler Register (APBC0_PSR), APB1  Prescaler  Register (APBC1_PSR), APB2 Prescaler Register 
(APBC2_PSR), and Trace Clock Prescaler Register  (TTC_PSR). For details on each register, see 5. Clock 
Gen eration Unit Register List
. 
 Setting the bus clock frequency division 
  The set frequency division ratio is not cleared by a soft ware reset. The latest value is retained even after 
the software reset. 
   The value is initialized by a reset other than software resets. 
Before changing the initially set master clock to a faster source clock, be sure to set the frequency 
division ratio. 
   If a combined value of master clock, PLL multiplica tion, and frequency division ratio settings exceeds 
the maximum operating frequency of each internal bus, the operation corresponding to the setting is not 
guaranteed. 
 
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3.3.  PLL clock control 
This section explains the PLL clock control. 
The PLL Clock Control Circuit is used to generate the main clock. The PLL Oscillation Circuit can 
enable/disable operation (oscillation), select the input clock, set the stabilization wait time, and set the 
multiplication. 
 PLL operation 
The following explains operation of the PLL clock. 
  Configure the following settings using the PLL Clock Oscillation Stabilization Wait Time Setup Register 
(PSW_TMR). 
   Selecting the PLL input clock 
   Setting the PLL clock stabilization wait time 
   The PLL oscillation enable bit of the System Clock Mode Control Register (SCM_CTL) must be 
enabled to let the PLL Circuit start oscillating. 
   When the PLL clock stabilization wait time has elapsed, and the PLL oscillation stable bit of the 
System Clock Mode Status Register (SCM_STR) indicates  a stable state, the preparation for transition to 
PLL clock mode completes. 
   The Master clock switch control bit of the System Clock Mode Control Register (SCM_CTL) must be 
set to PLL clock mode to change to PLL clock mode. 
 Setting the PLL clock oscillati on stabilization wait time 
The details are given in 5.10 PLL Clock Stabilization Wait Time Setup Register (PSW_TMR) . 
 
  For bloc k 

diagram of the PLL Clock Control Circuit, see  2.Clock Generat i
 on Unit Configuration/Block 
Diagram . 
   For the order of frequency  division settings 

for each internal bus clock, see 4 Clock Setup Procedure 
Examples. 
   For th e oscillation
 

stabilization wait time, see  3.4 Oscillation stabilization wait time . 
   Only the main o s

cillation can be selected for the PLL input clock. 
 
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 Setting the multiplication ratio  to generate the PLL clock 
Each frequency division clock in the PLL Multiplicati on Circuit must be set using PLL Control Register 1 
(PLL_CTL1) and PLL Control Register 2 (PLL_CTL2). The following  Ta b l e  3 - 2 provides example 
frequency divisi on

 settings. 
Table 3-2 Example PLL multiplication ratio settings 
Input clock K PLLin N PLLout M CLKPLL 
4MHz  1 4MHz 20 80MHz  1 80MHz 
4MHz  1 4MHz 15 60MHz  1 60MHz 
4MHz  1 4MHz 15 120MHz  2 60MHz 
5MHz  1 5MHz 16 80MHz  1 80MHz 
5MHz  1 5MHz 12 60MHz  1 60MHz 
5MHz  1 5MHz 12 120MHz  2 60MHz 
6MHz  1 6MHz 10 60MHz  1 60MHz 
6MHz  1 6MHz 10 120MHz  2 60MHz 
8MHz   1 8MHz   10 80MHz  1 80MHz 
10MHz  1 10MHz 8  80MHz 1  80MHz 
10MHz  1 10MHz 6  60MHz 1  60MHz 
10MHz  1 10MHz 6 120MHz  2 60MHz 
12MHz  1 12MHz 5  60MHz 1  60MHz 
12MHz  1 12MHz 5 120MHz  2 60MHz 
15MHz  1 15MHz 4  60MHz 1  60MHz 
16MHz  1 16MHz 5  80MHz 1  80MHz 
20MHz  1 20MHz 4  80MHz 1  80MHz 
30MHz  1 30MHz 2 120MHz  2 60MHz 
40MHz  2 20MHz 4  80MHz 1  80MHz 
48MHz  3 16MHz 5  80MHz 1  80MHz 
48MHz  4 12MHz 5  60MHz 1  60MHz 
 
 
  For PLL c h

aracteristics, see Data Sheet. 
   Set the PLLin within t h

e value PLL input clock frequency: f
PLLI shown in the data sheet. 
   The value MxN is a multiplication ratio for the PLLin. Set this value within the range shown in the 
PLL multiple rate of the data sheet. 
   The frequency of the PLLin multiplied by MxN becomes PLLout. Set this value within the range 
shown in the PLL macro oscillation clock frequency: f
PLLO of the data sheet. 
   The value of the PLLout divided by M becomes CLKPLL. 
   See  Figure 2-1  for the configurations of PLL and divider. 
 
 
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3.4.  Oscillation stabilization wait time 
This section explains the oscillation stabilization wait time. 
An oscillation stabilization wait time is required if the source clock is not in a stable operating state. During 
the oscillation stabilization wait time, internal and external clocks stop the supply, only the internal time 
counter operates to wait until the stabilization wait time passes, a time value set in the Clock Stabilization 
Wait Time Register (CSW_TMR) or PLL Clock Oscillation Stabilization Wait Time Setup Register 
(PSW_TMR). When the wait time has been passed, the co rresponding oscillator is ready to operate, and the 
clock can be used as a master clock. 
  Setting the oscillation stabilization wait time 
  Main clock (CLKMO) 
Set the oscillation stabilization wait time of the main clock using the Clock Stabilization Wait Time 
Register (CSW_TMR). The set time value is counted by CLKHC. 
   Sub clock (CLKSO) 
Set the oscillation stabilization wait time of the sub clock using the Clock Stabilization Wait Time 
Register (CSW_TMR). The set time value is counted by CLKLC. 
   PLL clock 
Configure the following settings using the PLL Clock Oscillation Stabilization Wait Time Setup 
Register (PSW_TMR). The set time value is counted by CLKHC. 
   Selecting the PLL input clock 
   Setting the PLL clock stabilization wait time 
 Cause of waiting for oscillation stability 
  After the oscillation is enabled via software 
If the PLLE, SOSCE, and MOSCE bits  of the System Clock Mode Control Register (SCM_CTL) are set 
to active, each relevant oscillator waits  during the oscillation stabilization wait time. 
   When returning from stop mode using an external interrupt 
The status returns to clock mode, a state before stop mode, using an external clock. During stop mode, 
all source clocks stop and, therefore, the hardware automatically waits during the oscillation 
stabilization wait time. 
   After PLL operation is enabled 
After PLL operation is enabled, the PLL oscillation stabilization wait time is spent. 
 
    Each set v a

lue of the oscillation stabilization wait time must be changed before the clock is enabled. 
   After software reset, the oscillation  stab

ilization wait time is not applied. 
   In the stabilization wait time for main clock, sub clock and PLL clock, the built-in CR counts the clock 
as set in the Clock Stabilization Wait Time Registers. Stabilization wait time flag will be activated when 
the counting is complete, so these wait times are inde pendent of each oscillator statuses. The oscillation 
stabilization wait time may be completed before oscillator stabilization if the setting of the oscillation 
stabilization wait time is too short.   
   As the stabilization wait times for main clock and sub clock oscillators depend on the type of the 
oscillator (crystal, ceramics, etc.), proper oscilla tion stabilization wait time must be chosen for the 
oscillator to be used. 
   Set the PLL oscillation stabilization wait time by referring to PLL Clock LOCKUP Time of the electric 
characteristics described in Data Sheet. 
 
 
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3.5. Interrupt causes 
This section explains interrupt causes relevant to clocks. 
The clock generation unit has the following interrupt causes. 
 Interrupt causes 
The clock generation unit has the following four types of interrupt causes: 
  FCS interrupt (anomalous frequency detection interrupt) 
When the FCS (anomalous frequency detection) is enabled, and an anomalous frequency of the main 
clock is detected, an interrupt occurs. 
     PLL clock oscillation stabilization completion interrupt 
When the PLL clock oscillation stabilization wait time ends, an interrupt occurs. 
   Sub clock oscillation stabilization completion interrupt 
When the sub clock oscillation stabilization wait time ends, an interrupt occurs. 
   Main clock oscillation stabilization completion interrupt 
When the main clock oscillation stabilization wait time ends, an interrupt occurs. 
  Registers 
The following three types of registers are provided for each interrupt cause: 
  Interrupt Enable Register 
Enables/disables each interrupt. 
   Interrupt Status Register 
Indicates each interrupt status. This register is read-only. 
   Interrupt Clear Register 
Clears each interrupt cause. This register is write-only. 
 
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							4.  Clock Setup Procedure Examples 
This section explains procedure examples of setting up clocks. 
 Setup procedure examples 
Figure 4-1 Example clock setup procedure (Power-on -> High-speed CR run mode -> Desired 
clock mode) 
 
Access the Clock Stabilization Wait Time Register 
(CSW_TMR). Set the main oscillation stabilization 
wait time. 
Access the Interrupt Enable Register (INT_ENR).  Set the oscillation stabilization wait interrupt. 
Ye s   No 
High-speed CR/low-speed CR oscillation stabilization 
completed. High-speed CR runs as a master clock.
Use the main clock? 
Enable the main oscillation in the System Clock Mode Control Register (SCM_CTL.MOSCE=1).
with SCM_STR.RCM=SCM_CTL.RCS, changing  the mode to the selected clock mode. 
Access each bus prescaler register. 
BSC_PSR:Base Clock Prescaler APBC0_PSR : APB0 Prescaler 
APBC1_PSR : APB1 Prescaler 
APBC2_PSR : APB2 Prescaler 
TTC_PSR : Trace Clock Prescaler 
Set the bus clock frequency division. 
Start waiting for 
oscillation stabilit
y. 
Access the Clock Stabilization Wait Time Register  (CSW_TMR). Set the sub oscillation stabilization 
wait time. 
Access the Interrupt Enable Register (INT_ENR).  Set the oscillation stabilization wait interrupt. 
Ye s   No 
Enable the sub oscillation in the System Clock 
Mode Control Register (SCM_CTL.SOSCE=1).  Start waiting for 
oscillation stability. 
Access the PLL Clock Stabilization Wait Time 
Register (PSW_TMR). Set the PLL oscillation  stabilization wait time. 
Access the Interrupt Enable Register (INT_ENR).  Set the oscillation stabilization wait interrupt. 
Access the PLL control register1, 2(PLL_CTL1,
.PLL
_CTL2). Set the PLL multiplication ratio. 
No 
Enable the PLL oscillation in the System Clock 
Mode Control Register (SCM_CTL.PLLE=1). 
Start waiting for 
oscillation stability. 
Access the Interrupt Clear Register (INT_CLR).
Clear the oscillation stabilization wait interrupt cause.
Ye s  Use the PLL clock? 
Use the sub clock? 
* Only low-speed CR run  mode is selectable. 
Check main clock oscillation  stable bit of the System 
Clock Mode Status Register (SCM_STR.MORDY=1) 
Complete waiting for  oscillation stability. 
Check sub clock oscillation stable bit of the System 
Clock Mode Status Register (SCM_STR.SORDY=1)
Check PLL oscillation stable bit of the System Clock  Mode Status Register (SCM_STR.PLRDY=1) 
Complete waiting for oscillation stability. 
Complete waiting for 
oscillation stability. 
SSet the master clock switch control bit of the System Clock mode Control 
Register (SCM_CTL.RCS) to a desired clock mode. 
Waiting for high-speed CR/low-speed CR  oscillation stability
 
 
Power-on 
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