Motorola Cm Radio Vhf2 Hp Information Manual

							VHF Transmitter Power Amplifier (146-174 MHz) 2-3
Op-amp U103-3 monitors the drain current of U101 via resistor R122 and adjusts the bias voltage of 
U101.
In receive mode, the DC voltage from RX_EN line turns on Q101, which in turn switches off the 
biasing voltage to U101.
3.2 Power Controlled Driver Stage
The next stage is an LDMOS device (Q105) which provides a gain of 12dB. This device requires a 
positive gate bias and a quiescent current flow for proper operation. The bias is set during transmit 
mode by the V_cntrl_driver which is set to provide 100-150mA of quiescent current by the factory, 
and fed to the gate of Q105 via the resistive network.
The V_cntrl_driver is directly controlled by the ASFIC CMP. In receive mode, the ASFIC CMP 
(U504) sets V_cntrl_driver to 0V (DACR pin 5).
3.3 Final Stage
The final stage is an LDMOS device (Q100) providing a gain of 12dB. This device also requires a 
positive gate bias and a quiescent current flow for proper operation. The voltage of the line PA_BIAS 
is set in transmit mode by the ASFIC and fed to the gate of Q100 via the resistive network R134, 
R131. This bias voltage is tuned in the factory. If the transistor is replaced, the bias voltage must be 
tuned using the Tuner. Care must be taken not to damage the device by exceeding the maximum 
allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC supply voltage 
input, B+, via L117 and L115.
A matching network consisting of C1004-5, C1007-9, C1096, C1021, C1013, C1019, L116: and two 
striplines, transforms the impedance to 50 ohms and feeds the directional coupler.
3.4 Bi-Directional Coupler
The bi-directional Coupler is a microstrip printed circuit, which couples a small amount of the 
forward and reverse power of the RF power from Q100.The coupled signal is rectified to an output 
power which is proportional to the DC voltage rectified by diode D105; and the resulting DC voltage 
is routed to the power control section to ensure that the forward power out of the radio is held to a 
constant value.
3.5 Antenna Switch
The antenna switch utilizes the existing dc feed (B+) to the last stage device (Q100). The basic 
operation is to have both PIN diodes (D103, D104) turned on during key-up by forward biasing 
them. This is achieved by pulling down the voltage at the cathode end of D104 to around 12.4V 
(0.7V drop across each diode). The current through the diodes needs to be set around 100 mA to 
fully open the transmit path through resistor R108. Q106 is a current source controlled by Q103 
which is turned on in Tx mode by TX_EN. VR102 ensures that the voltage at resistor R107 never 
exceeds 5.6V. 
						

							2-4THEORY OF OPERATION
3.6 Harmonic Filter
Inductors L111, L112, L124 and L113 along with capacitors C11321, C1022, C1020, C1137, C1018 
and C1017 form a low-pass filter to attenuate harmonic energy coming from the transmitter. 
Resistor R150 drains any electrostatic charges that might otherwise build up on the antenna. The 
harmonic filter also prevents high level RF signals above the receiver passband from reaching the 
receiver circuits to improve spurious response rejection.
3.7 Power Control
The output power is regulated by using a forward power detection control loop. A directional coupler 
samples a portion of the forward and reflected RF power. The forward sampled RF is rectified by 
diode D105, and the resulting DC voltage is routed to the operational amplifier U100. The error 
output current is then routed to an integrator, and converted into the control voltage. This voltage 
controls the bias of the pre-driver (U101) stage. The output power level is set by way of a DAC, 
PWR_SET, in the audio processing IC (U504), which acts at the forward power control loop 
reference.
The sampled reflected power is rectified by diode D107. The resulting DC voltage is amplified by an 
operational amplifier U100 and routed to the summing junction. This detector protects the final stage 
Q100 from reflected power by increasing the error current. The temperature sensor protects the 
final stage Q100 from overheating by increasing the error current. A thermistor RT100 measures the 
final stage Q100 temperature. The voltage divider output is routed to an operational amplifier U103 
and then goes to the summing junction. The Zener Diode VR101 keeps the loop control voltage 
below 5.6V and eliminates the DC current from the 9.3 regulator U501. 
A local loop for the Pre Driver (U101) is used in order to stabilize the current for each stage.
In Rx mode, the two transistors Q101 and Q102 go to saturation and shut down the transmitter by 
applying ground to the Pre Driver U101.
4.0 VHF (146-174MHz) Frequency Synthesis
The synthesizer consists of a reference oscillator (Y201), low voltage Fractional-N (LVFRAC-N) 
synthesizer (U200), and a voltage controlled oscillator (VCO) (U201).
4.1 Reference Oscillator
The reference oscillator is a crystal (Y201) controlled Colpitts oscillator and has a frequency of 
16.8MHz. The oscillator transistor and start-up circuit are located in the LVFRAC-N (U200) while the 
oscillator feedback capacitors, crystal, and tuning varactors are external. An analog-to-digital (A/D) 
converter internal to the LVFRAC-N (U200) and controlled by the microprocessor via SPI sets the 
voltage at the warp output of U200 pin 25. This sets the frequency of the oscillator. Consequently, 
the output of the crystal Y201 is applied to U200 pin 23.
The method of temperature compensation is to apply an inverse Bechmann voltage curve, which 
matches the crystal’s Bechmann curve to a varactor that constantly shifts the oscillator back on 
frequency. The crystal vendor characterizes the crystal over a specified temperature range and 
codes this information into a bar code that is printed on the crystal package. In production, this 
crystal code is read via a 2-dimensional bar code reader and the parameters are saved. 
						

							VHF (146-174MHz) Frequency Synthesis2-5
This oscillator is temperature compensated to an accuracy of +/-2.5 PPM from -30 to 60 degrees C. 
The temperature compensation scheme is implemented by an algorithm that uses five crystal 
parameters (four characterize the inverse Bechmann voltage curve and one for frequency accuracy 
of the reference oscillator at 25 degrees C). This algorithm is implemented by the LVFRAC-N (U200) 
at the power up of the radio.
4.2 Fractional-N Synthesizer
The LVFRAC-N U200 consists of a pre-scaler, programmable loop divider, control divider logic, 
phase detector, charge pump, A/D converter for low frequency digital modulation, balanced 
attenuator used to balance the high and low frequency analog modulation, 13V positive voltage 
multiplier, serial interface for control, and a super filter for the regulated 5 volts.
Figure 2-3VHF Synthesizer Block Diagram
A voltage of 5V applied to the super filter input (U200, pin 30) supplies an output voltage of 4.5Vdc 
(VSF) at U200, pin 28. This supplies 4.5 V to the VCO Buffer IC U201.
To generate a high voltage to supply the phase detector (charge pump) output stage at pin VCP 
(U200, pin 47) while using a low voltage 3.3Vdc supply, a 13V positive voltage multiplier is used 
(D200, D201, and capacitors C2024, 2025, 2026, 2055, 2027, 2001).
Output lock (U200, pin 4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. A 16.8 MHz reference frequency is provided at U200, pin 
19.
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U403 PIN 100)
CLOCK (U403 PIN 1)
CSX (U403 PIN 2)
MOD IN (U501 PIN 40)
+5V (U503 PIN 1)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
        1540FILTERED 5VSTEERING LOCK (U403 PIN 56)
PRESCALER INFREF (U504 PIN 34)
39 BIAS2
41
 48 5, 20, 34, 36
+5V (U503 PIN 1)
AUX1 VDD, DC5VMODOUT
U200 
LOW VOLTAGEFRACTIONAL-N
SYNTHESIZER
AUX21 
BWSELECTVCO Bias
TRB
To IF
SectionTX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
LOOP
FILTER 
						

							2-6THEORY OF OPERATION
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U201), the TX and 
RX tank circuits, the external RX amplifier, and the modulation circuitry.
Figure 2-4VHF VCO Block Diagram
The VCOBIC together with the LVFRAC-N (U200) generate the required frequencies in both 
transmit and receive modes. The TRB line (U201, pin 19) determines which VCO and buffer is 
enabled (high being TX output at pin 10, low being RX output at pin 8). A sample of the signal from 
the enabled output is routed from U201, pin 12 (PRESC_OUT), via a low pass filter to U200, pin 32 
(PREIN). 
A steering line voltage between 3.0V and 10.0V at varactor D204 tunes the TX VCO through the 
frequency range of 146-174MHz, and at D203 tunes the RX VCO through the frequency range of 
190-219MHz.
The external RX amplifier is used to increase the output from U201, pin 9 from 3-4 dBm to the 
required 15dBm for proper mixer operation. In TX mode, the modulation signal from the LVFRAC-N 
(U200, pin 41) is applied to the VCO by way of the modulation circuit D205, R212, R211, C2073.
 
Presc
RX
TXQ200
Low Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U200 Pin28)
VCC Buffers
TX RF Injection U200 Pin 32 AUX3 (U200 Pin 2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U201
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6RX
TX
(U200 Pin 28)Rx-SW
Tx-SW
Vcc-Logic
(U200 Pin 28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Buffer 
						

							VHF (146-174MHz) Frequency Synthesis2-7
4.4 Synthesizer Operation
The synthesizer consists of a low voltage FRAC-N IC (LVFRAC-N), reference oscillator, charge 
pump circuits, loop filter circuit, and DC supply. The output signal (PRESC_OUT) of the VCOBIC 
(U201, pin 12) is fed to the PREIN, pin 32 of U200 via a low pass filter which attenuates harmonics 
and provides a correct input level to the LVFRAC-N in order to close the synthesizer loop.
The pre-scaler in the synthesizer (U200) is a dual modulus pre-scaler with selectable divider ratios. 
The divider ratio of the pre-scaler is controlled by the loop divider, which in turn receives its inputs 
via the SPI. The output of the pre-scaler is applied to the loop divider. The output of the loop divider 
is connected to the phase detector, which compares the loop divider’s output signal with the 
reference signal. The reference signal is generated by dividing down the signal of the reference 
oscillator (Y201).
The output signal of the phase detector is a pulsed dc signal that is routed to the charge pump. The 
charge pump outputs a current from U200, pin 43 (IOUT). The loop filter (consisting of R224, R217, 
R234, C2074, C2075, C2077, C2078, C2079, C2080, C2028, and L205) transforms this current into 
a voltage that is applied the varactor diodes D203 and D204 for RX and TX respectively. The output 
frequency is determined by this control voltage. The current can be set to a value fixed in the 
LVFRAC-N or to a value determined by the currents flowing into BIAS 1 (U200, pin 40) or BIAS 2 
(U200, pin 39). The currents are set by the value of R200 or R206 respectively. The selection of the 
three different bias sources is done by software programming. 
To modulate the synthesizer loop, a two-spot modulation method is utilized via the MODIN (U200, 
pin 10) input of the LVFRAC-N. The audio signal is applied to both the A/D converter (low frequency 
path) and the balance attenuator (high frequency path). The A/D converter converts the low 
frequency analog modulating signal into a digital code which is applied to the loop divider, thereby 
causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s deviation 
sensitivity to high frequency modulating signals. The output of the balance attenuator is presented 
at the MODOUT port of the LVFRAC-N (U200,pin 41) and connected to the VCO modulation 
varactor D205. 
						

							2-8THEORY OF OPERATION
5.0 Controller Theory of Operation
This section provides a detailed theory of operation for the radio and its components. The main 
radio is a single-board design, consisting of the transmitter, receiver, and controller circuits. A 
control head is connected by an extension cable. The control head contains LED indicators, a 
microphone connector, buttons, and speaker. 
In addition to the power cable and antenna cable, an accessory cable can be attached to a 
connector on the rear of the radio. The accessory cable enables you to connect accessories to the 
radio, such as an external speaker, emergency switch, foot-operated PTT, and ignition sensing, etc.
Figure 2-5Controller Block Diagram 
5.1 Radio Power Distribution
Voltage distribution is provided by five separate devices:

U514 P-cH FET - Batt + (Ext_SWB+)

U501 LM2941T - 9.3V

U503 LP2951CM - 5V

U508 MC 33269DTRK - 3.3V

U510 LP2986ILDX - 3.3V Digital
External
Microphone
Internal
Microphone
External
Speaker
Internal
Sp ea ke r
SCI to
Control Head Audio
 PA Audio/Signaling
   Architecture To Synthesizer
Mod
Out
16.8 MHz
Reference Clock
from Synthesizer
Disc Audio
To  R F  S e c t i o nSPI
    Digital
ArchitectureµP Clock
   3.3V
RegulatorRAM
EEPROM
FLASHHC11FL0 ASFIC_CMP
Accessory &  
Connector
Handset
. 
						

							Controller Theory of Operation2-9
The DC voltage applied to connector P2 supplies power directly to the following circuitry:

Electronic on/off control

RF power amplifier

12 volts P-cH FET -U514

9.3 volt regulator

Audio PA
Figure 2-6DC Power Distribution Block Diagram
Regulator U501 is used to generate the 9.3 volts required by some audio circuits, the RF circuitry 
and power control circuitry. Input and output capacitors are used to reduce high frequency noise. 
Resistors R5001 / R5081 set the output voltage of the regulator. This regulator output is 
electronically enabled by a 0 volt signal on pin 2. Q502, Q505 and R5038 are used to disable the 
regulator when the radio is turned off. 
Voltage regulator U510 provides 3.3 volts for the digital circuitry. Operating voltage is from the 
regulated 9.3V supply. Input and output capacitors are used to reduce high frequency noise and 
provide proper operation during battery transients. U510 provides a reset output that goes to 0 volts 
if the regulator output goes below 3.1 volts. This is used to reset the controller to prevent improper 
operation.
Voltage regulator U508 provides 3.3V for the RF circuits and ASFIC_CMP. Input and output 
capacitors are used to reduce the high frequency noise and provide proper operation during battery 
transients.
U501
9.3V Regulator FET
P-CH
On/Off
Control500mA
SW_Filt_B+Acces Conn
Audio PA_Soutdown
Power Loop Op_Amp Auto
On/Off
Switch
Control Ignition
B+
RF_PA
Audio_PA
Antenna Switch
Power Control Filt_B+
Ferrite BitControl Head
Mic Connector
Mic Bias
9V, 5mAKeypad
7_Seg
Bed
to
7-Seg
Shift
Reg3.2V
72mA 9.3V
65mAStatus LEDs
7_Seg
DOT
Back
light
On/Off
Control11-16.6V
0.9A
0.85A
U503
5V RF RegulatorU508
3.3V RF RegU510
3.3V D RegReset
Rx_Amp
PA_Pre-driver
PA  D r i v e r 500mA
LV F R A C _ N
IF_AmpASFIC_CMP
IFIC
RX Cctmicro P
RAM
Flash
EEPROM90mA
25mA 50mA 45mA 9.3V
45mA9.3V
75mA9.3V
162mA 
						

							2-10THEORY OF OPERATION
Voltage regulator U503 provides 5V for the RF circuits. Input and output capacitors are used to 
reduce the high frequency noise and provide proper operation during battery transients.
VSTBY is used only for CM360 5-tone radios.
The voltage VSTBY, which is derived directly from the supply voltage by components R5103 and 
VR502, is used to buffer the internal RAM. Capacitor C5120 allows the battery voltage to be 
disconnected for a couple of seconds without losing RAM parameters. Dual diode D501 prevents 
radio circuitry from discharging this capacitor. When the supply voltage is applied to the radio, 
C5120 is charged via R5103 and D501.
5.2 Protection Devices
Diode VR500 acts as protection against ESD, wrong polarity of the supply voltage, and load dump.
VR692 - VR699 are for ESD protection.
5.3 Automatic On/Off
The radio can be switched ON in any one of the following three ways:

On/Off switch. (No Ignition Mode)

Ignition and On/Off switch (Ignition Mode)

Emergency 
5.3.1 No Ignition Mode
When the radio is connected to the car battery for the first time, Q500 will be in saturation, Q503 will 
cut-off, Filt_B+ will pass through R5073, D500, and S5010-pin 6 (On/Off switch). When S5010 is 
ON, Filt_B+ will pass through S5010-pin5, D511, R5069, R5037 and base of Q505 and move Q505 
into saturation. This pulls U501-pin2 through R5038, D502 to 0.2V and turns On U514 and U501 
9.3V regulator which supplies voltage to all other regulators and consequently turns the radio on, 
When U504 (ASFIC_CMP) gets 3.3V, GCB2 goes to 3.3V and holds Q505 in saturation, for soft turn 
off. 
5.3.2 Ignition Mode
When ignition is connected for the first time, it will force high current through Q500 collector, This 
will move Q500 out of saturation and consequently Q503 will cut-off. S5010 pin 6 will get ignition 
voltage through R601 (for load dump), R610, (R610 & C678 are for ESD protection), VR501, 
R5074, and D500. When S5010 is ON, Filt_B+ passes through S5010-pin 5, D511, R5069, R5037 
and base of Q505 and inserts Q505 into saturation. This pulls U501-pin 2 through R5038, D502 to 
0.2V and turns on U514 and U501 9.3V regulator which supply voltage to all other regulators and 
turns the radio on, When U504 (ASFIC_CMP) get 3.3V supply, GCB2 goes to 3.3V and holds Q505 
in saturation state to allow soft turn off, 
When ignition is off Q500, Q503 will stay at the same state so S5010 pin 6 will get 0V from Ignition, 
Q504 goes from Sat to Cut, ONOFF_SENSE goes to 3.3V and it indicates to the radio to soft turn 
itself by changing GCB2 to ‘0’ after de registration if necessary. 
						

							Controller Theory of Operation2-11
5.3.3 Emergency Mode
The emergency switch (P1 pin 9), when engaged, grounds the base of Q506 via EMERGENCY 
_ACCES_CONN. This switches Q506 to off and consequently resistor R5020 pulls the collector of 
Q506 and the base of Q506 to levels above 2 volts. Transistor Q502 switches on and pulls U501 
pin2 to ground level, thus turning ON the radio. When the emergency switch is released R5030 pulls 
the base of Q506 up to 0.6 volts. This causes the collector of transistor Q506 to go low (0.2V), 
thereby switching Q502 to off.
While the radio is switched on, the µP monitors the voltage at the emergency input on the accessory 
connector via U403-pin 62. Three different conditions are distinguished: no emergency kit is 
connected, emergency kit connected (unpressed), and emergency press.
If no emergency switch is connected or the connection to the emergency switch is broken, the 
resistive divider R5030 / R5049 will set the voltage to about 3.14 volts (indicates no emergency kit 
found via EMERGENCY_SENSE line). If an emergency switch is connected, a resistor to ground 
within the emergency switch will reduce the voltage on EMERGENCY _SENSE line, and indicate to 
the µP that the emergency switch is operational. An engaged emergency switch pulls line 
EMERGENCY _SENSE line to ground level. Diode VR503 limits the voltage to protect the µP input. 
While EMERGENCY _ACCES_CONN is low, the µP starts execution, reads that the emergency 
input is active through the voltage level of µP pin 64, and sets the DC POWER ON output of the 
ASFIC CMP pin 13 to a logic high. This high will keep Q505 in saturation for soft turn off. 
5.4 Microprocessor Clock Synthesiser
The clock source for the µP system is generated by the ASFIC CMP (U504). Upon power-up the 
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the 
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference 
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a 
programmable synthesizer which can generate a synthesized signal ranging from 1200Hz to 
32.769MHz in 1200Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864MHz CMOS square 
wave UP CLK (on U504 pin 28) and this is routed to the µP (U403 pin 90). After the µP starts 
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually 
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various 
times depending on the software features that are executing. In addition, the clock frequency of the 
synthesizer is changed in small amounts if there is a possibility of harmonics of the clock source 
interfering with the desired radio receive frequency.
The ASFIC CMP synthesizer loop uses C5025, C5024 and R5033 to set the switching time and jitter 
of the clock output. If the synthesizer cannot generate the required clock frequency it will switch 
back to its default 3.6864MHz output.
Because the ASFIC CMP synthesizer and the µP system will not operate without the 16.8 MHz 
reference clock it (and the voltage regulators) should be checked first when debugging the system. 
						

							2-12THEORY OF OPERATION
5.5 Serial Peripheral Interface (SPI)
The µP communicates to many of the IC’s through its SPI port. This port consists of SPI TRANSMIT 
DATA (MOSI) (U403-pin100), SPI RECEIVE DATA (MISO) (U403-pin 99), SPI CLK (U0403-pin1) 
and chip select lines going to the various IC’s, connected on the SPI PORT (BUS). This BUS is a 
synchronous bus, in that the timing clock signal CLK is sent while SPI data (SPI TRANSMIT DATA 
or SPI RECEIVE DATA) is sent. Therefore, whenever there is activity on either SPI TRANSMIT 
DATA or SPI RECEIVE DATA there should be a uniform signal on CLK. The SPI TRANSMIT DATA 
is used to send serial from a µP to a device, and SPI RECEIVE DATA is used to send data from a 
device to a µP. 
In the controller section, there are two IC’s on the SPI BUS, ASFIC CMP (U504 pin 22), and 
EEPROM (U400). In the RF sections there is one IC on the SPI BUS, the FRAC-N Synthesizer. The 
chip select line CSX from U403 pin 2 is shared by the ASFIC CMP and FRAC-N Synthesizer. Each 
of these IC’s check the SPI data and when the sent address information matches the IC’s address, 
the following data is processed. 
When the µP needs to program any of these Is it brings the chip select line CSX to a logic “0” and 
then sends the proper data and clock signals. The amount of data sent to the various IC’s are 
different; e.g., the ASFIC CMP can receive up to 19 bytes (152 bits). After the data has been sent 
the chip select line is returned to logic “1”.
5.6 SBEP Serial Interface
The SBEP serial interface allows the radio to communicate with the Customer Programming 
Software (CPS), or the Universal Tuner via the Radio Interface Box (RIB) or the cable with internal 
RIB. This interface connects to the SCI pin via control head connector (J2-pin 17) and to the 
accessory connector P1-6 and comprises BUS+. The line is bi-directional, meaning that either the 
radio or the RIB can drive the line. The µP sends serial data and it reads serial data via pin 97. 
Whenever the µP detects activity on the BUS+ line, it starts communication. 
5.7 General Purpose Input/Output
The controller provides six general purpose lines (PROG I/O) available on the accessory connector 
P1 to interface to external options. Lines PROG IN 3 and 6 are inputs, PROG OUT 4 is an output 
and PROG IN OUT 8, 12 and 14 are bi-directional. The software and the hardware configuration of 
the radio model define the function of each port.

PROG IN 3 can be used as external PTT input, or others, set by the CPS. The µP reads this 
port via pin 72 and Q412.

PROG OUT 4 can be used as external alarm output, set by the CPS. Transistor Q401 is 
controlled by the µP (U403 pin 55)

PROG IN 6 can be used as normal input, set by the CPS. The µP reads this port via pin 73 
and Q411. This pin is also used to communicate with the RIB if resistor R421 is placed.

DIG IN OUT 8,12,14 are bi-directional and use the same circuit configuration. Each port uses 
an output Q416, Q404, Q405 controlled by µP pins 52, 53, 54. The input ports are read 
through µP pins 74, 76, 77; using Q409, Q410, Q411