Motorola Cp185 Basic 68007024004 Manual
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VHF Specifications1-5 1.5 VHF Specifications General Self-Quieter FrequenciesTransmitter Receiver All specifications are subject to change without notice. VHF Frequency:136 – 174 MHz Channel Capacity: 16 Channels Power Supply:7.5 Volts ±20% Dimensions: (H x W x D) with High Capacity Li-Ion NiMH Std Li-Ion Std Batteries:120 mm x 55 mm x 40.7 mm 120 mm x 55 mm x 36.5 mm 120 mm x 55 mm x 35.5 mm Weight: model with Battery: High Capacity Li-Ion NiMH Std Li-Ion Std 342.0g 394.5g 335.0g Average Battery Life @ (5-5-90 Duty Cycle): High Capacity Li-Ion NiMH Std Li-Ion StdCapacity (mAh) 2150 1300 15005 W 12 Hrs. 8 Hrs. 8 Hrs.2 W 14 Hrs. 10 Hrs. 10 Hrs. VHF 140 155.01 155.02 155.03 155.015 155.17 155.18 155.175 155.505 159.995 160 160.005 161.45 167.025 167.03 169.995 170 170.005 173.985 173.99 VHF RF Output NiMH @ 7.5 V:Low 2 WHigh 5 W Frequency: 136 – 174 MHz Channel Spacing:12.5/25 kHz Freq. Stability: (-30°C to +60°C)0.00025% Spurs/Harmonics:-36 dBm < 1 GHz -30 dBm > 1 GHz Audio Response: (from 6 dB/oct. Pre-emphasis, 300 to 3000 Hz)+1, -3 dB Audio Distortion: @ 1000 Hz, 60% Rated Max. Dev.-40 dB VHF 12.5 kHzVHF 25 kHz Frequency:136 – 174 MHz Sensitivity 12 dB EIA SINAD:0.25 μV (typical) Adjacent Channel Selectivity:-65 dB-70 dB Intermodulation: -70 dB Freq. Stability (-30°C to +60°C):0.00025% Spur Rejection: -70 dB Image and 1/2 I-F Rejection:-70 dB Audio Output @
1-6Model Charts and Test Specifications: VHF Specifications Notes
Chapter 2 Theory Of Operation 2.1 Introduction This chapter provides a basic theory of operation for the radio components. 2.2 Major Assemblies • Main PCB – contains the RF circuits which comprises receiver, transmitter, phase-locked loop (PLL) frequency synthesizer, micro controller, power supply, audio and digital circuits • Display and Keypad PCB (Limited and Full Keypad models only) – 8 characters (14 segments star burst) and 10 icons with backlighting, liquid-crystal display (LCD) • Volume Knob PCB (PMDN4128AR) – Rotary Volume Knob and 16-channel Knob 2.2.1 Receiver The radios receiver is a double conversion super heterodyne with 1st IF of 45.1 MHz and 2nd IF of 455 kHz. UHF2 receiver design covers the frequency range of 435 – 480 MHz. VHF receiver design covers the frequency range of 136 – 174 MHz. Figure 2-1. Receiver Block Diagram Harmonic filter (LPF)ANT-SW VCO PRESELECTOR FILTER Q301 LNAPOST SELECTOR FILTER1’ST MIXERMCF (X-tal filter)45.1MHz IF AMP Q303 CR401, CR301 F.T.V. Cer filter CF1(FW) IF, MIX U201 N/S SW X-TAL 44.645MHz DESCRIMINATOR 450C24 Recovered AUDIO Inj FILTER Cer filter CF2(HW)
2-2Theory Of Operation: Major Assemblies 2.2.1.1 RX Front End UHF2 : Receiver Front-end consists of a low pass filter, a pre-selector filter, a low noise RF Amplifier and a Post-selector filter. Incoming RF signal from the antenna is applied through the Harmonics Low Pass Filter (L409 – L411, C426 – C429, C445 – C446) and passes through the transmit/receive switch (CR301) and a varactor-tuned 2-pole pre-selector filter (L320, L324, C351, C361, CR314 and CR307) before routed to an RF amplifier (Q301). The pre-selector filter is an 8 step Band-shift filter, and the frequency shifting is controlled by variable capacitor diodes (CR314 and CR307) connected to the CPU. The filter output is coupled to a 13 dB RF amplifier Q301 which outputs the RF signal to the post-selector filter (L323, L322, L328, C379, C354 and C355) which is also a band shift filter configured to provide steeper low-side attenuation. The 3 variable capacitors (CR313, CR304 and CR305) with 8 frequency steps are also controlled by the CPU. VHF : Receiver Front-end consists of a low pass filter, a pre-selector filter, a low noise RF Amplifier, a Post-selector filter. Incoming RF signal from antenna is applied through the Harmonics Low Pass Filter (L409 – L411, C426 – C430, C445 – C446) and passes the transmit/receive switch (CR301) and a varactor-tuned 2-pole pre-selector filter (L301 – L304, C301, CR302, CR303, C304, C305, C307, C308) before routed to an RF amplifier (Q301). The pre-selector filter is a 6 step Band-shift filter, and the frequency shifting is controlled by variable capacitors diode’s (CR302 & CR303) connected to the CPU. The filter output is coupled to a 13 dB RF amplifier Q301 which outputs the RF signal to the post-selector filter (L308, L309, L311, C315 and C354) which is also a band shift filter configured to provide steeper low-side attenuation. The 2 units of 6 step frequency variable capacitors (CR305, CR307) are also controlled by the CPU. 2.2.1.2 RX Back End UHF2 : RF signal from RX front-end is then directed to a Single Balanced Mixer (L329, L333, Q306, and Q307). 1st LO signal from VCO is filtered by an injection filter (L310, L331, C325 – C327) to remove harmonics. After passing through a pair of 45.1 MHz Crystal filter, the 1st IF signal is amplified by 15 dB via an IF amp (Q303) and channeled to IF IC (U201) to be mixed thus producing the 2nd IF Frequency (455 kHz): 1st IF (45.1 MHz) - 2nd LO (44.645 MHz) = 2nd IF (455 kHz) Depending on channel spacing, the 2nd IF frequency passes through the wide (CF1) and/or narrow (CF2) filters to eliminate undesired signals before being finally demodulated by demodulator in U201 with Recovered Audio as the final output. VHF : RF signal from RX front-end is then directed to a Single Balanced Mixer (L329, L333, Q306, and Q307). 1st LO signal from VCO is filtered by an injection filter (L310, L331, C325, C326 and C333) to remove harmonics. After passing through a pair of 45.1 MHz Crystal filter, The 1st IF signal is amplified by 15 dB via an IF amp (Q303) and channeled to IF IC (U201) to be mixed thus producing 2nd IF Frequency (455 kHz) 1st IF (45.1 MHz) - 2nd LO (44.645 MHz) = 2nd IF (455 kHz) Depending on channel spacing, the 2nd IF frequency passes through wide (CF1) or narrow (CF2) filter to eliminate undesired signals before being finally demodulated by demodulator in U201 with Recovered Audio as the final output.
Theory Of Operation: Major Assemblies2-3 2.2.1.3 RX Squelch The mute (squelch) circuitry switches off the audio amplifier when no audio is detected from the recovered audio. The squelch circuit main components are U202 & U201. U202 will adjust the squelch circuit sensitivity depending on Noise level from recovered audio. Noise level is amplified by internal amplifier of U201 to help U202 decide the squelch circuit sensitivity. If the noise level is over the set threshold, the microprocessor mutes the radio. 2.2.2 Transmitter The radios TX Power Amplifier system is a three stage amplifier which is able to amplify the VCO output up to the permitted maximum transmit power levels (UHF2: 4W, VHF: 5W). TX VCO output signal passes thru a 3 dB, pie style resistor, attenuator before going into the TX power stage acting as isolation between the low power VCO and high power amps. The next stage consists of a pre-driver (Q401) and a driver amplifier (Q402). The TX RF signal (UHF2 : -4 dBm, VHF : -3 dBm) from the attenuator is amplified to +25 dBm (UHF2) or +28 dBm (VHF) by the pre-driver and driver amp. This is followed by the final PA, an enhancement-mode N-channel MOSFET device (Q403), which provides a 12 dB gain. The fnal PA draws current directly from the DC battery supply voltage input via L413. The PA matching network consists of C416 – C422 (UHF2) or C417, C418, C420, C455 (VHF) and a strip line, which matches the TX Power impedance to approximately 50 ohm. Antenna switch is shared between TX and RX circuit. In TX mode, PIN diodes (CR401, CR301) are forward biased which enable the High Power RF signal to pass through the antenna. In RX mode, both diodes are off. Signals applied to the antenna jack are routed, via the Harmonics LPF in to the RX circuit. The High Power RF Signal finally passes through a TX Low Pass Filter, a 7th order Chebyshev filter (L409 – L411, C426 – C429, C445 – C446). Note Perform squelch tuning after any RX part replacement. Refer Chapter 5.6: Receiver Tuning on page 5-8. Figure 2-2. Transmitter Block Diagram CR401Strip LineQ403 R417Q402 Q401 LPF ANT-SWFINAL AMP CURRENT DETECTDRIVER AMP APCP.DRIVER AMP BATT. U401 3dB Atten.From VCO
2-4Theory Of Operation: Major Assemblies The APC (Auto Power Control) keeps the current supplied to Final PA (Q403) constant. Resistor, R417 is used for current sensing. The voltage difference ratio of R423 to R417 is amplified through U401 and passed to Q404 and Q405 to produce constant power output to the antenna. Do not exceed the maximum allowed bias voltage of the device. 2.2.3 Phase Lock Loop Synthesizer The Phase Lock Loop (PLL) synthesizer subsystem consists of the reference oscillator (VCTCXO), VCO, PLL IC, Charge pump and Loop filter. VCTCXO (Voltage Controlled Temperature Compensated crystal Oscillator) reference frequency (12.8 MHz) provides reference to PLL IC, with stability of +/-2.5PPM at -30° to +60°C. This reference frequency is divided to 6.25 kHz or 5 kHz by PLL IC. PLL IC outputs 2 Signals (P & R) depending on phase difference. A charge pump is used to charge these output signals from 0 – 3.3 V up to 0 – 10 V which is required to control the VCO. A voltage doubler (U507) converts 5 V to 10 V to supply the necessary voltage for a higher frequency resolution in VCO. The Loop filter is a Low Pass filter (C751 – C754, R726 – R728) to reduce the residual side-band noise of VCO Reference Frequency for the best signal-to-noise ratio. The VCO module contains both RX VCO and TX VCO, configured as Collpits oscillators and connects to DC power through cascaded buffers. Q705 and Q305 enable RX VCO when RX-EN is high. Q706 and Q503 enable TX VCO when TX-EN1 is high. The input audio signal for TX VCO is from (U501-B) and applied to a variable capacitor diode (CR703) in TX VCO to be modulated into TX RF signal. Note: Retune the TX Power if Final PA (Q403) is replaced. Refer Chapter 5.5: Transmitter Alignment Options on page 5-3. Figure 2-3. PLL Synthesizer Block Diagram U701 FL701U505 VCO PLL IC PLL DATA VCTCXOREG. 5V Loop filter AUDIO [From filter (U501)] Charge Pump U506 REG. 3.3V U50710VVoltage Doubler 3.3V5V To Transmit
Theory Of Operation: Major Assemblies2-5 2.2.4 RX Audio Circuit The RX audio circuit consists of Audio Processor IC, Audio amp, speakers & Sub-tone system. The RX Audio from U201 is channeled to Audio processor IC. VR3 controls the received demodulated signal level from -4.0 dB to +3.5 dB in 0.5 dB steps. RX LPF eliminates high-frequency audio components > 3 kHz. TX/RX HPF eliminates low-frequency audio components lower < 250Hz. Descrambler (if ON) inverts the spectrum distribution of audio signals with respect to scrambling frequency. De-emphasis (if ON) restores high-frequency component of audio signal which has been emphasized by the pre-emphasis circuit in transmitting radio. Expander (if ON) expands audio signal by 0.5 dB to restore the original signal compressed by transmitting radio. VR4 amplifies RX audio level by -18.0 dB, with -4.5 dB to +4.5 dB in 0.25 dB steps adjustment range. Smoothing filter (SMF) eliminates high-frequency and clock components, generated by ASIC. Sub-audio Programmable LPF totally eliminates voice audio from Audio signal to extract sub-audio tone. VR5 regulates the output level of extracted sub-audio tone and sends it to a high pass filter (U105-A,B) with 4 selectable cut-off frequencies and finally passes through a comparator (U105-C), to square the signal and sends it to the MCU. The output audio signal of Audio Processor IC is directed to volume control switch (SW/VOL1) which is controlled by user and is finally amplified by U601BTL Audio Amplifier to a sufficient level to drive either the external or internal speaker.Figure 2-4. RX Audio Block Diagram VR3Scrambler / DescramblerDe- emphasisExpanderVR4SMF SVRIN- IN+ OUT- OUT+ Audio Mute control RX LPF TX/RX HPF RXA1 -4 to +3.5dB / 0.5dB-18, -4.5 to + 4.5dB / 0.25dB Audio Processor IC (AK2347) Audio IN (from IF IC) VR5 Sub audio Programmable LPF To CPU (tone detect) pin 24 pin 18pin 21 Audio Amp. U102 U601Vol1 -6 to +6dB / 0.5dB INT SPK. EXT SPK.J601 Sub audio HPFU105-A,B Compar ator U105-C
2-6Theory Of Operation: Major Assemblies 2.2.5 TX Audio Circuit The TX audio circuit is comprised of microphones, LPF, Audio Processor IC, and TX Sub-tone system. The TX audio enters the radio via the internal MIC or external MIC. This TX Audio is filtered through a 4th order 4 kHz Low-pass filter (U501-C & D) which prevents aliasing noise from ASIC. TX Audio enters the Audio Processor IC which is then directed to an internal Amplifier (TX A1) for gain adjustment of audio signal. A HPF (VR1) controls the input level of TX audio signal from -6.0 dB to +4.5 dB in 1.5 dB steps. A Compressor (if ON) compresses the amplitude of TX audio signal by 0.5 dB. A Pre-emphasis circuit (if ON) emphasizes the high frequency component of TX audio signal to improve Signal to Noise ratio before modulation. A shared High-pass filter (TX/RX HPF) eliminates low-frequency components 3 kHz. A Smoothing filter (SMF) eliminates high-frequency and clock components generated internally by ASIC. For sub-tone data from CPU, DTA1 amplifies the signal, sends it through a Sub-audio Programmable LPF to eliminate components of DAT1 amplification, and finally the signal is regulated by VR5 from -6.0 dB to +6.0 dB in 0.5 dB steps. The final sub-tone data passes through a 2nd order LPF (U502-A) before it is mixed with TX Audio for modulation. The processed TX audio signal from Audio Processor IC is amplified by TX audio frequency amplifier (U502-C) to increase limiting range and then adjusted to a proper level for modulation by U508. Final TX Audio signal passes through a 6th order 3 kHz low pass filter (U501-A & B) before sent to VCO for modulation.Figure 2-5. TX Audio Block Diagram Note: Retune the TX modulation if U508 is replaced. Refer Chapter 5.5: Transmitter Alignment Options on page 5-3. VR1 (HPF)LimiterSplatterSMF TX/RX HPFTXA1 -6 to +4.5dB / 1.5dB-9.6 to + 3dB / 0. 2 d B Audio Processor IC (AK2347 ) Tone IN (from CPU)VR5 Sub audio Programmable LPF pin4 pin 17pin 8 U1 0 2 -6 to +6dB / 0.5dBFc = 300HzVR2Pr e- EmphasisCom- pr essor DTA1 pin 19 To VCO & VCT CXO 2 Order LPF (Fc=300Hz) U502-A Mod. Adj, 6 Order LPF (F c=3KH z ) U501-A ,B U5 0 8 T X AF Amp. U502-C 4 Order LPF (F c=4KH z ) U5 0 1 - C , DMic (Audio IN) Fc=2.55KHz/ 3KHz
Theory Of Operation: Major Assemblies2-7 The output audio signal of Audio Processor IC is directed to volume control switch (SW/VOL1) controlled by user and is finally amplified by U601BTL Audio Amplifier to a sufficient level to drive either the external or internal speaker. 2.2.6 Microcontroller The microprocessor or CPU includes Microprocessor (U101), EEPROM and support components. Radio operation is controlled by software in internal Flash ROM memory. Radio parameters and customer specific information is stored in External EEPROM (U104). Pins 35 & 36 controls the Sub-PCB mounted LED indicators. PTT button (PB501) is linked to CPU via pin 44. Side programmable buttons 1 & 2 (PB502 & PB503) is linked via pin 21 & 32, respectively. Customer Programming Software (CPS) connects to the radio via a USB Programming cable (PMDN4077_R) through the microphone port (J601 pin 6) to pin 34 & 33 (PRG/CLONE_RX & PRG/CLONE_TX port). A 7.3728 MHz clock signal (X-in) is provided by FL101 to CPU. A voltage divider system (R153 & R154) is used by CPU to sense battery level. 2.2.7 Power Supply There are 4 voltage supplies in this radio: SWB+, 3.3 V, 5 V & 10 V. SWB+ voltage is distributed to SW/Vol 1, Final PA (Q403 via R417) & APC circuit (U401) The 3.3 V regulated supply (U506) is applied to CPU (U101), EEPROM (U104), DTMF IC (U103), Audio processor IC (U102), microphone biasing circuit and LCD/keypad driver. The 5.0 V regulated source (U505) is distributed to RX back end circuit, RX/TX audio filters, 1/2 VCC generator, VCO (Q705, Q706), RX B+ (Q304), TXvB (Q407) & VCTCXO. The 10.0 V regulated source (U507) is solely applied for Charge pump use.