Motorola Gp328plus Gp338plus Gp338xls Detailed 6804112j28 G Manual

							Transmitter5A-5
4.1.2 Antenna Switch
The antenna switch circuit consists of two PIN diodes (D3521 and D3551), a pi network (C3531, 
L3551 and C3550), and two current limiting resistors (R3571, R3572, R3573 ).  In the transmit mode,  
B+ at PCIC (U3502) pin 23 will go low and turn on Q3561 where a B+ bias is applied to the antenna 
switch circuit to bias the diodes on.  The shunt diode (D3551) shorts out the receiver port, and the pi 
network, which operates as a quarter wave transmission line, transforms the low impedance of the 
shunt diode to a high impedance at the input of the harmonic filter.  In the receive mode, the diodes 
are both off, and hence, there exists a low attenuation path between the antenna and receiver ports.
4.1.3 Harmonic Filter
The harmonic filter consists of C3532 to C3536, L3531 and L3532.  This network forms a low-pass 
filter to attenuate harmonic energy of the transmitter to specifications level. The harmonic filter 
insertion loss should be less than 1.2dB.
4.1.4 Antenna Matching Network
A matching network which is made up of L3538 and C3537 is used to match the antennas 
impedance to the harmonic filter.  This will optimize the performance of the transmitter and receiver 
into an antenna.
4.1.5 Power Control Integrated Circuit (PCIC)
The transmitter uses the Power Control IC (PCIC), U3502  to control the power output of the radio by 
maintaining the radio current drain.  The current to the final stage of the power module is supplied 
through R3519 (0.1ohms),  which provides a voltage proportional to the current drain.   This voltage is 
then  fedback to the Automatic Level Control (ALC) within the PCIC  to keep the whole loop stable.  
The PCIC has internal digital to analog converters (DACs) which provide the reference voltage of the 
control loop.  The voltage level is controlled by the microprocessor through the data line of the PCIC.
There are resistors and integrators within the PCIC, and external capacitors (C3562, C3563 and 
C3565)  in controlling the transmitter rising and falling time.  These are necessary in reducing the 
power splatter into adjacent channels.
U3503 and its associated circuitry acts as a temperature cut back circuitry.  This circuitry provides the 
necessary voltage to the PCIC to cut the transmitter power when the radio temperature gets too high. 
						

							5A-6Receiver
5.0 Receiver
5.1 Receiver Front-End
(Refer to VHF Receiver Front End Schematic Diagram on page 5A-22, VHF Receiver Back End 
Schematic Diagram on page 5A-23, and VHF Transmitter Schematic Diagram on page 5A-26)
The RF signal is received by the antenna and applied to a low-pass filter. For VHF, the filter consists 
of L3531, L3532, C3532 to C3563. The filtered RF signal is passed through the antenna switch. The 
antenna switch circuit consists of two PIN diodes(D3521 and D3551) and a pi network (C3531, L3551 
and C3550).The signal is then applied to a varactor tuned bandpass filter. The VHF bandpass filter  
comprises of L3301, L3303, C3301 to C3304 and D3301. The bandpass filter is tuned by applying a 
control voltage to the varactor diode (D3301) in the filter.
The bandpass filter is electronically tuned by the DACRx from IC404 which is controlled by the 
microprocessor. Depending on the carrier frequency, the DACRx will supply the tuned voltage to the 
varactor diodes in the filter. Wideband operation of the filter is achieved by shifting the bandpass filter 
across the band.
The output of the bandpass filter is coupled to the RF amplifier transistor Q3302 via C3306. After 
being amplified by the RF amplifier, the RF signal is further filtered by a second varactor tuned 
bandpass filter, consisting of  L3305, L3306, C3311 to C3314 and  D3302. 
Both the pre and post-RF amplifier varactor tuned filters have similar responses. The 3 dB bandwidth 
of the filter is about 12 MHz. This enables the filters to be electronically controlled by using a single 
control voltage which is DACRx .
Figure 5-2: VHF Receiver Block Diagram
Demodulator
Synthesizer
Crystal 
Filter Mixer Varactor 
Tuned Filter RF Amp Va r a c t o r  
Tuned Filter Pin Diode 
Antenna 
Switch
RF Jack Antenna
AGC
Control Voltage
from  ASFICFirst LO
from FGU
Recovered Audio
Squelch
RSSI
IFIC
SPI Bus 16.8 MHz
Reference Clock
Second
LO VCOIF Amp
U3220 
						

							Receiver5A-7
The output of the post-RF amplifier filter is connected to the passive double balanced mixer which 
consists of T3301, T3302 and CR3301. Matching of the filter to the mixer is provided by C3317, 
C3318 and L3308. After mixing with the first LO signal from the voltage controlled oscillator (VCO) 
using high side injection, the RF signal is down-converted to the 45.1 MHz IF signal. 
The IF signal coming out of the mixer is transfered to the crystal filter (Y3200) through a resistor pad 
(R3321 - R3323) and a diplexer (C3320 and L3309). Matching to the input of the crystal filter is 
provided by C3200 and L3200. The crystal filter provides the necessary selectivity and 
intermodulation protection. 
5.2 Receiver Back-End
(Refer to VHF Receiver Back End Schematic Diagram on page 5A-23)
The output of crystal filter Y3200 is matched to the input of IF amplifier transistor Q3200 by capacitor 
C3203. Voltage supply to the IF amplifier is taken from the receive 5 volts (R5). The gain controlled IF 
amplifer provides a maximum gain of about 10dB.  The amplified IF signal is then coupled into 
U3220(pin 3) via L3202, C3207, and C3230 which provides the matching for the IF amplifier and 
U3220.
The IF signal applied to pin 3 of U3220 is amplified, down-converted, filtered, and demodulated, to 
produce the recovered audio at pin 27 of U3220. This IF IC is electronically programmable, and the 
amount of filtering (which is dependent on the radio channel spacing) is controlled by the 
microprocessor. Additional filtering, once externally provided by the conventional ceramic filters, is 
replaced by internal filters in the IF module (U3220). 
The IF IC uses a type of direct conversion process, whereby the externally generated second LO 
frequency is divided by two in U3220 so that it is very close to the first IF frequency. The IF IC (U3220) 
synthesizes the second LO  and phase-locks the VCO to track the first IF frequency. The second LO 
is designed to oscillate at twice the first IF frequency because of the divide-by-two function in the IF 
IC.
In the absence of an IF signal, the VCO will “search” for a frequency, or its frequency will vary close to 
twice the IF frequency. When an IF signal is received, the VCO will lock onto the IF signal. The 
second LO/VCO is a Colpitts oscillator built around transistor Q3270. The VCO has a varactor diode, 
D3270, to adjust the VCO frequency. The control signal for the varactor is derived from a loop filter 
consisting of C3278 to C3280, R3274 and R3275.
The IF IC (U3220) also performs several other functions. It provides a received signal-strength 
indicator (RSSI) and a squelch output. The RSSI is a dc voltage monitored by the microprocessor, 
and used as a peak indicator during the bench tuning of the receiver front-end varactor filter. The 
RSSI voltage is also used to control the automatic gain control (AGC) circuit at the front-end. 
The demodulated signal on pin 27 of U3220 is also used for squelch control. The signal is routed to 
U404 (ASFIC) where squelch signal shaping and detection takes place. The demodulated audio 
signal is also routed to U404 for processing before going to the audio amplifier for amplification.  
						

							5A-8Receiver
5.3 Automatic Gain Control Circuit
(Refer to VHF Receiver Front End Schematic Diagram on page 5A-22 and VHF Receiver Back End 
Schematic Diagram on page 5A-23)
The front end automatic gain control circuit  provides automatic reduction of gain, of the front end RF 
amplifier via feedback. This action is necessary to prevent overloading of back end circuits. This is 
achieved by drawing some of the output power from the RF amplifier output. At high radio 
frequencies, capacitor C3327 provides the low impedance path to ground for this purpose. CR3302 is 
a PIN diode used for switching the path on or off. A certain amount of forward biasing current is 
needed to turn the PIN diode on. Transistor Q3301 provides this current.
Radio signal strength indicator, RSSI,  a voltage signal, is used to drive Q3301 to saturation i.e. 
turned on. RSSI is produced by U3220 and is proportional to the gain of the RF amplifier and the input 
power to the radio. 
Resistors R3304 and R3305 are voltage dividers designed to turn on Q3301 at certain RSSI levels. In 
order to turn on Q3301 the voltage across R3305 must be greater or equal to the voltage across 
R3324, plus the base-emitter voltage (Vbe) present at Q3301. Capacitor C3209 is used to dampen 
any instability while the AGC is turning on. The current flowing into the collector of Q3301, a high 
current gain NPN transistor, will be drawn through the PIN diode to turn it on. Maximum current 
flowing through the PIN is limited by the resistors R3316, R3313, R3306 and R3324. C3326 is a 
feedback capacitor used to provide some stability  to this high gain stage.
An additional gain control circuit is formed by Q3201 and its associated circuitry. Resistors R3206 and 
R3207 are voltage dividers designed to turn on Q3201 at a significantly higher RSSI level than the 
level required to turn on PIN diode control transistor Q3301. In order to turn on Q3201 the voltage 
across R3207 must be greater or equal to the voltage across R3208, plus the base-emitter voltage 
(Vbe) present at Q3201. As current starts flowing into the collector of Q3201, it reduces the bias 
voltage at the base of IF amplifier transistor Q3200 and in turn, the gain of the IF amplifier. The gain 
can be controlled in a range of -30dB up to +10dB. 
						

							Frequency Generation Circuitry5A-9
6.0 Frequency Generation Circuitry
The Frequency Generation Circuitry is composed of two main ICs, the Fractional-N synthesizer 
(U3701), and the VCO/Buffer IC (U3801). Designed in conjunction to maximize  compatibility, the two 
ICs provide many of the functions that normally would require additional circuitry. The synthesizer  
block diagram illustrates the interconnect and support circuitry used in the region. Refer to the 
relevant schematics for the reference designators.
The synthesizer is powered by regulated 5V and 3.3V which come from U3711 and U3201 
respectively. The synthesizer in turn generates a superfiltered 4.5V which powers U3801.
In addition to the VCO, the synthesizer must interface with the logic and ASFIC circuitry. 
Programming for the synthesizer is accomplished through the data , clock and chip select lines from 
the microprocessor. A 3.3V dc signal from synthesizer lock detect line indicates to the microprocessor 
that the synthesizer is locked.
Transmit modulation from the ASFIC is supplied to pin10 of U3701. Internally the audio is digitized by 
the Fractional-N and applied to the loop divider to provide the low-port modulation. The audio runs 
through an internal attenuator for modulation balancing purposes before going out to the VCO.
Figure 5-3: Frequency Generation Unit Block Diagram
Vo l t a g e  
Multiplier
Synthesizer 
U3701
Loop 
Filter
VCOBIC 
U3801
To
Mixer
To
PA  D r i v e rVCP
Vmult1Aux3
MOD Out
Modulating
Signal Vmult2Rx VCO Circuit
Tx VCOTRB
16.8 MHz
Ref. Osc.Rx Out
Tx Out
Circuit 
						

							5A-10Frequency Generation Circuitry
6.1 Synthesizer
(Refer toVHF Synthesizer Schematic Diagram on page 5A-24)
The Fractional-N Synthesizer uses a 16.8MHz crystal (Y3761) to provide a reference  for the system. 
The LVFractN IC (U3701) further divides this to 2.1MHz, 2.225MHz, and 2.4MHz as reference 
frequencies. Together with C3761, C3762, C3763, R3761 and D3761 , they build up the  reference 
oscillator which is capable of 2.5ppm stability over temperatures of -30 to 85°C. It also provides 
16.8MHz at pin 19 of U3701 to be used by ASFIC and LVZIF. 
The loop filter which consist of  C3721, C3722, R3721, R3722 and R3723 provides the necessary dc 
steering voltage for the VCO and determines the amount of noise and  spur passing through .
In achieving fast locking for the synthesizer, an internal adapt charge pump provides higher current at 
pin 45 of U3701 to put synthesizer within the lock range. The required frequency is then locked by 
normal mode charge pump at pin 43 .
Both the normal and adapt charge pumps get their supply from the capacitive voltage multiplier which 
is made up of C3701 to C3704 and triple diodes D3701, D3702. Two 3.3V square waves ( 180 deg 
out of phase) are first multiplied by four and then shifted, along with regulated 5V,  to build up 13.5V at 
pin 47 of U3701.
Figure 5-4: Synthesizer Block Diagram
DATA
CLK
CEX
MODIN
VCC, DC5V
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
  VOLTAGE
CONTROLLED
 OSCILLATOR
2-POLE
LOOP
FILTER
DATA (U409 PIN 100)
CLOCK (U409 PIN 1)
CSX (U409 PIN 2)
MOD IN (U404 PIN 40)
+5V (U3711 PIN 4)7
8
9
10
13, 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3
AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 23, 24
43
45
3
2
28
14
1540FILTERED 5VSTEERING
LINE LOCK (U409 PIN 56)
PRESCALER INLO RF INJECTION
TX RF INJECTION
(1ST STAGE OF PA) FREF (U3220 PIN 21 & U404 PIN 34)
39 BIAS2
41
DUAL 
TSTRS
48
5VR5 5, 20, 34, 36
(U3201 PIN 5)
AUX1 VDD, 3.3VMODOUT          U3701 
LOW VOLTAGE 
FRACTIONAL-N 
 SYNTHESIZER 
						

							Frequency Generation Circuitry5A-11
6.2 VCO - Voltage Controlled Oscillator
(Refer toVHF Voltage Controlled Oscillator Schematic Diagram on page 5A-25)
The VCOBIC (U3801) in conjunction with the Fractional-N synthesizer (U3701) generates RF in both 
the receive and the transmit modes of operation. The TRB line (U3801 pin 19) determines which 
oscillator and buffer will be enabled. A  sample of the RF signal from the enabled oscillator is routed  
from U3801 pin 12, through a low pass filter, to the prescaler input (U3701 pin 32). After frequency 
comparison in the synthesizer, a resultant CONTROL  VOLTAGE is received at the VCO. This voltage 
is a DC voltage typically between 3.5V and 9.5V when the PLL is locked on frequency.
Figure 5-5: VCO Block Diagram
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(3701 Pin28)
VCC Buffers
TX RF Injection U3701 Pin 32 AUX3 (U3701 Pin2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U3801
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U3701 Pin28)Rx-SW
Tx-SW
Vcc-Logic
(U3701 Pin28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB_IN
LO RF INJECTION
VSFVSF VSF 
						

							5A-12Frequency Generation Circuitry
The RF section of the VCOBIC(U3801) is operated at 4.54 V (VSF), while the control section of the 
VCOBIC and Fractional-N synthesizer (U3701) is operated at 3.3V. The operation logic is shown in 
Ta b l e  
5-1.
In the receive mode, U3801 pin 19 is low or grounded. This activates the receive VCO by enabling the 
receive oscillator and the receive buffer of U3801. The RF signal at U3801 pin 8 is run through a 
matching network. The resulting RF signal  is the LO RF INJECTION and it is applied to the mixer at 
T3302.
During the transmit condition, when PTT is depressed, 3.2 volts is applied to U3801 pin 19. This 
activates the transmit VCO by enabling the transmit oscillator and the transmit buffer of U3801. The 
RF signal at U3801 pin 10 is injected into the input of the PA module (U3501 pin16). This RF signal is 
the TX RF INJECTION. Also in transmit mode, the audio signal to be frequency modulated onto the 
carrier is received through U3701 pin 41.
When a high impedance is applied to U3801 pin19, the VCO is operating in BATTERY SAVER mode. 
In this case, both the receive and transmit oscillators as well as the receive transmit and prescaler 
buffer are turned off.
Table 5-1: VCO Control Logic
Desired 
ModeAUX 4AUX 3TRB
Txn.u.High (@3.2V)High (@3.2V)
Rxn.u.LowLow
Battery Savern.u.Hi-Z/Float 
(@1.6V)Hi-Z/Float (@1.6V) 
						

							Notes For All Schematics and Circuit Boards 5A-13
7.0 Notes For All Schematics and Circuit Boards
* Component is frequency sensitive. Refer to the Electrical Parts List for value and usage.
1.Unless otherwise stated, resistances are in Ohms (k = 1000), and capacitances are in picofarads 
(pF) or microfarads (µF).
2.DC voltages are measured from point indicated to chassis ground using a Motorola DC multime-
ter or equivalent. Transmitter measurements should be made with a 1.2 µH choke in series with 
the voltage probe to prevent circuit loading.
3.Reference Designators are assigned in the following manner:
400/500 Series = Controller
600 Series = Keypad Board
3200 Series  = IF Circuitry
3300 Series  = Receiver
3500 Series = Transmitter
3700 and  
3800 Series = Frequency Generation
4.Interconnect Tie Point Legend:
UNSWB+ = Unswitch Battery Voltage (7.5V)
SWB+ = Switch Battery Voltage (7.5V)
R5 = Receiver Five Volts
CLK = Clock
Vdda = Regulated 3.3 Volts (for analog)
Vddd = Regulated 3.3 Volts (for digital)
CSX = Chip Select Line (not for LVZIF)
SYN = Synthesizer
DACRX = Digital to Analog Voltage (For Receiver Front End Filter)
VSF = Voltage Super Filtered (5 volts)
VR = Voltage Regulator
6-LAYER CIRCUIT BOARD DETAIL VIEWING 
COPPER STEPS IN PROPER LAYER SEQUENCE
LAYER 1 (L1)
LAYER 2 (L2)
LAYER 3 (L3)
LAYER 4 (L4)
LAYER 5 (L5)
LAYER 6 (L6)
INNER LAYERS SIDE 1
SIDE 2 
						

							5A-14 Notes For All Schematics and Circuit Boards
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