Samsung Exynos 5 User Manual

 
      
List of Figures 
Figure Title Page 
Number  Number 
 
Figure 1-1      Block Diagram of Exynos 5250 ......................................................................................................... 1-5 
 
Figure 4-1      GPIO Block Diagram ........................................................................................................................ 4-4 
 
Figure 5-1      Exynos 5250 Clock Domains...

 
      
Figure 13-1      I2C-Bus Block Diagram ................................................................................................................. 13-2 
Figure 13-2      Start and Stop Condition ............................................................................................................... 13-4 
Figure 13-3      I2C-Bus Interface Data Format ..................................................................................................... 13-5 
Figure 13-4      Data...

 
      
List of Tables 
Table Title Page 
Number  Number 
 
Table 5-1      Operating Frequencies in Exynos 5250 ............................................................................................. 5-3 
Table 5-2      APLL, MPLL, BPLL, CPLL and GPLL PMS Value ........................................................................... 5-10 
Table 5-3      EPLL PMS Value ................................................................................................................................

 
      
List of Conventions 
Register RW Access Type Conventions 
Type Definition Description 
R Read Only The application has permission to read the Register field. Writes to read-only fields 
have no effect. 
W Write Only The application has permission to write in the Register field. 
RW Read & Write The application has permission to read and writes in the Register field. The 
application sets this field by writing 1’b1 and clears it by writing 1’b0. 
 
Register Value Conventions 
Expression...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-1  
1 Product Overview 
1.1 Introduction 
Exynos 5250 is a system-on-a-chip (SoC) based on the 32-bit RISC processor for tablets and cell-phones. 
Designed with the 32 nm low power process, features of Exynos 5250 include: 
 Dual core CPU 
 Highest memory bandwidth 
 WQXGA display 
 1080p 60 frame video decoding and encoding hardware 
 3D graphics hardware 
 Image signal processor  
 High-speed interfaces such as eMMC4.5 and USB 3.0...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-2  
Exynos 5250 lowers the Bill of Materials (BOM) by integrating these IPs:  
 DDR3/LPDDR3 interfaces 
 Image signal processor (ISP)  
 Eight channels of I2C for a variety of sensors  
 Variety of USB derivatives (USB Host or Device 3.0,USB Host or Device 2.0)  
 HSIC interfaces with PHY transceivers to connect with 802.11n, Ethernet, HSPA+, and 4G LTE modem 
 C2C for modem sharing DRAM 
The application processor also supports eMMC 4.5...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-3  
1.2 Features 
The key features of Exynos 5250 include: 
 Cortex-A15 dual core subsystem with 64/128-bit SIMD NEON 
 32 KB (Instruction)/32 KB (Data) L1 Cache and 1 MB L2 Cache 
 Core frequency of 1.7 GHz at overdrive/2.0 GHz by binning 
 128-bit Multi-layered bus architecture 
 Internal ROM and RAM for secure booting, security, and general purposes 
 Memory Subsystem: 
 Two ports 32-bit 800 MHz LPDDR3/DDR3 Interfaces 
 Or two ports...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-4  
 One channel AC-97, three channel PCM, and two channel 24-bit I2S audio interface that supports stereo 
channel audio and one channel 24-bit I2S audio interface that supports 5.1 channel audio 
 One channel S/PDIF interface support for digital audio 
 Four channel I2C interface support (up to 400 kbps) for PMIC, HDMI, and general-purpose multi-masters 
 Four channel HS-I2C (up to 3.1 Mbps) 
 Samsung Reconfiguration Processor supports...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-5  
1.3 Block Diagram 
Figure 1-1 illustrates the block diagram of Exynos 5250. 
 
    Figure 1-1   Block Diagram of Exynos 5250 
 Memory/ Storage I/F
LPDDR3 and DDR3
32-bit 1600Mbps 2-port
Max. 12.8GBytes/sec
(LPDDR2 1066Mbps)
SRAM
1x eMMC 4.5(8-bit DDR)
1x SDIO 3.0(4-bit DDR)
2x SD 2.0(4-bit SDR)
2-ch EF-NAND
(8-bit DDR)
Graphics/ Video/ ISP
1080p 60fps codec:
VP8
3D HW: OpenGL ES,
OpenCL
2D HW
ISP & Post processors 
16MP ISP/ 8MP 30fps
3DNR,...

Samsung Confidential  
Exynos 5250_UM 1 Product Overview 
 1-6  
1.4 Product Details 
This section includes: 
 ARM Core 
 Memory Subsystem 
 Display Subsystem 
 Camera and General Scaling Subsystem 
 Graphics, Multimedia Acceleration Hardware and Image Signal Processor  
 Security Subsystem 
 High Speed Interfaces 
 External Peripheral