Anaheim Integrated Circuit LSILS7166 User Manual

							7166-110503-11
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
ALE
8051
80C31
74HC573
7166
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7   
  1
19
18
212
Q8
WR/
RD/
D0
D1
D2
D3
D4
D5
D6
D7
C/D
CS/
WR/ RD/ 19
NOTE:   Port_0 is open drain output. Add pull-up resistors to all Port_0 i/0 l\
ines.
FIGURE 9.  80C31/8051 TO LS7166 INTERFACE IN EXTERNAL ADDRESS MODE
D1            Q1
C
0C
1 D2
D3
D4
D5
D6
D7
D8
2
3
4
5
6
7
8
9
11
  8
  9
10
11
12
13
14
15
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7 
						

							P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.71
2
3
4
5
6
7
8P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
8051
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD
WR
PSEN
ALE/PTXO
RXO 17
16
29
30
11
10
21
22
23
24
25
26
27
28
39
38
37
36
35
34
33
32VCC
31
19
18 9
12
13
15
14ER/VP X1X2
RESET
INT0
INT1
T0
T1
/7166C/D
/7166CS
/7166RD
/7166WR
5 16
17
6
7
3
4
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7   1
19
18
  2/7166WR
/7166RD
/7166C/D
/7166CS
WR
RD C/D
CS
  8
  9
10
11
12
13
14
15 D0
D1
D2
D3
D4
D5
D6
D7R
8
LCTR/LLTC
RBGT/RCTR
CY
BW
Vss 20 V
DD
VCC
FIGURE 10.  8751 INTERFACE TO LS7166 IN I/O MODE
UR
LS7166
7166-092304-12 
						

							7166-110103-13
16
173
4
6
7
GND
VDDCY
BW
LCTR/LLTC
RBGT/RCTR A COUNT IN
B COUNT IN
D0
D1
D2
D3
D4
D5
D6
D7
  8
  9
10
11
12
13
14
15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
A0
CS/ 2
WR/ 1
RD/ 19
ADDRESS 
DECODE
D Q
CLK
Q
CL
PR
74HC74
  2
  5
  6
  9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 20
LS7166 +5V 
+5V
5
6
4
2
1
3
1
4
5 6
74HC08
U5   A
U6   B 74HC04
1
2
3  4
74HC0474HC08
U6   A
U5   B
74HC373
68HC11A1 27
26
2825
2442
43
44
45
46
47
31
32
33
34
35
36
37
38
16
15
14
13
12
11
10
  9
5
4
3
2
1
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
MODB
U1
30
29
39
41
40
8
7
6
17
18
19
20
22
21 XTAL
EXTAL
RESET
IRQ
XIRD
PA0
PA1
PA2 PE0
PE1
PE2
PE3
YRH
YRL PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7  3
  4 
  7
  8
13 14
17
18
  1 11 U3
OC
G
D0
D1
D2
D3
D4
D5
D6
D7
C/D
CS
WR
RD
FIGURE  11. LS7166 TO 68HC11 INTERFACE
18
2
E
AS
RW 
						

							7166-110503-14
ADDRESS
DECODER
A0
IOR/ IOW/ A8
A7
A6
A5
A4
A3
A2
A1
AEN
D7
D6
D5
D4
D3
D2
D1
D0
  8
  9
10
11
12
13
14
15
D0
D1
D2
D3
D4
D5
D6
D7
CS
WR
RD
C/D 1
19
18 2 IOR/
D0
D1
D2
D3
D4
D5
D6
D7
ISA BUS
FIGURE 12. LS7166 INTERFACE EXAMPLE
A0
IOW/
LS7166 
						

							7166-062306-15
6800068008
68010 7166
DATA BUS
A0
  DECODE
  D
CK  WR
 RD
 D0 - D7
R/W
LDS/UDS
DTACK
CLK  LS373
CK
ADDRESS
S74
   CS
D Q
 D
Q
CK
 S74
S
D
CK
       S74
+V
+V
CLOCK
R
FIGURE 13. 68000 INTERFACE TO LS7166
    AS
  R
C/D
 Q
 S S
 QR 
						

							C Sample Routines for Interfacing with LS7166
#include  
#include  
#include  
#define DATAMODE(arg)(arg + 0)
#define CTRLMODE(arg)(arg + 1)
/************************************************************************/
/* MCR (Master Control Register) */
/* Select MCR */
#define MCR(arg)(arg | 0x00)
/* Master Reset */
/* Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL, COMPT, and PR/OL Byte Pointer */
/* Set PR and SIGN */
#define Rst_Master0x20
/* Reset COMPT */
#define Rst_COMPT0x10
/* Transfer PR to CNTR (24 bits) */
#define Trf_PR_CNTR0x08
/* Reset CNTR, BWT and CYT */
/* Set SIGN bit */
#define Rst_CNTR_BWT_CYT_Set_SIGN     0x04
/* Transfer CNTR to OL (24 bits) */
#define Trf_CNTR_OL0x02
/* Reset PR/OL Byte Pointer */
#define Rst_BP0x01
/************************************************************************/
/* ICR (Input Control Register) */
/* Select ICR */
#define ICR(arg)(arg | 0x40)
              _____    ____
/* Select LCTR / LLTC as Load-CNTR  Input */
#define LCNTR0x00
              _____    ____
/* Select LCTR / LLTC as Load-OL  Input */
#define LOL0x20
               _____    ____
/* Select ABGT / RCTR as Reset-CNTR Input */  
#define RCNTR0x00
               _____    ____
/* Select ABGT / RCTR as Enable / Disable Gate for A / B Inputs */
#define ABGate0x10
/* Disable A / B Inputs */
#define DisAB0x00
/* Enable  A / B Inputs */
#define EnAB0x087166-081507-16 
						

							/* Decrement CNTR once for A / B = 1, if A / B inputs are enabled */
#define Decr_CNTR0x04
/* Increment CNTR once for A / B = 1, if A / B inputs are enabled */
#define Incr_CNTR0x02
/* Set Input A = Up Count Input, Input B = Down Count Input */
#define AUP_BDN0x00
/* Set Input A = Count Input, Input B = Count Direction  Input */
/* B = 0 selects Up Count Mode */
/* B = 1 selects Down Count Mode  */
#define AIN_BDIR0x01
/************************************************************************/
/* OCCR (Output Control Register)  */
/* Select OCCR */
#define OCCR(arg)(arg | 0x80)
          ___     _____
/* Set CY = COMP Comparator Out (active 0)  */
          ___
/* Set BW = COMPT Comparator Toggle Output  */ 
#define COMPN_COMPT0x30
         ___
/* Set CY = CY   */
          ___
/* Set BW = BW  */ 
#define CY_BW0x20
         ___    ___
/* Set CY = CY   */
         ____   ____ 
/* Set BW = BW   */ 
#define CYN_BWN0x00
/* Set Binary or BCD Count Mode  */
#define Bin_BCD_Cnt0x00
/* Set 24 Hr Clock Mode – Overrides BCD / Binary Modes  */
#define Clk_24HR_Cnt0x08
/* Set Normal Count Mode  */
#define Nrml_Cnt0x00
/* Set Divide by N Count Mode  */
#define div_N_Cnt0x04
/* Set Non Recycle Count Mode  */
#define Nrcyc_Cnt0x02
/* Set Binary Count Mode  */
#define Bin_Cnt0x00
/* Set BCD Count Mode  */
#define BCD_Cnt0x01
/************************************************************************/7166-081507-17 
						

							/* QR (Quadrature Register)  */
/* Select QR */
#define QR(arg)(arg | 0xC0)
/* Enable x4 Quadrature Mode  */
#define En_x4QM0x03
/* Enable x2 Quadrature Mode  */
#define En_x2QM0x02
/* Enable x1 Quadrature Mode  */
#define En_x1QM0x01
/* Disable Quadrature Mode  */
#define Dis_QM0x00
/************************************************************************/
/* Initialize 7166 */
void Init_7166(int Addr)
/* Initialize 7166 as follows
Do a Master Reset
Set ICR as follows
Set Input A = Up Count
Set Input B = Down Count
Disable Inputs A/B
Enable Reset_CNTR input
Enable Load_CNTR input
Set OCCR – Normal Count Mode
Disable QM
Enable A and B Inputs
*/
void Init_7166(int Addr){
/* Master Reset */
outp(CTRLMODE(Addr), MCR(Rst_Master));
/* Set ICR */
outp(CTRLMODE(Addr), ICR(AUP_BDN + DisAB + RCNTR + LCNTR));
/* Set OCCR */
outp(CTRLMODE(Addr), OCCR(Nrml_Cnt));
/* Set QR */
outp(CTRLMODE(Addr), QR( Dis_QM));
/*Enable A and B inputs */
outp(CTRLMODE(Addr), ICR(EnAB));
} 7166-081507-18 
						

							/* Write data into 7166 Preset Register 
Addr has address of 7166 counter
Data has 24 bit data to be written to PR register */
void Write_7166_PR(int Addr, unsigned long Data);
void Write_7166_PR(int Addr, unsigned long Data){
outp(CTRLMODE(Addr), MCR(Rst_BP));
outp(DATAMODE(Addr), (unsigned char)Data);
Data >>= 8;
outp(DATAMODE(Addr), (unsigned char)Data);
Data >>= 8;
outp(DATAMODE(Addr), (unsigned char)Data);
}
/* Read 7166 Output Latch
Addr has address of 7166 counter
Data returns 24 bit OL register value. */
unsigned long Read_7166_OL(int Addr);
unsigned long Read_7166_OL(int Addr){
unsigned long Data = 0;
outp(CTRLMODE(Addr), MCR(Rst_BP + Trf_CNTR_OL));
Data |= (unsigned long) inp(DATAMODE(Addr));
lrotr(Data,8);
Data |= (unsigned long) inp(DATAMODE(Addr));
lrotr(Data,8);
Data |= (unsigned long) inp(DATAMODE(Addr));
lrotr(Data,16);
return(Data);
}
/* Read Output Status Register 
Addr has address of 7166 counter
returns OSR data  */
unsigned long Read_7166_OSR(int Addr);
unsigned long Read_7166_OSR(int Addr){
return(inp(CNTRLMODE(Addr)));
}7166-121508-19