Anaheim Integrated Circuit LSILS7366R Spec Sheet

							GENERAL FEATURES: 
• Operating voltage: 3V to 5.5V (V
DD - VSS)
• 5V count frequency:  40MHz
• 3V count frequency:  20MHz
• 32-bit counter (CNTR).
• 32-bit data register (DTR) and comparator.
• 32-bit output register (OTR).
• Two 8-bit mode registers (MDR0, MDR1) 
   for programmable functional modes.
• 8-bit instruction register (IR).
• 8-bit status register (STR).
• Latched Interrupt output on Carry or Borrow or Compare or Index.
• Index driven counter load, output register load or counter reset.
• Internal quadrature clock decoder and filter.
• x1, x2 or x4 mode of quadrature counting.
• Non-quadrature up/down counting.
• Modulo-N, Non-recycle, Range-limit or 
  Free-running modes of counting
• 8-bit, 16-bit, 24-bit and 32-bit programmable configuration
  synchronous (SPI) serial interface
•  LS7366R  (DIP), LS7366R-S  (SOIC), LS7366R-TS  (TSSOP)
                            - See Figure 1 -
SPI/MICROWIRE  (Serial Peripheral Interface): 
• Standard 4-wire connection: MOSI, MISO, SS/ and SCK. 
• Slave mode only.
GENERAL DESCRIPTION:
LS7366R is a 32-bit CMOS counter, with direct interface for quadra-
ture clocks  from incremental encoders. It  also interfaces with the
index  signals  from  incremental  encoders  to  perform  variety  of
marker functions. 
For  communications  with  microprocessors  or  microcontrollers,  it
provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os
are SS/, SCK, MISO and MOSI. The data transfer between a micro-
controller and a slave LS7366R is synchronous. The synchroniza-
tion is done by the SCK clocks supplied by the microcontroller. Each
transmission is organized in blocks of 1 to 5 bytes of data. A trans-
mission cycle is intitiated by a high to low transition of the SS/ input\
.
The first byte received in a transmission cycle is always an instruc-
tion  byte, whereas the second  through  the  fifth  bytes  are  always
interpreted as data bytes. A transmission cycle is terminated with
the low to high transition of the SS/ input. Received bytes are shifted
in at the MOSI input, MSB first, with the leading edges (high transi-
tion) of the SCK clocks. Output data are shifted out on the MISO
output, MSB first, with the trailing edges (low transition) of the SCK\
clocks.
   32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE
LSI/CSI
L SI  C o m pute r Sy ste m s, I n c.   12 35 W alt  W hit m an  Ro ad, M elv ill e, N Y 1 174 7     (631 ) 2 71 -0 40 0   F A X  (631 ) 2 7 1-0 4 05
LS7366R
U
L®
A3800
        February  2009
7366R-021309-1
Read  and  write  commands  cannot  be  combined.
For example, when the device is shifting out read
data  on  MISO  output,  it  ignores  the  MOSI  input,
even though the SS/ input is active. SS/ must be
terminated  and  reasserted  before  the  device  will
accept a new command. 
The counter can be configured to operate as 1, 2, 3
or  4-byte  counter.  When  configured  as  an  n-byte
counter, the CNTR, DTR and OTR are all config-
ured as n-byte registers, where n = 1, 2, 3 or 4. 
The  content  of  the  instruction/data  identity  is
automatically adjusted to match the n-byte configu-
ration. For example, if the counter is configured as a
2-byte  counter,  the  instruction  “write  to  DTR”
expects 2 data bytes following the instruction byte.
If the counter is configured as a 3-byte counter, the
same instruction will expect 3 bytes of data follow-
ing the instruction byte.
Following the transfer of the appropriate number of
bytes any further attempt of data transfer is ignored
until a new instruction cycle is started by switching
the SS/ input to high and then low.
The  counter  can  be  programmed  to  operate  in  a
number  of  different  modes,  with  the  operating
characteristics  being  written  into  the  two  mode
registers  MDR0  and  MDR1.  Hardware  I/Os  are
provided  for  event  driven  operations,  such  as
processor interrupt and index related functions.
   1
   2
   3
   4
   5  
   6
   7
    8
    9
10
  11
 12
 13
V
SS
14 VDD
B
A
INDEX/ LFLAG/
SS/
SCK
LS7366R
MISO MOSI f
CKi
fCKO
 
CNT_EN
DFLAG/
FIGURE 1
LSI
  PIN ASSIGNMENT
       TOP VIEW 
						

							7366R-081507-2I/O Pins:
Following is a description of all the input/output pins.
A (Pin 12) B (Pin 11)
Inputs. A and B quadrature clock outputs from incremental
encoders are directly applied to the A and B inputs of the
LS7366R. These clocks are ideally 90 degrees out-of-phase
signals. A and B inputs are validated by on-chip digital filters
and then decoded for up/down direction and count clocks.
In non-quadrature mode, A serves as the count input and B
serves as the direction input  (B = high enables up count, 
B = low enables down count). In non-quadrature mode, 
the A and B inputs are not filtered internally, and are instan-
taneous in nature.
INDEX/ (Pin 10)
Input. The INDEX/ is a programmable input that can be
driven directly by the Index output of an incremental encod-
er.  It can be programmed via the MDR0 to function as one
of the following:
LCNTR (load CNTR with data from DTR), RCNTR (reset
CNTR), or LOTR (load OTR with data from CNTR).
Alternatively, the INDEX input can be masked out for no
functionality.
In quadrature mode, the INDEX/ input can be configured to
operate in either synchronous or asynchronous mode. In the
synchronous mode the INDEX/ input is sampled with the
same filter clock used for sampling the A and the B inputs
and must satisfy the phase relationship in which the INDEX/
is in the active level of Logic 0 during a minimum of a
quarter cycle of both A and B High or both A and B Low. In
non-quadrature mode, the INDEX/ input is unconditionally
set to the asynchronous mode. In the asynchronous mode,
the INDEX/ input is not sampled and can be applied in any
phase relationship with respect to A and B. 
fCKi  (Pin 2), fCK0 (Pin 1)
Input, Output. A crystal connected between these 2 pins
generates the basic clock for filtering  the A, B and INDEX/
inputs in the quadrature count mode. Instead of a crystal the
fCKi input may also be driven by an external clock.
The frequency at the fCKi input is either divided by 2
(if MDR0  = 1) or divided by 1 (if MDR0  = 0) for
the filter circuit. For proper filtering of the A, B and the Index/
inputs the following condition must be satisfied:
              ff ³ 4fQA
Where ff is the internal filter clock frequency derived from the
fCKi in accordance with the status of MDR0  and fQA is
the maximum frequency of Clock A in quadrature mode. In
non-quadrature count mode, fCKi is not used and should be
tied off to any stable logic state.
SS/ (Pin 4)
A high to low transition at the SS/ (Slave Select) input
selects the LS7366R for serial bi-directional data transfer; a
low to high transition disables serial data transfer and brings
the MISO output to high impedance state. This allows for the
accommodation of multiple slave units on the serial I/O.
 CNT_EN (Pin 13)
Input. Counting is enabled when CNT_EN input is high; counting
is disabled when this input is low. There is an internal pull-up
resistor on this input.
LFLAG/ (Pin 8), DFLAG/ (Pin 9)
Outputs. LFLAG/ and DFLAG/ are programmable outputs to flag
the occurences of Carry (counter overflow), Borrow (counter
underflow), Compare (CNTR = DTR) and INDEX. The LFLAG/ is
an open drain latched output. In contrast, the DFLAG/ is a push-
pull instantaneous output. The LFLAG/ can be wired in multi-
slave configuration, forming a single processor interrupt line.
When active LFLAG/ switches to logic 0 and can be restored to
the high impedence state only by clearing the status register,
STR. In contrast, the DFLAG/ dynamically switches low with
occurences of Carry, Barrow, Compare and INDEX conditions.
The configuration of LFLAG/ and DFLAG/ are made through the
control register MDR1. 
MOSI (RXD) (Pin 7)
Input. Serial output data from the host processor is shifted into
the LS7366R at this input.
MISO (TXD) (Pin 6)
Output. Serial output data from the LS7366R is shifted out on
the MISO (Master In Slave Out) pin. The MISO output goes into
high impedance state when SS/ input is at logic high, providing
multiple slave-unit serial outputs to be wire-ORed.
SCK (Pin 5)
Input. The SCK input serves as the shift clock input for transmit-
ting data in and out of LS7366R on the MOSI and the MISO
pins, respectively.  Since the LS7366R can operate only in the
slave mode, the SCK signal is provided by the host processor
as a means for synchronizing the serial transmission between
itself and the slave LS7366R.
REGISTERS:
The following is a list of LS7366R internal registers:
Upon power-up the registers DTR, CNTR, STR, MDR0 and
MDR1 are reset to zero.
DTR. The DTR is a software configurable 8, 16, 24 or 32-bit
input data register which can be written into directly from MOSI,
the serial input. The DTR data can be transferred into the 32-bit
counter (CNTR) under program control or by hardware index
signal. The DTR can be cleared to zero by software control.  In
certain count modes, such as modulo-n and range-limit, DTR
holds the data for n and the count range, respectively. In
compare operations, whereby compare flag is set, the DTR is
compared with the CNTR.The information included herein is believed to be
accurate and reliable.  However, LSI Computer Systems,Inc.  assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which mayresult from its use. 
						

							STR. The STR is an 8-bit status register which stores 
          count related status information.  
 CY     BW      CMP      IDX      CEN     PLS    U/D    S
     7          6          5           4           3          2        1        0 
 
7366R-102708-3IR.  The IR is an 8-bit register that fetches instruction bytes from
the received data stream and executes them to perform such
functions as setting up the operating mode for the chip (load the
MDR) and data transfer among the various registers.
B7    B6    B5    B4    B3    B2    B1    B0                B2 B1 B0 = XXX  (Don’t care)           
  B5 B4 B3 = 000:  Select none
= 001:  Select MDR0  
= 010:  Select MDR1
= 011:  Select DTR
= 100:  Select CNTR
= 101:  Select OTR 
= 110:  Select STR
= 111:  Select none
                            B7 B6 =  00:  CLR register
=  01:  RD register
=  10:  WR register
=  11:  LOAD register
The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1. 
                                                         TABLE 1
Number of BytesOP Code           Register      Operation
MDR0Clear MDR0 to zero
MDR1Clear MDR1 to zero
1  CLRDTRNone
CNTRClear CNTR to zero
OTRNone
STRClear STR to zero
MDR0Output MDR0 serially on TXD (MISO)
MDR1Output MDR1 serially on TXD (MISO)
2 to 5  RDDTRNone
CNTRTransfer CNTR to OTR, then output OTR serially 
on TXD (MISO)
OTROutput OTR serially on TXD (MISO)
STROutput STR serially on TXD (MISO)
MDR0Write serial data at RXD (MOSI) into MDR0
MDR1Write serial data at RXD (MOSI) into MDR1
2 to 5  WRDTRWrite serial data at RXD (MOSI) into DTR
CNTRNone
OTRNone
STRNone
MDR0None
MDR1None
1  LOADDTRNone
CNTRTransfer DTR to CNTR in “parallel”
OTRTransfer CNTR to OTR in “parallel”CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from 
the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input.  
By means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR. 
OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output. 
Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a 
convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process.CY:  Carry (CNTR overflow) latch
BW:  Borrow (CNTR underflow) latch
 CMP:  Compare (CNTR = DTR) latch
   IDX:  Index latch
     CEN:  Count enable status:  0: counting disabled,
                                                   1: counting enabled
   PLS:  Power loss indicator latch; set upon power up
    U/D:  Count direction indicator:  0: count down, 1: count up 
       S:  Sign bit.  1:  negative, 0:  positive 
						

							7366R-041906-4ABSOLUTE MAXIMUM RATINGS:
(All voltages referenced to Vss)
Parameter                             Symbol                           Values                                     Unit
DC Supply VoltageVDD             +7.0V
Input VoltageVIN                    Vss - 0.3 to VDD + 0.3           V
Operating Temperature TA                            -25  to +80                                   o
C
Storage TemperatureTSTG                          65  to +150                                 o
C     MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes.             
Upon power-up MDR1 is cleared to zero.
                          B7      B6      B5      B4      B3      B2      B1      B0
B1 B0 = 00:  4-byte counter mode
       = 01:  3-byte counter mode
       = 10:  2-byte counter mode.
       = 11:  1-byte counter mode
      B2 = 0:   Enable counting
        = 1:   Disable counting
      B3 =   :   not used      
      B4 = 0:   NOP
        = 1:   FLAG on IDX (B4 of STR)
      B5 = 0:   NOP
        = 1:   FLAG on CMP (B5 of STR)
      B6 = 0:   NOP
        = 1:   FLAG on BW (B6 of STR)
      B7 = 0:   NOP
        = 1:   FLAG on CY (B7 of STR)MDR0. The MDR0 (Mode Register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366R. The MDR0 is
written into by executing the write-to-MDR0 instruction via the instruction register. Upon power up MDR0 is cleared to zero. The
following is a breakdown of the MDR bits:
                          B7      B6      B5      B4      B3      B2      B1      B0
B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction).
       = 01:  x1 quadrature count mode (one count per quadrature cycle).
       = 10:  x2 quadrature count mode (two counts per quadrature cycle).
       = 11:  x4 quadrature count mode (four counts per quadrature cycle).
B3 B2 = 00: free-running count mode.
       = 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load).
       = 10: range-limit count mode (up and down count-ranges are limited between DTR and zero,
             respectively; counting freezes at these limits but resumes when direction reverses).
       = 11: modulo-n count mode  (input count clock frequency is divided by a factor of (n+1),
         where n = DTR, in both up and down directions).
B5 B4 = 00: disable index.
       = 01:  configure index as the load CNTR input (transfers DTR to CNTR).
       = 10:  configure index as the reset CNTR input (clears CNTR to 0).
       = 11:  configure index as the load OTR input (transfers CNTR to OTR).
     B6 = 0:  Asynchronous Index
       = 1:  Synchronous Index (overridden in non-quadrature mode)
 B7 =  0:  Filter clock division factor = 1
       = 1:  Filter clock division factor = 2NOTE: Applicable to both
LFLAG/ and DFLAG/ 
						

							DC Electrical Characteristics.  (TA = -25˚C to +85°C)
   Parameter                                  Symbol        Min.             TYP          Max.             Unit                      Remarks
Supply Voltage                                 VDD3.0-5.5V-
Supply CurrentIDD300400450µAVDD = 3.0V
IDD700800950µAVDD = 5.0V
Input Voltages
fCKi,  Logic high VCH2.3--VVDD = 3.0V
VCH3.7--VVDD = 5.0V
fCKi,  Logic Low VCL--0.7VVDD = 3.0V
VCL--1.3VVDD = 5.0
All other inputs, Logic HighVAH2.1-VVDD = 3.0V
VAH3.5-VVDD = 5.0V
All other inputs, Logic LowVAL--0.5VVDD = 3.0V
VAL--1.0VVDD = 5.0V
Input Currents:
CNT_EN LowIIEL-3.05.0µAVAL = 0.7V, VDD = 3.0V
IIEL-                  10.0          15.0µAVAL = 1.2V, VDD = 5.0V
CNT_EN HighIIEH-1.03.0µAVAH = 1.9V, VDD = 3.0V
IIEH-6.09.0µAVAH = 3.2V, VDD = 5.0V
All other inputs, High or Low--00µA                     -
Output Currents:
LFLAG, DFLAG Sink IOFL             -1.3               -2.0-mAVOUT = 0.5V, VDD = 3.0V
 IOFL             -3.2               -4.0-mAVOUT = 0.5V, VDD = 5.0V
LFLAG Source-00-mA                   Open Drain Output
DFLAG SourceIOFH1.01.8-mA                   VOUT = 2.5V, VDD = 3.0V
IOFH2.83.6-mAVOUT = 4.5V, VDD = 5.0V
fCKO Sink IOCL            -1.3                -2.0-mAVOUT = 0.5V, VDD = 3.0V
 IOCL            -3.2                -4.0-mAVOUT = 0.5V, VDD = 5.0V
fCKO SourceIOCH             1.32.0-mAVOUT = 2.5V, VDD = 3.0V
 IOCH3.24.0-mAVOUT = 4.5V, VDD = 5.0V
TXD/MISO:
 Sink IOML           -1.5                -2.4-mAVOUT  = 0.5V, VDD = 3.0V
 IOML           -3.8                -4.8-mAVOUT  = 0.5V, VDD = 5.0V
 Source IOMH            1.52.4-mAVOUT  = 2.5V, VDD = 3.0V
 IOMH            3.84.8-mAVOUT  = 4.5V, VDD = 5.0V
7366R-120407-5Transient Characteristics.  (TA = -25˚C to +85˚C, VDD = 5V ± 10%)
      Parameter                                    Symbol          Min. Value       Max.Value        Unit                    Remarks
(See Fig. 2) 
SCK High Pulse WidthtCH100-ns-
SCK Low Pulse WidthtCL100-ns-
SS/ Set Up TimetCSL100-ns-
SS/ Hold  TimetCSH100-ns-
Quadrature Mode
(See Fig. 5, 7 & 8 )
fCKI High Pulse Widtht112-ns-
fCKI  Pulse Widtht212-ns-
fCKI FrequencyfFCK-40MHz-
Effective Filter Clock fF Periodt325-nst3 = t1+t2, MDR0  = 0
t350-nst3 = 2(t1+t2), MDR0  = 1
Effective Filter Clock fF frequencyfF-40MHzfF =  1/ t3
Quadrature Separationt426-nst4 > t3
Quadrature Clock Pulse Widtht552-nst5 ³ 2t3
Quadrature Clock frequencyfQA, fQB-9.6MHzfQA = fQB < 1/4t3
Quadrature Clock to Count DelaytQ14t35t3--
x1 / x2 / x4 Count Clock Pulse WidthtQ212-nstQ2 = (t3)/2
Index Input Pulse Widthtid32-nstid > t4
Index Set Up Timetis-5ns-
Index Hold Timetih-5ns-
Quadrature clock to       tfl4.5t35.5t3ns-
DFLAG/ or LFLAG/ delay
DFLAG/ output width       tfw26-nstfw = t4 
						

							   
   Parameter                                Symbol         Min. Value   \
     Max.Value           Unit                Remarks
Non-Quadrature Mode
(See Fig. 6 & 9) 
Clock A - High Pulse Width  t
6 12   -  ns                  -
Clock A - Low Pulse Width  t
7 12   -  ns                  -
Direction Input B Set-up Time  t
8S 12  -  ns                  -
Direction Input B Hold Time t
8H10 - ns                  -
CNT_EN Set-up Time  t
9S 12  -  ms                 -
CNT_EN Hold Time t
9H12 - ms                 -
Clock Frequency (non-Mod-N) f
A- 40 MHz fA = (1/(t6 + t7))
Clock to DFLAG/ or t
1020 - ns                  -
LFLAG/ delay
DFLAG/ output width t
1112 - ns t10 = t7
Transient Characteristic s.  (TA = -25˚C to +85˚C,  VDD = 3.3V ± 10%)
       Parameter                                    Symbol          Min. Va\
lue       Max.Value        Unit                    Remarks
(See Fig. 2)  
SCK High Pulse Width t
CH120 - ns -
SCK Low Pulse Width t
CL120 - ns -
SS/ Set Up Time t
CSL120 - ns -
SS/ Hold  Time t
CSH120 - ns -
Quadrature Mode
(See Fig. 5, 7 & 8)
f
CKI High Pulse Width t124 - ns -
f
CKI  Pulse Width t224 - ns -
f
CKI Frequency fFCK- 20 MHz -
Effective Filter Clock fF Period t
350 - ns t3 = t1+t2, MDR0  = 0
t
3100 - ns t3 = 2(t1+t2), MDR0  = 1
Effective Filter Clock f
F frequency fF- 20 MHz fF =  1/ t3
Quadrature Separation t452 - ns t4 > t3
Quadrature Clock Pulse Width t5105 - ns t5  ³  2t3
Quadrature Clock frequency fQA, fQB- 4.5 MHz fQA = fQB < 1/4t3
Quadrature Clock to Count Delay tQ14t35t3- -
x1/x2/x4 Count Clock Pulse Width t
Q225 - ns tQ2 = (t3)/2
Index Input Pulse Width ti
d60 - ns tid > t4
Index Set Up Time tis- 10 ns -
Index Hold Time ti
h- 10 ns -
Quadrature clock to        t
fl4.5t35.5t3ns -
DFLAG/ or LFLAG/ delay
DFLAG/ output width        t
fw52 - ns tfw = t4
Non-Quadrature Mode
(See Fig. 6 & 9) 
Clock A - High Pulse Width t
624 - ns -
Clock A - Low Pulse Width t
724 - ns -
Direction Input B Set-up Time t
8S24 - ns -
Direction Input B Hold Time t
8H24 - ns -
Clock Frequency (non-Mod-N) f
A- 20 MHz fA = (1/(t6 + t7))
Clock to DFLAG/or t
940 - ns -
LFLAG/ delay
DFLAG/ output width t
1024 - ns t10 = t7
7366R-012609-6 
						

							Note 1.  The SPI port of the host MCU must be set up as follows:
   1.  SPI master mode.
   2.  SCK idle state = low
   3.  Clock edge for MOSI data shift = high to low
              4.  Clock edge for input data (MISO) sample by the Processor = low to high (or bit middle)
Note 2.  To conform with the multibyte transmission protocol of LS7366R, the SS/ output port 
              of the MCU may require direct manipulation by the application program.
FIGURE 2.  SPI TIMINGS7366R-041906-7 tCSH
  tCL     tCH
 tCSL
MSB
LSB
SS/
SCK
MOSI
MISO
HIGH IMPEDANCE
( )( )
( )( )
( )( )
( )( ) 
						

							D7 D6 D5 D4 D3
D3
D2 D1 D0
D2D6 D5D7 D4
X X XRANDOM DATA
X X X
D1 D0
X
SS/
SCK
MOSI
MISO BIT #
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
START OF NEW COMMAND
RD MDR1
DATAWR MDR1tCSL
BIT # 7 6 5 4 3 2 1 0
tCHtCL
TRI-STATE
D7 D6 D5 D4 D3
D3 D2 D1 D0
D2D6 D5D7 D4 XXX
X X X
D1 D0
SS/
SCK
MOSI
MISO BIT # 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
RD CNTR
tCSI
BIT # 7 6 5 4 3 2 1 0
BYTE 1 BYTE 0
CLR STR
RANDOM DATA
7 6 5 4 3 2 1 0
TRI-STATE
NOTE:  Write to MDR1 followed by Read from MDR1 operation
7366R-120407-8
FIGURE 3. WR MDR1 - RD MDR1
FIGURE 4. RD CNTR - CLR STR
FIGURE 5. f
CKI, A, B and INDEX
Note 1
.  Synchronous index coincident with both A and B high.
Note 2 .  Synchronous index coincident with both A and B low.. 
Note 3 .  f
F is the internal effective filter cloc k.
NOTE:  Read CNTR (in 2-byte configuration) followed by CLR STR operatio n.
fCKi
t1t2
ff  (Note 3)
(MDR0  = 0)
ff (Note 3)
(MDR0  = 1)
A
B
INDEX/
t3
t3
t5t5
t4   t4 t4  t4
Note 1 Note 2
tid
tistihtistih 
						

							7366-081507-9
UP  DOWN
A
B
X4_CLK
X2_CLK
X1_CLK
(see note)
(see note)
(see note)
tQ1
tQ2
      Note:   x1, x2, and x4 CLKs are internal up/down clocks derived from filtered a\
nd decoded quadrature clocks.
                           FIGURE 7. A/B QUADRATURE CLOCKS vs INTERNAL C\
OUNT CLOCKS
                                                                Note:   CNTR values are indicated in 3-byte mode
                                          FIGURE 8.  QUADRATURE CLOCKS v\
s FLAG OUTPUTS
FIGURE 6. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE
UP                                                                  DOWN
A
B
X4_CLK
tfl
CNTR
DFLG/
LFLG/
tfl
CY CMP                                          BW
FFFFFC
FFFFFD
FFFFFE FFFFFF
FFFFFFFFFFFE FFFFFD
000000
000001
000002000001
000000
 (SHOWN WITH DTR = 000OO1)
tfw
DOWN UP DOWN
t
6t7t8s t8H
B
A
t9s
CNT_ENt9H 
						

							7366R-050106-10
NOTE:  CNTR values are indicated in 2-byte mode
FIGURE 9.  SINGLE-CYCLE, NON-QUADRATURE
NOTE:  CNTR values are indicated in 1-byte mode
FIGURE 10.  MODULO-N, NON-QUADRATURE
NOTE:  CNTR values are indicated in 1-byte mode
FIGURE 11.  RANGE-LIMIT, NON-QUADRATURE
INDX/ DFLG/CNTR
A B
FFFFFFCFFFFFFDFFFFFFEFFFFFFF     0
     2     1      0FFFFFFF
CY
t9t10
t11CNTR DISABLED  CNTR DISABLED
(Shown with DTR = 2)   
CNTR ENABLED
(LOAD CNTR)
UP                                        DOWN
DFLAG/ CNTR
A B
000000
 000002      000001  000000
CMP
 (Shown with DTR = 3)
BW
UP DOWN
000001000002000003000003000000000001000002000001
DFLAG/CNTR
A B
000003
  000002 000001
CMP
(Shown with DTR = 3 )
UP                                                                    DOWN
000000
 000001  000002
 
000000
BW           BW
BWCMPCMP CMP