Casio Qt 6100 Service Manual
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Page 51
— 49 — 8-3. RESET CIRCUIT The reset circuit is as follows. 8-4. POWER SUPPLY CIRCUIT 1 VP (DC 19V) For the drawer circuit VOP (DC 5.2V) For the COM2, 3 power and display ON/OFF LED VCC (DC 5V) For the logic circuit power The power supply circuit is as follows.
Page 52
— 50 — 8-5. POWER SUPPLY CIRCUIT 2 VBAT (DC 3.3V) For the battery V1.5 (DC 1.5V) For the CPU core V1.8 (DC 1.8V) For the PCMCIA core The power supply circuit is as follows. 8-6. DRAWER I/F CIRCUIT The drawer open circuit is as follows.
Page 53
— 51 — 8-7. CPU (IC26: SH7751) 8-7-1. Pin Assignment 193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256 XTAL2EXTAL2VDD-RTCVSS-RTCCA NMI//MD6/ TXD MD2/RXD2RXDTCLKMD8/SCKMD1/TXD2MD0/SCK2MD7/AUDSYNCAUDCK AUDATA0AUDATA1 AUDATA2AUDATA3ReservedMD3/MD4/MD5 DACK0DACK1DRAK0DRAK1 STATUS0STATUS1 /BRKACKTDO VDD-PLL2VSS-PLL2VDD-PLL1VSS-PLL1VDD-CPGVSS-CPGXTALEXTAL...
Page 54
— 52 — 8-7-2. Block Diagram Lower 32-bit data 64-bit data (store) CPG INTC SCI (SCIF) RTC TMU External (SH) bus interface DMAC 32-bit data 29-bit addres s 32-bit dataAddress 32-bit data 32-bit data Upper 32-bit data 32-bit address (instructions) 32-bit data (instructions) 32-bit address (data) Peripheral address bus 26-bit SH bus address32-bit PCI address/ data 32-bit SH bus data Peripheral data bus UBC 32-bit data (store) 32-bit data (load) CPU I cacheO cacheITLB UTLB Cache andTLB controller FPU BSC:...
Page 55
— 53 — 8-7-3. Pin Function NO. PIN NAME I/O DESCRIPTION 1 TMS I Mode (H-UDI) 2 TCK I Clock (H-UDI) 3 VDDQ Power IO VDD 4 VSSQ Power IO GND 5 TDI I Data in (H-UDI) 6 CSO O Chip select 0 7 CS1 O Chip select 1 8 CS4 O Chip select 4 9 CS5 O Chip select 5 10 CS6 O Chip select 6 11 BS O Bus start 12 WE0/REG O D7-D0 select signal 13 WE1 O D15-D8 select signal 14 D0 I/O Data 15 VDDQ Power IO VDD 16 VSSQ Power IO GND 17 VDD Power Internal...
Page 56
— 54 — NO. PIN NAME I/O DESCRIPTION 55 VDDQ Power IO VDD 56 VSSQ Power IO GND 57 A4 58 A5 59 A6 60 A7 61 A8 O Address 62 A9 63 A10 64 A11 65 A12 66 A13 67 VDDQ Power IO VDD 68 VSSQ Power IO GND 69 A14 70 A15 O Address 71 A16 72 A17 73 CAS2/DQM2 O D23-D16 select signal 74 CAS3/DQM3 O D31-D24 select signal 75 D16 76 D17 I/O Data 77 D18 78 D19 79 VDDQ Power IO VDD 80 VSSQ Power IO GND 81 VDD Power Internal VDD...
Page 57
— 55 — NO. PIN NAME I/O DESCRIPTION 110 WE3/ICIOWR O D31-D24 select signal 111 VDD Power Internal VDD 112 VSS Power Internal GND 113 SLEEP I Sleep 114 PCIGNT4 O Bus grant (host function) 115 PCIGNT3 O Bus grant (host function) 116 PCIGNT2 O Bus grant (host function) 117 PCIREQ4 I* Bus request (host function) 118 PCIREQ3/MD10 I* Bus request (host function)/mode 119 VDDQ Power IO VDD 120 VSSQ Power IO GND 121 PCIREQ2/MD9 I* Bus request (host...
Page 58
— 56 — NO. PIN NAME I/O DESCRIPTION 165 AD14 166 AD13 I/O PCI address/data/port 167 AD12 168 AD11 169 VDDQ Power IO VDD 170 VSSQ Power IO GND 171 AD10 172 AD9 I/O PCI address/data/port 173 AD8 174 C/BE0 I/O Command/byte enable 175 VDD Power Internal VDD 176 VSS Power Internal GND 177 AD7 178 AD6 179 AD5 I/O PCI address/data/port 180 AD4 181 AD3 182 AD2 183 VDDQ Power I/O VDD 184 VSSQ Power I/O GND 185 AD1 I/O PCI...
Page 59
— 57 — NO. PIN NAME I/O DESCRIPTION 219 AUDSYNC - AUD sync 220 AUDCK - AUD clock 221 VDDQ Power IO VDD 222 VSSQ Power IO GND 223 AUDATA0 - AUD data 224 AUDATA1 225 VDD Power Internal VDD 226 VSS Power Internal GND 227 AUDATA2 - AUD data 228 AUDATA3 229 Reserved - Do not connect 230 MD3/CE2A I/O Mode/PCMCIA-CE 231 MD4/CE2B I/O Mode/PCMCIA-CE 232 MD5 I Mode MD5 233 VDDQ Power IO VDD 234 VSSQ Power IO GND 235 DACK0 O DMAC0 bus...
Page 60
— 58 — 8- 8. G/A (IC14: uPD65945GJ-093-JEU) 8- 8-1. Pin Function PIN NO PIN NAME I / O DESCRIPTINPIN NO PIN NAME I / O DESCRIPTIN1 VDD VDD VDD 73 VDD VDD VDD 2 GD0 I/O ARC DATA (D0) 74 CLKOUT OCLOCK 8MHz 3 GD1 I/O ARC DATA (D1) 75 CLKIN I CLOCK 8MHz 4 GD2 I/O ARC DATA (D2) 76 GND I GND 5 GD3 I/O ARC DATA (D3) 77 CS I C hip Select 5 6 GD4 I/O ARC DATA (D4) 78 A0 I ADDRESS (A1) 7 TVDD VDD VDD 79 A1 I ADDRESS (A2) 8 TGND GND GND 80 A2 I ADDRESS (A3) 9 GD5 I/O ARC DATA (D5) 81 A3 I GND 10...