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Casio Qt6000 Service Manual

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    							— 49 —
    [ 27 ] Sound playback test
    [Function]
    This test will check the sound playback of the internal or external speaker.
    In case of one time check only, the test can be ended by the judgment (OK or NG) of the operator.
    [Operation]
    Operation :  a x n 0 9 7 ST
    a: Number of volume levels
    0 → Max volume
    * The volume can be designated in 8 levels (0 to 7). The higher the number is, the
    lower the volume is. Note that the number 8 and 9 automatically are changed to 7.
    x : 0 → Plays back the sound which was recorded by the command 98.
    1 to 9 → Plays back the specific sound.
    n : 0 → One time check
    not 0 → Continuous loop (Press [ESC] key to end the test manually.)
    * In case of one time check only, [OK] and [NG] keys below can be used.
    •[OK] key : number 1
    •[NG] key : number 9
    [LCD]
    SOUND   xn097
    SOUND   OK
    END   xn097
    SOUND   xn097
    SOUND   OK
    END   xn097
    [Print] 
    						
    							— 50 —
    [ 28 ] Sound recording test
    [Function]
    This test will check the sound recorded by the internal or external microphone.
    The test records sound for three seconds, followed by the playback of the recorded data at the
    maximum volume.
    [Operation]
    Operation : 9 8 ST
    Press [OK] or [NG] key to end the test.
    OK = 1
    NG = 9
    [LCD]
    [ 29 ] Charging test
    [Function]
    This test will turn off the charging function.
    [Operation]
    Operation : 9 9 ST
    [LCD]
    CAHRGE OFF  99
    END   99
    CAHRGE OFF  99
    END   99
    MIKE   98
    MIKE   OK
    END   98
    MIKE   98
    MIKE   OK
    END   98
    [Print]
    [Print] 
    						
    							— 51 —
    option
    iButton Probe
    +19V 12.1inch TFT LCD UNIT
    Touch PanelCFL INVERTOR unit
    Init
    CUSTOMER DISP. SYSTEMOPTIONAL REMOTE +5V SupplyOPTIONAL Hand Held Scanner
    iButton FROM
    EtherNet 1
    iButton LCDC
    CF CARD
    CF card I/FCardBusCPU
    Power Supply for CFL
    Wireless LAN CARD
    SPEAKER
    SW
    CFL
    CARDBUS card I/F         
    COM1DSUB9pin
    Battery
    main pcb
    +5V Supply
    COM2
    SIGNAL ONLY
    Disp On/OffSDRAM
    E820-1
    MCR
    I/O ctrl.
    G/A Sound
    BGA256pin
    BGA90pin
    EtherNet
    MODEM or PC
    COM4~6
    DSUB9pin x3SPEAKER OutMIC in
    Green
    DL-****
    POWER CORD
    DSUB9pin
    DSUB9pin
    AC adaptor unit type
    (LPS)
    Casio Drawer2
    HUB
    SPEAKER OU
    SIGNAL ONLY
    CAT.5 UTP cable
    DL-****
    FPCharness FFC
    Optional Printer, etc.
    MIC in
    POWER SUPPLY UNIT
    Power Status
    Casio Drawer1
    POW SW
    COM3
    Built-in MIC
    SW
    LED
    8. CIRCUIT EXPLANATION
    8-1. BLOCK DIAGRAM 
    						
    							— 52 —
    8-2. LSI BLOCK DIAGRAM
    BUZZER
    DRAWER DRIVE x 2
    COMPULSORY SW x 2
    LOAD x 2
    CLOCK x 2
    DATA x 2
    SERIAL I/FISDN(MODEM)PORT
    10M/100MBASE SH BUS
    80Mhz
    PCI BUS
    33MhzBUFFER
    (IC8, 13, 17)
    SDRAM
    256MB
    (IC12)
    FROM
    128MB
    (IC1)
    SVGA
    TFT PANEL
    (12.1inch)
    TOUCH
    PANEL
    DALLAS
    KEY DISPLAY
    ON/OFF
    SW
    DRAWER
    PORT
    X 2
    SOFT
    WARE
    KEY LCDC IC
    (IC45)
    SERIAL I/F
    3.3V    5VPCMCIA IC
    (IC36)
    PCI     CARD
    CPUSH-4
    SH-7751R
    240MHz
    (IC26)
    I/O
    CONTROLLER
    78K4
    12.5MHz
    (IC44)PC CARD
    SLOT CARD BUS
    IEEE802.11b
    IEEE802.11g BUFFER
    (IC4, 5, 6, 7)RS232C ×
     1
    (COM1)
    CF CARD
    SLOT
    Ethernet
    IC
    (IC28)EEP
    ROM
    (IC35)LAN
    PORT
    ADPCM
    IC
    (IC15)Amplifier
    IC
    (IC18)
    MICSound
    Speaker
    RTC
    (IC19) RS232C ×
     5
    (COM26)
    GA
    (IC14)
    INIT SW
    MCR (OPTION)
    (OPTION) 
    						
    							— 53 —
    8-3. RESET CIRCUIT
    The reset circuit is as follows.
    8-4. POWER SUPPLY CIRCUIT 1
    VP (DC 19V) For the drawer circuit
    VOP (DC 5.2V) For the COM2, 3 power and display ON/OFF LED
    VCC (DC 5V) For the logic circuit power
    The power supply circuit is as follows. 
    						
    							— 54 —
    8-5. POWER SUPPLY CIRCUIT 2
    VBAT (DC 3.3V) For the battery
    V1.5 (DC 1.5V) For the CPU core
    V1.8 (DC 1.8V) For the PCMCIA core
    The power supply circuit is as follows.
    8-6. DRAWER I/F CIRCUIT
    The drawer open circuit is as follows. 
    						
    							— 55 —
    8-7. CPU (IC26: SH7751)
    8-7-1. Pin Assignment
    193
    194
    195
    196
    197
    198
    199
    200
    201
    202
    203
    204
    205
    206
    207
    208
    209
    210
    211
    212
    213
    214
    215
    216
    217
    218
    219
    220
    221
    222
    223
    224
    225
    226
    227
    228
    229
    230
    231
    232
    233
    234
    235
    236
    237
    238
    239
    240
    241
    242
    243
    244
    245
    246
    247
    248
    249
    250
    251
    252
    253
    254
    255
    256 XTAL2
    EXTAL2
    VDD-RTC
    VSS-RTC
    CA
    NMI//MD6/
    TXD
    MD2/RXD2
    RXD
    TCLK
    MD8/
    SCK
    MD1/TXD2
    MD0/SCK2
    MD7/
    AUDSYNC
    AUDCK
    AUDATA0
    AUDATA1
    AUDATA2
    AUDATA3
    Reserved
    MD3/MD4/
    MD5
    DACK0
    DACK1
    DRAK0
    DRAK1
    STATUS0
    STATUS1
    /BRKACK
    TDO
    VDD-PLL2
    VSS-PLL2
    VDD-PLL1
    VSS-PLL1
    VDD-CPG
    VSS-CPG
    XTAL
    EXTAL
    128
    127
    126
    125
    124
    123
    122
    121
    120
    119
    118
    117
    116
    115
    114
    113
    112
    111
    110
    109
    108
    107
    106
    105
    104
    103
    102
    101
    100
    99
    98
    97
    96
    95
    94
    93
    92
    91
    90
    89
    88
    87
    86
    85
    84
    83
    82
    81
    80
    79
    78
    77
    76
    75
    74
    73
    72
    71
    70
    69
    68
    67
    66
    65
    //PCICLK
    IDSEL/MD9
    /MD10
    //
    A25
    A24
    A23
    A22
    A21
    A20
    A19
    A18
    D31
    D30
    D29
    D28
    D27
    D26
    D25
    D24
    D23
    D22
    D21
    D20
    D19
    D18
    D17
    D16/DQM3
    /DQM2
    A17
    A16
    A15
    A14
    A13
    A121
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    37
    38
    39
    40
    41
    42
    43
    44
    45
    46
    47
    48
    49
    50
    51
    52
    53
    54
    55
    56
    57
    58
    59
    60
    61
    62
    63
    64 TMS
    TCK
    TDI/
    D0
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    D8
    D9
    D10
    D11
    D12
    D13
    D14D15/DQM0
    /DQM1RD/
    CKIO
    ReservedReserved
    /
    /CKE
    A0
    A1
    A2
    A3
    A4
    A5
    A6
    A7
    A8
    A9
    A10A11
    192
    191
    190
    189
    188
    187
    186
    185
    184
    183
    182
    181
    180
    179
    178
    177
    176
    175
    174
    173
    172
    171
    170
    169
    168
    167
    166
    165
    164
    163
    162
    161
    160
    159
    158
    157
    156
    155
    154
    153
    152
    151
    150
    149
    148
    147
    146
    145
    144
    143
    142
    141
    140
    139
    138
    137
    136
    135
    134
    133
    132
    131
    130129AD0
    AD1
    AD2
    AD3
    AD4
    AD5
    AD6
    AD7
    C/
    AD8
    AD9
    AD10
    AD11
    AD12
    AD13
    AD14
    AD15C/PARC/
    AD16
    AD17
    AD18
    AD19
    AD20
    AD21
    AD22
    AD23C/
    AD24
    AD25
    AD26
    AD27
    AD28
    AD29
    AD30AD31
    QFP256
    (Top view)
    VDD (internal)
    VSS (internal)
    VDDQ (IO)
    VSSQ (IO)
    Note: Power must be supplied to the on-chip PLL power supply pins (VDD-PLL1, VDD-PLL2, VSS-PLL1, 
    VSS-PLL2, VDD-CPG, VSS-CPG, VDD-RTC, and VSS-RTC) regardless of whether or not the PLL 
    circuits, crystal resonator, and RTC are used. 
    						
    							— 56 —
    8-7-2. Block Diagram
    Lower 32-bit data
    64-bit data (store)
    CPG
    INTC
    SCI
    (SCIF)
    RTC
    TMU
    External (SH) bus
    interface
    DMAC
    32-bit data29-bit address
    32-bit data Address
    32-bit data
    32-bit data
    Upper 32-bit data 32-bit address (instructions)
    32-bit data (instructions)
    32-bit address (data)
    Peripheral address bus
    26-bit 
    SH bus
    address 32-bit
    PCI
    address/
    data32-bit 
    SH bus
    data
    Peripheral data bus
    UBC
    32-bit data (store) 32-bit data (load)
    CPU
    I cacheO cacheITLB UTLBCache and
    TLB
    controller
    FPU
    BSC: Bus state controller
    CPG: Clock pulse generator
    DMAC: Direct memory access controller
    FPU: Floating-point unit
    INTC: Interrupt controller
    ITLB: Instruction TLB (translation lookaside buffer)
    UTLB: Unified TLB (translation lookaside buffer)
    RTC: Realtime clock
    SCI: Serial communication interface
    SCIF: Serial communication interface with FIFO
    TMU: Timer unit
    UBC: User break controller
    PCIC:
    PCI bus controller
    32-bit data
    PCIC
    BSC
    Address
    (PCI)DMAC 
    						
    							— 57 —
    8-7-3. Pin Function
    NO. PIN NAME I/O DESCRIPTION
    1 TMS I Mode (H-UDI)
    2 TCK I Clock (H-UDI)
    3 VDDQ Power IO VDD
    4 VSSQ Power IO GND
    5 TDI I Data in (H-UDI)
    6 CSO O Chip select 0
    7 CS1 O Chip select 1
    8 CS4 O Chip select 4
    9 CS5 O Chip select 5
    10 CS6 O Chip select 6
    11 BS O Bus start
    12 WE0/REG O D7–D0 select signal
    13 WE1 O D15-D8 select signal
    14 D0 I/O Data
    15 VDDQ Power IO VDD
    16 VSSQ Power IO GND
    17 VDD Power Internal VDD
    18 VSS Power Internal GND
    19 D1
    20 D2
    21 D3
    22 D4
    23 D5
    I/O Data
    24 D6
    25 D7
    26 D8
    27 D9
    28 D10
    29 VDDQ Power IO VDD
    30 VSSQ Power IO GND
    31 D11
    32 D12
    33 D13 I/O Data
    34 D14
    35 D15
    36 CAS0/DQM0 O D7–D0 select signal
    37 CAS1/DQM1 O D15–D8 select signal
    38 RD/WR O Read/write
    39 CKIO O Clock output
    40 Reserved–Do not connect
    41 VDDQ Power IO VDD
    42 VSSQ Power IO GND
    43 Reserved–Do not connect
    44 RD/CASS/FRAME O Read/CAS/FRAME
    45 CKE O Clock output enable
    46 RAS O RAS
    47 VDD Power Internal VDD
    48 VSS Power Internal GND
    49 CS2 O Chip select 2
    50 CS3 O Chip select 3
    51 A0
    52 A1
    O Address
    53 A2
    54 A3 
    						
    							— 58 —
    NO. PIN NAME I/O DESCRIPTION
    55 VDDQ Power IO VDD
    56 VSSQ Power IO GND
    57 A4
    58 A5
    59 A6
    60 A7
    61 A8
    O Address
    62 A9
    63 A10
    64 A11
    65 A12
    66 A13
    67 VDDQ Power IO VDD
    68 VSSQ Power IO GND
    69 A14
    70 A15
    O Address
    71 A16
    72 A17
    73 CAS2/DQM2 O D23–D16 select signal
    74 CAS3/DQM3 O D31–D24 select signal
    75 D16
    76 D17
    I/O Data
    77 D18
    78 D19
    79 VDDQ Power IO VDD
    80 VSSQ Power IO GND
    81 VDD Power Internal VDD
    82 VSS Power Internal GND
    83 D20
    84 D21
    85 D22
    86 D23
    87 D24
    I/O Data
    88 D25
    89 D26
    90 D27
    91 D28
    92 D29
    93 VDDQ Power IO VDD
    94 VSSQ Power IO GND
    95 D30
    I/O Data
    96 D31
    97 VDD Power Internal VDD
    98 VSS Power Internal GND
    99 A18
    100 A19
    101 A20
    O Address
    102 A21
    103 A22
    104 A23
    105 VDDQ Power IO VDD
    106 VSSQ Power IO GND
    107 A24
    O Address
    108 A25
    109 WE2/ICIORD O D23–D16 select signal 
    						
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