Casio Qt6000 Service Manual

							Ñ 69 Ñ
8-12. DISPLAY CONTROLLER (IC45: SM712)
8-12-1. Pin Assignment
MD3MD4MD5MD7MD31MD17MD28MD20MD25MD22AD0AD4AD7AD9AD12AD14PAR
MD44
MD45
~DQM4FPFPENCKINAVDDAVSS2
MD0MD11MD9MD8MD30MD18MD27MD21MD24AD1AD5~BE0AD10AD13~BE1
MD1MD13MD10MD6~DQM2MD16MD29MD19MD26MD23AD3AD6AD8AD11AD15AD17
~DQM1MD14VDDVSSMVDDN/CMVDDVSSVSSAD2HVDDVSSHVDDVDDVSSHVDDAD19AD20
MD46
MD34
MD47LPDECRTH
SYNCRVDDIREF
BLUE
P15
MD42
MD41
MD33~DQM5FPSCLKCVDDRVSS
RED
USR1TEST0
MD38
MD39
MD43MVDDN/CFDA22N/CFPVDDN/CN/CFPVDDN/CCVSSAVSS1USR0TEST1P13
    12          3        4   5         6          7          8         9         10       11        12      13        14       15      16         17       18        19     20
    12          3        4   5           6        7         8         9        10        11        12        13      14       15      16        17       18        19      20 A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
YA
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
MD12
MD35
MD36
MD37
MD40
~CS0
MD15
MD2
~BE2
USR3
USR2
P14
P11
AD21
AD18
AD16
P9
P6
P2
PCLK
BLANK
~EXCKEN
REFCLK
CLK
AD31
AD28
AD25
IDSEL
MD63
MD49
MD60
MD52
MD57
MD55
N/C
SDCKEN
MA1
MA7
MA5
~WE
~DQM6
MD62
MD50
MD59
MD53
MD56
~ROMEN
SDCK
MA8
MA3
~CAS
BA
MD48
MD61
MD51
MD58
MD54
DSF
MA9
MA2
MA4
~RAS
~DQM0
VSS
~DQM7
MVDD
VSS
VDD
VSSA
N/C
MA0
MA6
VSS
MVDD
VSS
P10
P7
P3
P0
HREF
~INTA
~GNT
AD30
AD27
AD24
AD23
P12
P8
P5
P1
VREF
~RST
~REQ
AD29
AD26
~BE3
AD22
N/C
N/C
P4
PALCLK
VSS
HVDD
VSS
VDD
HVDD
VSS
~DQM3
~DEVSEL
MCKIN
VPVDD
~TRDY
~IRDY
~PDOWN
GREEN
~FRAME
~STOP
~CLKRUN
FDA23
FDA21
FDA20
FDA19
FDA18
FDA17
FDA16
FDA15
FDA14
FDA13
FDA12
FDA11
FDA8
FDA9
FDA10
FDA5
FDA6
FDA7
FDA2
FDA4
FDA3
FPVDDEN
VBIASEN
FDA0
FDA1CRTV
SYNCMD32
SM712
TOP VIEW
 N/C
  
 N/C 
						

							Ñ 70 Ñ
PIN NAME I/O DESCRIPTION
AD [31:0]
C/
~BE [3:0]
PAR
~FRAME
~TRDY
~IRDY
~STOP
~DEVSEL
IDSEL
CLK
~RST
~REQ
~GNT
~INTA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
I
OPCI multiplexed Address and Data Bus. A bus transaction consists of an address cycle followed by one or
more data cycles.
PCI Bus Command and Byte Enables. These signals carry the bus command during the address cycle and
byte enable during data cycles.
Parity. LynxEM+ asserts this signal to verify even parity across AD [31:0] and C/~BE [3:0].
Cycle Frame. LynxEM+ asserts this signal to indicate the beginning and duration of a bus transaction. It is
de-asserted during the final data cycle of a bus transaction.
Target Ready. A bus data cycle is completed when both ~IRDY and ~TRDY are asserted on the same
cycle.
Initiator Ready. A bus data cycle is completed when both ~IRDY and ~TRDY are asserted on the same
cycle.
Stop. LynxEM+ asserts this signal to indicate that the current target is requesting the master to stop current
transaction.
Device Select. LynxEM+ asserts this signal when it decodes its addresses as the target of the current
transaction.
ID Select. This input is used during PCI configuration read/write cycles.
PCI System Clock, 33 MHz.
PCI System Reset. LynxEM+ asserts this signal to force registers and state machines to initial default
values
PCI Bus Request (bus master mode)
PCI Bus Grant (bus master mode)
PCI Interrupt
Host Interface
Power Down Interface
~PDOWN
~CLKRUN/
ACTIVITYI
OPower down mode enable
~CLKRUN or LynxEM+ Memory and I/O activity detection depending on SCR18 [7]
0 = select ~CLKRUN
1 = select ACTIVITY
Clock Interface
REFCLK
CKIN
MCKIN/
LVDSCLK
~EXCKENI
I
I/O
I32 KHz refresh clock source for power down or PALCLK for PALTV
14.318 MHz clock (~EXCKEN = 1) or Video Clock (~EXCKEN = 0)
Memory Clock In (~EXCKEN = 0) or LVDSCLK Out (~ESCKEN = 1), LVDSCLK is a free running clock
which can be used to drive LVDS transmitter for DSTN panels.
External Clock Enable. Select external VCLK form CKIN and MCLK from MCKIN.
8-12-2. Pin Function 
						

							Ñ 71 Ñ
PIN NAME I/O DESCRIPTION
MA [9:0]
MD [63:0]
~WE
~RAS
~CAS
~CS0
~DQM
[7:0]
DSF
BA
SDCK
SDCKEN
~ROMEN
O
I/O
O
O
O
O
O
O
O
I/O
I/O
OExternal Memory Address Bus. The video memory row and column addresses are multiplexed on these
lines.
External Memory Data Bus
External Memory Write Strobe
External Memory SDRAM Row Address Select
External SGRAM Column Address Select
External SGRAM Chip Select 0, select 1st 1MB within the 2MB memory, or select 1st 2MB within the 4MB
memory
External SGRAM I/O mask [7:0]. DQM [7:0] are byte specific. DQM0 masks MD [7:0], DQM1 masks MD
[15:8],…,and DQM7 masks MD [63:58].
External SGRAM Block write
External SGRAM Bank Select. SDRAM has dual internal banks. Bank address defines to which bank the
current command is being applied.
External SGRAM clock. SDCK is driven by the memory clock. All SDRAM input signals are sampled on the
positive edge of SDCK.
External SGRAM clock enable. SDCKEN activates (HIGH) and deactivates (LOW) the SDCLK signal.
Deactivating the SDCK provides POWER-DOWN and SELF-REFRESH mode.
ROM Enable
External Display Memory Interface
Flat Panel Interface
FDATA
[23:0]
LP/FHSYNC
FP/FVSYNC
M/
DE
FPSCLK
FPEN
FPVDDEN
VBIASENO
O
O
O
O
O
O
OFlat Panel Data bit 23 to bit 0. Note: For SM712, the upper 12 bits [25:24] are multiplexed with ZV port, and
the upper 12 bits [23:11] are dedicated for flat panel data
DSTN LCD: Line Pulse
TFT LCD: LCD Horizontal Sync
DSTN LCD: Frame Pulse
TFT LCD: LCD vertical sync
M-signal or Display Enable. This signal is used to indicate the active horizontal display time.
FPR3E [7] is used to select
1 = M-signal
0 = Display Enable
Flat Panel Shift Clock. This is the pixel clock for Flat Panel Data.
Flat Panel Enable. This signal needs to become active after all panel voltages, clocks, and data are
supplied. This signal also needs to become inactive before any panel voltages or control signals are
removed. FPEN is part of the VESA FPDI-1B specification.
Flat Panel VDD Enable. This signal is used to control LCD logic power.
Flat Panel Voltage Bias Enable. This signal is used to control LCD Bias power. 
						

							Ñ 72 Ñ
PIN NAME I/O DESCRIPTION
RED
GREEN
BLUE
IREF
CRTVSYNCC
CRTHSYNC/
CSYNC
O
O
O
I
O
OAnalog Red Current Output
Analog Green Current Output
Analog Blue Current Output
Current Reference Input
CRT Vertical Sync
CRT Horizontal Sync or Composite Sync depending on CCR65 [0]
0 = CRT Horizontal Sync
1 = Composite Sync
CRT Interface
Video Port Interface
P [15:0]
PCLK
VREF
HREF
BLANK/
TVCLKI/O
I/O
I/O
I/O
I/ORGB or YUV input/ RGB digital output
Pixel Clock
VSYNC input from PC Card or video decoder
HSYNC input from PC Card or video decoder
Blank output or TVCLK output depending on CCR69 bit 7.
0 = BLANK output
1 = TVCLK output
TVCLK output is used to drive external NTSC/PAL TV encoder. To select NTSC or PAL TV, please refer to
CCR65 register
General Purpose Registers / I2C
USR3
USR2
USR1 / SDA
USR0 / SCLI/O
I/O
I/O
I/OGeneral Purpose register. It is recommended to use USR3 to control TV On/Off.
0 = TV display is OFF
1 = TV display is ON
General Purpose register. It is recommended to use USR2 to select NTSC/PAL TV settings.
0 = PALTVCLK
1 = NTSCTVCLK or REFCLK
General Purpose register. USR1/ DDC2/ I2C Data. Can be used to select different test modes.
General Purpose register. USR0/ DDC2/ I2C Clock. Can be used to select different test modes.
Tes t Mode Pi ns
TEST [1:0] I Test mode selects 
						

							Ñ 73 Ñ
PIN NAME I/O DESCRIPTION
HVDD
MVDD
FPVDD
VPVDD
CVDD
AVDD
RVDD
CVSS
AVSS1
AVSS2
RVSS
VDD
VSS
Host Interface VDD on I/O Ring, 3.3V
Display Memory Interface VDD on I/O Ring, 3.3V
Flat Panel Interface VDD on I/O Ring, 3.3V
VPVDD VPort Interface VDD on I/O Ring 3.3V
Clock (PLL) Analog Power, 3.3V
DAC Analog Power, 3.3V
RAM Filtered Palette Power, 3.3V
PLL Analog Ground
DAC Analog Ground
DAC Analog Ground
RAM Filtered Palette Ground
Digital 3.3V Core Power Supply
Digital 3.3V Internal Memory Power Supply
Digital Ground
VCC and GROUND Pins 
						

							Ñ 74 Ñ
8-13. ADPCM SPEECH LSI (IC15: MSM9841)
8-13-1. Pin Assignment
MOUT LOUTAOUTLAOUTR
MIN 
EMP
MID
FUL/DREQR
CH/DACKR
D15 to D0
WR
RD
CS
D/C
BUSYFIFO
MCU
I/FADSD
DASD
SIOCK
TEST0
TEST1
DREQLDACKLIOWIOR
VCKXTXTRESET
input side
LPF
Volume Controller
ADPCM2/ADPCM/PCM/Non-linear PCM
Synthesizer
DMA I/F
Timing Controller
External
DAC/ ADC I/F
LIN 
ADCoutput side
LPFDACDAC
SG
AV
DD
AGND
DV
DD
DGND
ADPCM2/ADPCM/PCM
Analyzer
output side
LPF
8-13-2. Block Diagram
D0
D1
D2
D3
NC
D4
D5
D6
D7
NC
D8
D9
D10
D11BUSY
D/C
CS
RD
WR
FUL/DREQR
MID
EMP
CH/DACKR
RESET
NC
DV
DD
AVDD
AOUTR 1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
XT
XT
IOR
IOW
DREQL
DACKL
DGND
TEST1
TEST0
VCK
ADSD
DASD
SIOCK 56
55
54
53
52
51
50
49
48
47
46
45
44
43 NC
D12
D13
D14
D15
NC
DGND
AGND
MIN
MOUT
LIN
LOUT
SG
AOUTL15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29 
						

							Ñ 75 Ñ
8-13-3. Pin Function
PIN NAME I/O DESCRIPTION
D15-D8
D7-D0
WR
RD
CS
D/C
BUSY
EMP
MID
FUL/
DREQR
CH/DACKR
DREQL
DACKL
IOW
IOR
ADSD
DASD
SIOCK
 I/O
I/O
I
I
I
I
O
O
O
O
I
O
I
I
I
I
O
OFor 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or
output data to and from an external memory. Otherwise, these pins are configured to be inputs only.
For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external
microcontroller and memory.
Birirectional data bus to input or output data and output status to and from an external microcontroller and
memory.
Write pulse input pin. This pin pulses ÒLÓ when command or voice data is input to D15-D0 pins.
Read pulse input pin. This pin pulses ÒLÓ when status or voice data is output to D15-D0 pins.
Accepts write pulse and read pulse when this pin is ÒLÓ. Does not accept write pulse and read pulse when
this pin is ÒHÓ.
Voice data is input or output to and from D15-D0 pins when this pin is ÒHÓ. Command is input to and status
is output from D7-D0 pins when this pin is ÒLÓ.
This pin outputs a ÒLÓ level during RECORDING, PLAYBACK or PAUSE.
ÒHÓ level indicates that there is no data in FIFO memory. Active ÒHÓ can be changed to active ÒLÓ by
command input.
ÒHÓ level indicates that more than half of the FIFO memory space is filled with data.
During playback, voice synthesis starts when MID changes to ÒHÓ level. Active ÒHÓ can be changed to active
ÒLÓ by command input. This pin outputs a synchro signal for voice data input/output when non-use of FIFO is
selected.
ÒHÓ level indicates that FIFO memory is full of data. During playback, this pin is ÒHÓ and data cannot be
written in FIFO memory. Active ÒHÓ can be changed to active ÒLÓ by command input.
When DMA transfer and stereo playback are selected, ÒHÓ level DREQR outputs a signal to request a DMA
transfer. Active ÒHÓ can be changed to active ÒLÓ by command input.
When stereo playback is selected and CH is ÒHÓ, the EMP, MID or FUL pin outputs the status of right FIFO
memory. When CH is ÒLÓ, the EMP, MID or FUL pin outputs the status of left FIFO memory. Set this pin to
ÒLÓ during recording and monophonic playback. When DMA transfer and stereo playback are selected,
DACKR is selected. In this case, input a DMA transfer acknowledge signal to DACKR. When DACKR is ÒLÓ,
the IOW signal is accepted. Active ÒLÓ can be changed to active ÒHÓ by command input.
When DMA transfer is selected, ÒHÓ level DREQL outputs a signal to request a DMA transfer.
When stereo playback is selected, ÒHÓ level DREQL outputs a signal to request a DMA transfer.
Active ÒHÓ can be changed to active ÒLÓ by command input.
Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL is ÒLÓ, IOR
and IOW signals are accepted. When stereo playback is selected, input to DACKL a DMA transfer acknowl-
edge signal for left FIFO memory. Active ÒLÓ can be changed to active ÒHÓ by command input. If DMA
transfer is not used, set this pin to ÒHÓ level.
Write pulse input pin to write external memory data to MSM9841 during DMA transfer.
If DMA transfer is not used, set this pin to ÒHÓ level.
Read pulse input pin to read data of MSM9841 during DMA transfer.
If DMA transfer is not used, set this pin to ÒHÓ level.
16-bit serial data input pin when external ADC is used. If external ADC is not used, set this pin to ÒLÓ level.
16-bit serial data output pin when external DAC is used.
Synchronizing clock for 16-bit serial data input/output when external ADC or DAC is used. 
						

							Ñ 76 Ñ
PIN NAME I/O DESCRIPTION
Oscillator connection pins. When external clock is used, input clock into XT pin and leave XT pin open.
Outputs sampling frequency selected at recording or playback.
VCK pin is used as a synchronizing signal when external ADC or DAC is used.
When this pin is ÒLÓ level input, the LSI is initialized.
Pins for testing. Set the pins to ÒLÓ.
Analog circuit signal ground output pin.
Inverting input pin for built-in OP amplifier. Noninverting input pin is connected to SG (Signal Ground)
internally.
MOUT is the output of internal OP amplifier to MIN, and LOUT is to LIN.
Left analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to
the amplifier for driving speakers.
Right analog output pin from built-in LPF. This is the output pin of playback wavefroms, and is connected to
the amplifier for driving speakers.
Digital power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and DGND pin.
Digital GND pin.
Analog power supply pin. Insert a minimum 0.1 mF bypass capacitor between this pin and AGND pin.
Analog GND pin.XT
XT
VCK
RESET
TEST0
TEST1
SG
MIN
LIN
MOUT
LOUT
AOUTL
AOUTR
DV
DD
DGND
AV
DD
AGNDI
O
O
I
I
O
I
O
O
O
Ñ
Ñ
Ñ
Ñ 
						

							Ñ 77 Ñ
8-14. ETHERNET CONTROLLER (IC28: LAN91C113)
8-14-1. Pin Assignment
8-14-2. Block Diagram   
						

							Ñ 78 Ñ
8-15. PCMCIA CONTROLLER (IC36: R5C485)
8-15-1. Pin Assignment
8-15-2. Block Diagram
GBRST#AD[31:0]IDSEL GNT# REQ#
C/BE[3:0]#
DEVSEL# FRAME#
IRDY#
TRDY#
Interrupt
&
Audio RESET
&
Clock
Socket
Power
Control Socket
Status &
Control
16-bit
Registers CardBus
Registers PCI
Config.
Registers16-bit
Interface
Master CardBus
Interface
Master &
Target CardBus
Address
Decode
&
Mapping PCI
Address
Decode
&
Mapping PCI
Interface
STOP#
PERR#
SERR#
PCICLK
PCIRST#
CLKRUN#
INTA#
IRQ3-IRQ15
RI_OUT#/PME# HWSPND#M
P
X Socket A (Func#0)
Buffer
Manage
ADDR/DATA
Buffer
Card to PCI ADDR/DATA
Buffer
PCI to CardCCLK
VCC3EN#,VCC5EN#
VPPEN0,VPPEN1 CREQ# CRST#
CCLKRUN# CGNT#
CAD[31:0]
CC/BE[3:0]#
CPAR
CFRAME#
CDEVSEL#
CIRDY#
CTRDY#
CSERR# CPERR#
CCD1,2#
CVS1,2
CSTSCHG
CINT#
CAUDIO PAR
CADR13
CADR18
CADR8
CADR17
CADR9
VCC_3V
IOWR#
CADR11
IORD#
OE#
CADR10
CE2#
CE1#
CDATA15
GND
CDATA7
CDATA14
CDATA6
CDATA13
CDATA5
CDATA12
CDATA4
CDATA11
CDATA3
INPACK#
BVD1
VCC_CORE18V
AD0
AD1
AD2
AD3
GND
AD4
AD5
AD6AD7 HWSPND#
VPPEN1
VPPEN0
VCC3EN#
VCC5EN#
VCC_3V
RI_OUT#/PME#
CCD1#
CCD2#
VS1#
VS2#
BGRST#
GND
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9/SIRQ#
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
INTA#
CLKRUN#
PCIRST#
PCICLK
GNT#
REQ#
AD31
AD30
AD29
AD28
GND
AD27
AD26
CADR19
CADR14
CADR20
WE#
CADR21
RDY/IREQ#
CADR22
GND
CADR16
CADR23
CADR15
CADR24
CADR12
CADR25
VCC_3V
CADR7
CADR6
CADR5
RESET
CADR4
WAIT#
CADR3
GND
CADR2
REG#
CADR1
BVD2
CADR0
CDATA0
CDATA8
CDATA1
CDATA9
CDATA2
CDATA10
WP/IOIS16#
VCC_CORE18VC/BE0#
AD8
AD9
VCC_PCI3V
AD10
AD11
GND
AD12
AD13
AD14
AD15
C/BE1#
PAR
SERR#
PERR#
GND
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
C/BE2#
AD16
AD17
AD18
AD19
GND
AD20
AD21
AD22
AD23
VCC_PCI3V
IDSEL
C/BE3#
AD24
AD25
1
36
72
37108
73109
144