JBL Ms 8 Service Manual
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64Mb: x32 SDRAMFeatures Synchronous DRAM MT48LC2M32B2 – 512K x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site Features • PC100 functionality Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operatio n; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto precharge, includes co ncurrent auto precharge, and auto refresh modes Self refresh mode (not available on AT devices) –64ms, 4,096-cycle refresh (15.6µs/row) (commercial, industrial) – 16ms, 4,096-cycle refresh (3.9µs/row) (automotive) LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Supports CAS latency (CL) of 1, 2, and 3 Notes: 1. Off-center parting line. 2. Available on -6 and -7. 3. Contact Micron for product availability. Options Marking – 2 Meg x 32 (512K x 32 x 4 banks) 2M32B2 1 – 86-pin TSOP II (400 mil) TG – 86-pin TSOP II (400 mil) Pb-free P – 90-ball VFBGA (8mm x 13mm) Pb-free B5 Timing (cycle time) – 5ns (200 MHz) -5 – 5.5ns (183 MHz) -55 – 6ns (166 MHz) -6 – 7ns (143 MHz) -7 :G Operating temperature range – Commercial (0° to +70°C) None – Industrial (–40°C to +85°C) IT 2 –Automotive (–40°C to +105°C) AT3 Notes: 1. FBGA Device Decode: http:// www.micron.com/support/FBGA/FBGA.asp Part Number Example: MT48LC2M32B2P-7:G Table 1: Address Table 2 Meg x 32 Configuration 512K x 32 x 4 banks Refresh count 4K Row addressing 2K (A0–A10) Bank addressing 4 (BA0, BA1) Column addressing 256 (A0–A7) Table 2: Key Timing Parameters CL = CAS (READ) latency Speed GradeClock Frequency Access Time Setup TimeHold TimeCL = 3 -5 200 MHz 4.5ns 1.5ns 1ns -55 183 MHz 5ns 1.5ns 1ns -6 166 MHz 5.5ns 1.5ns 1ns -7 143 MHz 5.5ns 2ns 1ns Table 3: 64Mb (x32) SDRAM Part Number Part NumberArchitecture MT48LC2M32B2TG 2 Meg x 32 MT48LC2M32B2P 2 Meg x 32 MT48LC2M32B2B5 12 Meg x 32 MS-8 37
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice. 64MSDRAMx32_2.fm - Rev. J 12/08 EN6©2001 Micron Technology, Inc. All rights reserved. 64Mb: x32 SDRAM Functional Block Diagram Functional Block Diagram Figure 1: 2 Meg x 32 SDRAM 11 RAS# CAS# CLK CS# WE# CKE 8 A0–A10, BA0, BA1 DQM0– DQM3 13 256 (x32) 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS COLUMN DECODER BANK0 MEMORY ARRAY (2,048 x 256 x 32) BANK 0 ROW- ADDRESS LATCH & DECODER 2048 SENSE AMPLIFIERS BANK CONTROL LOGIC DQ0– DQ31 32 32 DATA INPUT REGISTER DATA OUTPUT REGISTER 32 BANK 1BANK 0 BANK 2 BANK 3 11 8 2 4 4 2 REFRESH COUNTER 11 11 MODE REGISTER CONTROL LOGIC COMMAND DECODE ROW- ADDRESS MUX ADDRESS REGISTER COLUMN- ADDRESS COUNTER/ LATCH MS-8 38
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice. 64MSDRAMx32_2.fm - Rev. J 12/08 EN7©2001 Micron Technology, Inc. All rights reserved. 64Mb: x32 SDRAM Pin/Ball Assignments and Descriptions Pin/Ball Assignments and Descriptions Figure 2: 86-Pin TSOP (Top View) Note: The # symbol indicate s signal is active LOW. VDDDQ0 VDDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 NC V DDDQM0 WE# CAS# RAS# CS#NC BA0 BA1 A10 A0 A1 A2 DQM2 V DDNC DQ16 V SSQ DQ17 DQ18 V DDQ DQ19 DQ20 V SSQ DQ21 DQ22 V DDQ DQ23 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44VSSDQ15 VSSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SSDQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 V SSNC DQ31 V DDQ DQ30 DQ29 V SSQ DQ28 DQ27 V DDQ DQ26 DQ25 V SSQ DQ24 V SS MS-8 39