JBL Ms 8 Service Manual

							
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN8©2001 Micron Technology, Inc. All rights reserved.
 64Mb: x32 SDRAM
Pin/Ball Assignments and Descriptions
Figure 3:   90-Ball VFBGA (Top View, Ball Down)
1234 6789 5
DQ26
DQ28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1 V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13 DQ24
V
DDQ
DQ27
DQ29
DQ31
DQM3 A5
A8
CKE NC
DQ8
DQ10
DQ12 V
DDQ
DQ15 V
SS
VSSQ
DQ25
DQ30 NCA3
A6
NC A9
NC
V
SS
DQ9
DQ14 V
SSQ
V
SS
VDD
VDDQ
DQ22
DQ17 NCA2
A10 NC
BA0
CAS# V
DD
DQ6
DQ1
V
DDQ
V
DD
DQ21
DQ19 V
DDQ
V
DDQ
V
SSQ
V
DD
A1
NC
RAS#
DQM0 V
SSQ
V
DDQ
V
DDQ
DQ4
DQ2
DQ23
V
SSQ
DQ20
DQ18
DQ16
DQM2 A0
BA1 CS#
WE# DQ7
DQ5
DQ3
V
SSQ
DQ0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
 
 MS-8                      
 
 
 
40  
						

							
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN9©2001 Micron Technology, Inc. All rights reserved.
 64Mb: x32 SDRAM
Pin/Ball Assignments and Descriptions
 
Table 4:  Pin/Ba ll Descriptions
86-Pin TSOP 
Numbers90-Ball VFBGA  NumbersSymbolTy p eDescription
68 J1 CLK Input Clock: CLK is driven by the system  clock. All SDRAM input signals 
are sampled on the positive edge  of CLK. CLK also increments 
the internal burst counter and co ntrols the output registers. 
67 J2 CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the 
CLK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all banks idle), ACTIVE 
power-down (row active in  any bank), or CLOCK SUSPEND 
operation (burst/access in progre ss). CKE is synchronous except 
after the device enters power-down and self refresh modes, 
where CKE becomes asynchronous  until after exiting the same 
mode. The input buffers, including CLK, are disabled during 
power-down and self refresh  modes, providing low standby 
power. CKE may be tied HIGH.
20 J8 CS# Input Chip select: CS# enables (registered LOW) and disables 
(registered HIGH) the command decoder. All commands are 
masked when CS# is register ed HIGH, but READ/WRITE bursts 
already in progress will conti nue and DQM operation will retain 
its DQ mask capability while  CS# is HIGH. CS# provides for 
external bank selection on syste ms with multiple banks. CS# is 
considered part of the command code.
17, 18, 19 K8, K7, J9 WE#,  CAS#, RAS#  Input
Command inputs : WE#, CAS#, and RAS# (along with CS#) 
define the command being entered.
16, 71, 28, 59 K9, K1, F8, F2 DQM0– DQM3Input
Input/output mask : DQM is sampled HIGH and is an input 
mask signal for write accesses an d an output enable signal for 
read accesses. Input data is ma sked during a WRITE cycle. The 
output buffers are placed in a  High-Z state (2-clock latency) 
during a READ cycle. DQM0 co rresponds to DQ0–DQ7; DQM1 
corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23; 
and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are 
considered same state when referenced as DQM.
22, 23 J7, H8 BA0, BA1 Input Bank address input(s): BA0 and BA1 define to which bank the 
ACTIVE, READ, WRITE, or PRECHARGE command is being 
applied. 
25–27, 60–66,  24 G8, G9, F7, F3, 
G1, G2, G3, H1, 
H2, J3, G7 A0–A10
Input
Address inputs : A0–A10 are sampled during the ACTIVE 
command (row-address A0–A10) and READ/WRITE command 
(column-address A0–A7 with A10 defining auto precharge) to 
select one location out of the  memory array in the respective 
bank. A10 is sampled during a PRECHARGE command to 
determine whether all banks are  to be precharged (A10 HIGH) 
or bank selected by BA0, BA1 (LOW). The address inputs also 
provide the op-code during a LOAD MODE REGISTER command. 
2, 4, 5, 7, 8, 10,  11, 13, 74, 76, 
77, 79, 80, 82, 
83, 85, 31, 33, 
34, 36, 37, 39, 
40, 42, 45, 47, 
48, 50, 51, 53,  54, 56  R8, N7, R9, N8, 
P9, M8, M7, L8, 
L2, M3, M2, P1,  N2, R1, N3, R2, E8, D7, D8, B9, 
C8, A9, C7, A8, 
A2, C3, A1, C2,  B1, D2, D3, E2 DQ0–
DQ31
Input/
Output Data I/Os
: Data bus.
 
 MS-8                      
 
 
 
41  
						

							
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN10©2001 Micron Technology, Inc. All rights reserved.
 64Mb: x32 SDRAM
Functional Description
Functional Description
In general, this 64Mb SDRAM (512K x 32 x 4 banks) is a 4-bank DRAM that operates at 
3.3V and includes a synchronous interface (all signals are registered on the positive edge 
of the clock signal, CLK). Each of the 16,777,21 6-bit banks is organized as 2,048 rows by 
256 columns by 32 bits.
Read and write accesses to the SDRAM are bu rst oriented; accesses start at a selected 
location and continue for a programmed  number of locations in a programmed 
sequence. Accesses begin with the registration  of an ACTIVE command, which is then 
followed by a READ or WRITE command. The address bits registered coincident with the 
ACTIVE command are used to select the ba nk and row to be accessed (BA0 and BA1 
select the bank, A0–A10 select the row). The  address bits (A0–A7) registered coincident 
with the READ or WRITE command are used to  select the starting column location for 
the burst access. 
Prior to normal operation, the SDRAM must be initialized. The following sections 
provide detailed information covering device initialization, register definition, 
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initiali zed in a predefined manner. Operational 
procedures other than those specified may resu lt in undefined operation. After power is 
applied to V
DD and VDDQ (simultaneously) and the cloc k is stable (stable clock is 
defined as a signal cycling wi thin timing constraints specified for the clock pin), the 
SDRAM requires a 100µs delay prior to is suing any command other than a COMMAND 
INHIBIT or NOP. Starting at some point during  this 100µs period, and continuing at least 
through the end of this period, COMMAN D INHIBIT or NOP commands must be 
applied.
When the 100µs delay has been satisfied wi th at least one COMMAND INHIBIT or NOP 
command having been applied, a PRECHARGE command should be applied. All banks 
must then be precharged, thereby placing the device in the all banks idle state.
3, 9, 35, 41, 49, 
55, 75, 81 B2, B7, C9, D9, 
E1, L1, M9, N9, 
P2, P7 VDDQ Supply 
DQ power supply : Isolated on the die for improved noise 
immunity.
6, 12, 32, 38, 
46, 52, 78, 84 B8, B3, C1, D1, 
E9, L9, M1, N1,  P3, P8 V
SSQ Supply 
DQ ground: Provide isolated ground to DQs for improved noise 
immunity.
1, 15, 29, 43 A7, F9, L7, R7 V
DDSupply Power supply : +3.3V ±0.3V. (See note 27 on page 50.)
44, 58, 72, 86 A3, F1, L3, R3 V
SSSupply Ground.
14, 21, 30, 57,  69, 70, 73 E3, E7, H3, H7, 
K2, K3, H9 NC –
No connect: These pins/balls should be  left unconnected. Pin 70 
is reserved for SSTL reference volt age supply. H7 is a no connect 
for this part but may be used as A12 in future designs. H9 is used 
as A11 in 128Mb, 256Mb, and 512Mb x32 FBGAs. PCB designs 
that accommodate different densities must account for A11 with 
stuffing options.
Table 4:  Pin/Ball De scriptions (continued)
86-Pin TSOP 
Numbers90-Ball VFBGA  NumbersSymbolTy p eDescription
 
 MS-8                      
 
 
 
42  
						

							
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN11©2001 Micron Technology, Inc. All rights reserved.
 64Mb: x32 SDRAM
Functional Description
When in the idle state, at least two AUTO REFRESH cycles must be performed. After the 
AUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up  in an unknown state, it must be loaded 
prior to applying any operational command. If desired, the two AUTO REFRESH 
commands can be issued after the LOAD MODE REGISTER command.
The recommended power-up sequence for SDRAMs:
1. Simultaneously apply power to V
DD and VDDQ.
2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL- compatible.
3. Provide stable CLOCK signal. Stable clock is  defined as a signal cycling within timing 
constraints specified for the clock pin. 
4. Wait at least 100µs prior to issuing  any command other than a COMMAND INHIBIT 
or NOP.
5. Starting at some point during this 100µs  period, bring CKE HIGH. Continuing at least 
through the end of this period, 1 or  more COMMAND INHIBIT or NOP commands 
must be applied.
6. Perform a PRECHARGE ALL command.
7. Wait at least 
tRP time; during this time,0 NOPs  or DESELECT commands must be 
given. All banks will complete their precharge, thereby placing the device in the all 
banks idle state.
8. Issue an AUTO REFRESH command.
9. Wait at least 
tRFC time, during which only NOPs  or COMMAND INHIBIT commands 
are allowed.
10. Issue an AUTO REFRESH command.
11. Wait at least 
tRFC time, during which only NOPs  or COMMAND INHIBIT commands 
are allowed.
12. The SDRAM is now ready for mode register programming. Because the mode register  will power up in an unknown state, it should be loaded with desired bit values prior to 
applying any operational command. Using the LMR command, program the mode 
register. The mode register is progra mmed via the MODE REGISTER SET command 
with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again 
or the device loses power. Not programming  the mode register upon initialization will 
result in default settings which may not be  desired. Outputs are guaranteed High-Z 
after the LMR command is issued. Outputs sh ould be High-Z already before the LMR 
command is issued.
13. Wait at least 
tMRD time, during which only NOP or DESELECT commands are 
allowed.
At this point the DRAM is ready for any valid command.
Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence. 
After steps 9 and 10 are complete, repeat  them until the desired number of AUTO 
REFRESH + 
tRFC loops is achieved.
 
 MS-8                      
 
 
 
43  
						

							
AUREUS TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 772511443

Aureus  High-Performance 32-/64-Bit
Audio Digital Signal Processors (DSPs)

DA610-250 MHz, 2000 MIPS/1500 MFLOPS

DA601-225 MHz, 1800 MIPS/1350 MFLOPS

Single DSP Solutions for Multichannel
Audio Applications: A/V and DVD
Receivers, Multi-Zone Receivers, High
Speed Encoder, Simultaneous
Encode/Decode, Surround Headphone,
Speaker Virtualization, Room Correction

DA601 and DA610 Compatibility Provides a
Scalable Audio Solution Based on a Single
DSP Instruction Set Architecture

Certified Algorithms:
  Dolby Digital Decoder, Dolby Digital EX, Dolby Pro Logic IIx, Dolby Pro Logic II
  DTS 5.1, DTSES 6.1, DTS Neo:6,  DTS 96/24
  MPEG2 AAC
  THX Ultra 2

Supports Other Algorithms Including:
  MP3 CODEC
  WMA CODEC
  SRS Circle Surround II
  Waves’ MaxxBass Technology

Highly Optimized C/C++ Compiler

VelociTI  Advanced Very Long Instruction
Word (VLIW) C67x  DSP Core
  Native Instruction Set Support for:   32-/64-Bit IEEE 754 Floating-Point
  32/40/64 & Packed-16-Bit Fixed-Point
  Eight Independent Functional Units:   Two ALUs (Fixed-Point)
  Four ALUs (Floating- and Fixed-Point)
  Two Multipliers (Floating-/Fixed-Point)
  Fast Time to Market with RISCLike ISA

Low-Cost, Two-Level Memory System
  4K-Byte L1P Plus 4K-Byte L1D Cache
  256K-Byte L2 Cache/RAM (DA610)
  128K-Byte L2 Cache/RAM (DA601)
  512K-Byte L2 ROM (DA610/DA601)

32-Bit External Memory Interface (EMIF)
Seamlessly Expands Memory Space by
Supporting: SRAM, SDRAM, FLASH,
EPROM, and SBSRAM.
Four External Address Spaces

16-Bit Host-Port Interface (HPI) Enables
High-Speed Encode/Decode Applications

Enhanced Direct-Memory-Access (EDMA)
Controller With 16 Independent Channels

Two Multichannel Audio Serial Ports
(McASPs)
  Independent Dual Zone Audio on a Single DSP
  16 Data Pins (32 Channel Stereo)
  Flexible Clocking
  TDM Streams 2-32 Channels per Pin
  Data Formatting Unit Supports Wide Variety of I2S and Similar Formats
  Integrated Digital Audio Interface Transmitter (DIT) With Enhanced 
Channel Status/User Data
  Extensive Error Checking and Recovery

Two Inter-Integrated Circuit Bus (I2C Bus )
Multi-Master and Slave Interfaces

Two Multichannel Buffered Serial Ports
(McBSPs) Supporting:
  Serial-Peripheral-Interface (SPI)
  High-Speed TDM Interface

Two 32-Bit General-Purpose Timers

Two General-Purpose Input/Output
Modules

On-Chip Oscillator and PLL Module

IEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible

Package Options:
  208-Pin PowerPAD  PQFP (PYP Suffix)
  272-Pin Ball Grid Array (GDP Suffix)

0.13-µ m Copper Metal CMOS Process

3.3-V I/Os, 1.2-V Internal
          
Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of
Copyright  2005, Texas Instruments Incorporated
Aureus, VelociTI, C67x, and PowerPAD are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
 
 MS-8                       
 
 
44  
						

							
AUREUS TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS002I   SEPTEMBER 2001  REVISED OCTOBER 2005
3POST OFFICE BOX 1443 • HOUSTON, TEXAS 772511443
GDP BGA package (bottom view) 
VSSVSS
CLKIN CVDD
VSSVSS
VSSCVDDDVDDCE2EA4 DVDDED17 EA6DVDDEA13VSSEA15EA19 CE1CVDDVSS
GP0[5]
(EXT_INT5)/ AMUTEIN0 GP0[4]
(EXT_INT4)/ AMUTEIN1
CVDDED16 BE3CE3EA3 EA5 EA8 EA10
EMU4 OSCOUT NMIEA12 DVDD
HD9/
GP0[9] HD6/
AHCLKR1CVDDHD4/
GP0[0] HD3/
AMUTE1
ED20 ED19
CV
DDCLK
MODE0 PLLHV ARE
/
SDCAS/
SSADSDVDD
HD14/
GP0[14] HD12/
GP0[12]
CVDDDVDD
VSSCVDDDVDDRSV
RSV TRSTTMSEMU1
DVDD
AOE/
SDRAS/
SSOEVSS
DVDD
EA11
HD15/
GP0[15] HD10/
GP0[10]
V
SSHD8/
GP0[8] HD5/
AHCLKX1 CVDDVSS
VSSVSS
ED18 BE2
VSSVSS
VSSVSSVSSVSS
VSSVSSVSSVSS
VSS
VSSVSS
VSS
VSSVSS
VSSVSS
1 2 3 4 5 6 7 8 9 1011121314151617181920
Y
W V
U
T
R P
N
M L
K J
H
G F
E
D
C B
A V
SS
AWE/
SDWE/
SSWE
RSV TCK TDI TDO CVDDCVDDVSSRESETVSSHD13/
GP0[13] HD11/
GP0[11] DVDDHD7/
GP0[3]
OSCVDD
DVDDEA7 EA9
VSSEA14 EA16 EA18 DVDDEA20
EA2
ARDY ECLKOUT ECLKINCLKOUT2/
GP0[2]
EMU3 OSCV
SSEMU5 BE0
DVDDCE0CVDDEA17
V
SSVSSVSS
DVDDEMU2 V
SSDVDDCVDDDVDDVSSVSSCVDDCVDDDVDDVSSCVDDCVDDDVDDVSSEA21 BE1VSS
VSSCVDDCVDDRSV VSSEMU0 CLKOUT3 CVDDOSCIN VSSCVDDCVDDDVDDVSSHD2/
AFSX1 DVDDHD1/
AXR0[8]/
AXR1[7]
ED22 ED21 ED23GP0[6]
(EXT_INT6)
CLKS1/ SCL1 VSSGP0[7]
(EXT_INT7)VSSVSS
ED13/
GP1[13] ED15/
GP1[15] ED14/
GP1[14]
VSSVSS
HDS1/
AXR0[9]/
AXR1[6]
HAS/
ACLKX1 HD0/
AXR0[11]/
AXR1[4]
ED24 ED25 DV
DD
CVDDDVDDED27 ED26
CV
DDHDS2/
AXR0[10]/
AXR1[5] VSSHCS/
AXR0[13]/
AXR1[2]
TOUT1/
AXR0[4]/
AXR1[11] TINP1/
AHCLKX0 DVDDCVDD
CVDDDVDDED11/
GP1[11] ED12/
GP1[12]
TOUT0/
AXR0[2]/
AXR1[13] TINP0/
AXR0[3]/
AXR1[12] CLKX0/
ACLKX0 V
SS
VSSED9/
GP1[9] VSSED10/
GP1[10]
VSSED28 ED29 ED30
V
SSHCNTL0/
AXR0[12]/
AXR1[3] HCNTL1/
AXR0[14]/
AXR1[1]HR/W/
AXR0[15]/
AXR1[0]
FSX0/
AFSX0 SDA0
V
SSVSSED6/
GP1[6] ED7/
GP1[7] ED8/
GP1[8]
CLKR0/
ACLKR0 V
SSDX0/
AXR0[1]/
AXR1[14]
SCL0
ED31
VSSDVDDHRDY/
ACLKR1 HHWIL/
AFSR1
FSR0/
AFSR0
CLKR1/
AXR0[6]/
AXR1[9] DR1/
SDA1 V
SSVSSDVDDED4/
GP1[4] ED5/
GP1[5]
DR0/
AXR0[0]/
AXR1[15] DV
DDVSS
FSR1/
AXR0[7]/
AXR1[8]
HOLD
HOLDABUS
REQ HINT/
GP0[1]
FSX1
DX1/
AXR0[5]/
AXR1[10] CLKX1/
AMUTE0 CV
DDCVDDED2/
GP1[2] ED3/
GP1[3] CVDD
CVDDVSSCLKS0/
AHCLKR0 CVDDCVDDED0/
GP1[0] ED1/
GP1[1] VSS
Shading denotes the GDP package pin functions that drop out on the PYP package.\
 
 MS-8                       
 
 
45  
						

							
AUREUS TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS002I   SEPTEMBER 2001  REVISED OCTOBER 2005
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 772511443
PYP PowerPAD QFP package (top view) 
HD5/AHCLKX1
HD8/GP0[8]
HD6/AHCLKR1
HD7/GP0[3]
HD9/GP0[9]
HD10/GP0[10]
HD11/GP0[11]
HD12/GP0[12]
HD13/GP0[13]
HD14/GP0[14]
HD15/GP0[15] NMI
OSCIN
OSCOUT
EMU1
EMU0TDO
TDI
TMS TCK
RSV2
RSV0
RSV1
CLKIN
CLKMODE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51 HD4/GP0[0]
HD2/AFSX1
HD3/AMUTE1
HD1/AXR0[8]/AXR1[7]
HD0/AXR0[11]/AXR1[4]
HCNTL0/AXR0[12]/AXR1[3]
HCNTL1/AXR0[14]/AXR1[1]
HR/
HHWIL/AFSR1
BUSREQ
HINT
ED0/GP1[0]
ED1/GP1[1]
ED2/GP1[2]
ED3/GP1[3]
ED5/GP1[5]
ED4/GP1[4]
ED8/GP1[8]
ED7/GP1[7]
ED6/GP1[6]
ED10/GP1[10]
ED9/GP1[9]
ED12/GP1[12]
ED11/GP1[11]
ED14/GP1[14]
ED15/GP1[15]
ED13/GP1[13]
EA21
EA20
EA19
EA17
EA18
EA15
EA12
EA16
EA13
EA14
EA11
CLKOUT2/GP0[2] ECLKIN
ECLKOUT
EA10
EA9
EA7 EA8
EA6
EA5
EA4 EA3
EA2
ARDY
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
GP0[4](EXT_INT4)/AMUTEIN1
GP0[6](EXT_INT6)
GP0[5](EXT_INT5)/AMUTEIN0 DD
GP0[7](EXT_INT7)
CLKS1/SCL1
TINP1/AHCLKX0
TOUT1/AXR0[4]/AXR1[11]
CLKX0/ACLKX0
TINP0/AXR0[3]/AXR1[12]
TOUT0/AXR0[2]/AXR1[13] CLKR0/ACLKR0
DX0/AXR0[1]/AXR1[14]
FSX0/AFSX0
FSR0/AFSR0
DR0/AXR0[0]/AXR1[15] CLKS0/AHCLKR0
FSX1
DX1/AXR0[5]/AXR1[10]
CLKX1/AMUTE0
CLKR1/AXR0[6]/AXR1[9] DR1/SDA1
FSR1/AXR0[7]/AXR1[8]
SCL0
SDA0 156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
11 9
11 8
11 7
11 6
11 5
11 4
11 3
11 2111
11 0
109
108
107
106
105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
TRST
RESET
/GP0[1]W/AXR0[15]/AXR1[0]HAS /ACLKX1HCS /AXR0[13]/AXR1[2]HDS1/AXR0[9]/AXR1[6]HDS2/AXR0[10]/AXR1[5]HRDY/ACLKR1
CE3
CE2
CE1CE0
BE1BE0HOLDAHOLD
ARE/SDCAS/SSADS
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
DVDD
DVDD
OSCVDD
PLLHV
CLKOUT3
DV
DVDD
DD
DV
DD
DV
DD
DV DD
DV
DD
DV
DVDD
DVDD
DVDD
DVDD
DD
CV
CVDD
DVDD
DVDD
CVDD
CVDD
CVDD
CVDD
DD
CV DD
CV
DD
CV
CVDD
CVDD
DD
CV
CVDD
DD
CV
DD
CV
DD
CV
DD
CV
CVDD
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PYP 208-PIN PowerPAD
 PLASTIC QUAD FLATPACK (PQFP)
( TOP VIEW )
VSS
CVDD
 
 MS-8                       
 
 
46  
						

							
AUREUS TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS002I   SEPTEMBER 2001  REVISED OCTOBER 2005
8POST OFFICE BOX 1443 • HOUSTON, TEXAS 772511443
functional block and CPU (DSP core) diagram 
Test
C67x
 CPU
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-DownLogic
.L1
†.S1†.M1†.D1 .D2 .M2†.S2†.L2†
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control Logic
L1D Cache 2-Way Set
Associative
4K Bytes Total In-Circuit
Emulation
InterruptControl
DA610 and DA601 Digital Signal Processors
†In addition to fixed-point instructions, these functional units execute \
floating-point instructions.
Enhanced DMA
Controller
(16 channel) L2 Cache/
Memory
4 Banks
64K Bytes Total
(4-Way)
Clock Generator,
Oscillator, and PLL 
x4 through x25 Multipliers  /1 through /32 Dividers
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM  512K
Bytes Total
EMIF32
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
GP1
GP0
HPI16
Pin Multiplexing
McBSPs interface to:
SPI Control Port
High-Speed TDM Codecs
AC97 Codecs
Serial EEPROM
EMIF32 interfaces to: 
SDRAM
SBSRAM
SRAM, 
ROM/Flash, and 
I/O devices McASPs interface to:
I2S Multichannel ADC, DAC, Codec, DIR
DIT: Multiple Outputs
 
 MS-8                       
 
 
47  
						

							
Full Speed USB Flash MCU Family
C8051F340/1/2/3/4/5/6/7/8/9/A/B
Analog Peripherals
-10-Bit ADC (C8051F340/1/2/3/4/5/6/7 only)•Up to 200 ksps•Built-in analog multiplexer with single-ended and differential mode•VREF from external pin, internal reference, or VDD•Built-in temperature sensor•External conversion start input option-Two comparators
-Internal voltage reference (C8051F340/1/2/3/4/5/6/7 
only)
-Brown-out detector and POR CircuitryUSB Function Controller
-USB specification 2.0 compliant
-Full speed (12 Mbps) or low speed (1.5 Mbps) operation
-Integrated clock recovery; no external crystal required for 
full speed or low speed
-Supports eight flexible endpoints
-1 kB USB buffer memory
-Integrated transceiver; no external resistors required
On-Chip Debug
-On-chip debug circuitry facilitates full speed, non-intru-
sive in-system debug (No emulator required)
-Provides breakpoints, single stepping, 
inspect/modify memory and registers
-Superior performance to emulation systems using 
ICE-chips, target pods, and sockets
Voltage Supply Input: 2.7 to 5.25 V
-Voltages from 3.6 to 5.25 V supported using On-Chip 
Voltage Regulator
HIgh Speed 8051 µC Core
-Pipelined instruction architecture; executes 70% of 
Instructions in 1 or 2
 system clocks
-48 MIPS and 25 MIPS versions available.
-Expanded interrupt handler
Memory
-4352 or 2304 Bytes RAM
-64 or 32 kB Flash; In-system programmable in 512-byte 
sectors
Digital Peripherals
-40/25 Port I/O; All 5 V tolerant with high sink current
-Hardware enhanced SPI™, SMBus™, and one or two 
enhanced UART serial ports
-Four general purpose 16-bit counter/timers
-16-bit programmable counter array (PCA) with five cap-
ture/compare modules
-External Memory Interface (EMIF)
Clock Sources
-Internal Oscillator: ±0.25% accuracy with clock recovery 
enabled. Supports all USB and UART modes
-External Oscillator: Crystal, RC, C, or clock (1 or 2 Pin 
modes)
-Low Frequency (80 kHz) Internal Oscillator
-Can switch between cl ock sources on-the-fly
Packages
-48-pin TQFP (C8051F340/1/4/5/8)
-32-pin LQFP (C8051F342/3/6/7/9/A/B)
-5x5 mm 32-pin QFN (C8051F342/3/6/7/9/A/B)
Temperature Range: –40 to +85 °C
ANALOG 
PERIPHERALS
10-bit
200 ksps ADC
64/32 kB 
ISP FLASH4/2 kB RAM
POR DEBUG 
CIRCUITRYFLEXIBLE 
INTERRUPTS
8051 CPU
(48/25 MIPS)
DIGITAL I/O
 PRECISION INTERNAL  OSCILLATORS
HIGH-SPEED CONTROLLER CORE
A
M
UX
CROSSBAR
+
-
 WDT
+
-
USB Controller / 
Transceiver
Port 0
Port 1
Port 2
Port 3
TEMP 
SENSORVREGVREFPort 4Ext. Memory I/F48 Pin Only
UART0
SMBus
PCA
4 Timers
SPI
UART1*
C8051F340/1/2/34/5/6/7/A/B Only * C8051F340/1/4/5/8/A/B Only
 
 MS-8                      
 
 
 
48  
						

							
Rev. 1.317
C8051F340/1/2/3/4/5/6/7/8/9/A/B
1. System Overview
C8051F340/1/2/3/4/5/6/7/8/9/A/B devices are fully  integrated mixed-signal S ystem-on-a-Chip MCUs. High-
lighted features are listed below. Refer to Ta b l e 1.1 for specific product feature selection.
• High-speed pipelined 8051-compatible microcontroller core (up to 48 MIPS)
• In-system, full-speed, non-intrusive debug interface (on-chip)
• Universal Serial Bus (USB) Function Controller wit h eight flexible endpoint pipes, integrated trans-
ceiver, and 1 kB FIFO RAM
• Supply Voltage Regulator
• True 10-bit 200 ksps differential / single-ended 
ADC with analog multiplexer
• On-chip Voltage Reference and Temperature Sensor
• On-chip Voltage Comparators (2)
• Precision internal calibrated 12 MHz internal oscillator and 4x clock multiplier
• Internal low-frequency oscillato
r for additional power savings
• Up to 64 kB of on-chip Flash memory
• Up to 4352 Bytes of on-chip RAM (256 + 4 kB)
• External Memory Interface (EMIF) available on 48-pin versions.
• SMBus/I2C, up to 2 UARTs, and Enhanced SPI 
serial interfaces implemented in hardware
• Four general-purpose 16-bit timers
• Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer 
func tion
• On-chip Power-On Reset, VDD Monitor, and Missing Clock Detector
• Up to 40 Port I/O (5 V tolerant)
With on-chip Powe r-On Reset, VDD monitor, Voltage Regulator, Watc
hdog Timer, and clock oscillator, 
C8051F340/1/2/3/4/5/6/7 /8/9/A/B devices are truly stand-alone System-on-a-Chip solutions. The Flash 
memory can be reprogrammed in-circuit, providing n on-volatile data storage, and also allowing field 
upgrades of the 8051 firmware. User software has complete control of all peripherals, and may individually 
shut down any or all peripherals for power savings.
The on-chip Silicon Labs 2- Wire (C2) Development Interface allo
ws non-intrusive (uses no on-chip 
resources), full speed, in-circuit debugging using the  production MCU installed in the final application. This 
debug logic supports inspection and modification of  memory and registers, setting breakpoints, single 
stepping, run and halt commands. All analog and digita l peripherals are fully functional while debugging 
using C2. The two C2 interface pins  can be shared with user functions, allowing in-system debugging with
-
out occupying package pins.
Each device is specified for 2.7–5.25 V operation over the industrial temperature range (–40 to +85 °C). 
F or voltages above 3.6
 V, the on-chip Voltage Regulator must be used.  A minimum of 3.0 V is required for 
USB com munication. The Port I/O and 
RST pins are tolerant of input signals up to 5 V. C8051F340/1/2/3/
4/5/6/7/8/9/A/B devices are available in 48-pin TQFP, 32-pin LQFP, or 32-pin QFN packages. See 
Ta b l e 1.1, “Product Selection Guide,” on page 18 for feature and package choices.
 
 MS-8                      
 
 
 
49