Motorola Cp150 Cp200 6880309n62 C Manual

							6880309N62-CJune, 2005
VHF Schematic Diagrams, Overlays, and Parts Lists: Speaker and Microphone Schematic 7-3
7.1.2 Six Layer Circuit Board
Figure 7-1.  Six-Layer Circuit Board: Copper Steps in Layer Sequence 
7.2 Speaker and Microphone Schematic
Figure 7-2.  Speaker and Microphone Schematic
7.2.1 Speaker and Microphone Parts List
Reference
DesignatorMotorola Part 
No.Description
MK15080258E16Microphone, electret
SP1 5005679X04 Speaker assembly with 
connector
LAYER 1 (L1)
LAYER 2 (L2)
LAYER 3 (L3)
LAYER 4 (L4)
LAYER 5 (L5)
LAYER 6 (L6)
INNER LAYERS SIDE 1
SIDE 2
MK1
SP11
2
1
2MATES WITH J470 ON
RADIO BOARD
MATES WITH J491 ON
RADIO BOARD 
						

							
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7-4VHF Schematic Diagrams, Overlays, and Parts Lists:  Speaker and Microphone Schematic 
						

							Chapter 8 403-440 MHz UHF Theory Of Operation
8.1 Introduction
This chapter provides a detailed theory of operation for the radio components. Schematic diagrams 
for the circuits described in the following paragraphs are located in Chapter 12 of this manual.
8.2 UHF Receiver
The UHF receiver covers the range of 403-440 MHz and provides switchable IF bandwidth for use 
with 20/25/30 kHz or 12.5 kHz channel spacing systems. The receiver is divided into two major 
blocks, as shown in Figure 8-1.
• Front End 
• Back End 
Figure 8-1.  UHF Receiver Block Diagram
8.2.1 Receiver Front End
Incoming RF signals from the antenna are first routed through the harmonic filter and antenna switch, 
part of the transmitter circuitry, before being applied to the receiver front end. The receiver front end 
consists of a preselector filter, RF amplifier, an interstage filter, and a double-balanced first mixer.
The preselector filter is a fixed-tuned 3-pole Butterworth design using discrete elements (L1-L3, C1-
C10, C12 and C523) in a shunt-resonator configuration. It has a 3 dB bandwidth of 68 MHz centered 
at 421 MHz, an insertion loss of 2.2 dB and image attenuation of 38 dB at 350 MHz. Diode CR1 
protects the RF amplifier by limiting excessive RF levels. The filter bandwidth is considerably wider 
than the receive band, to achieve low insertion loss in a compact size. C523 provides a transmission-
zero to improve image attenuation.
The output of the filter is matched to the base of RF amplifier Q21, which provides 18 dB of gain and 
a noise figure of 4 dB. A BFS505 device is used for high gain, low noise figure and reduced operating 
current. Operating voltage is obtained from the 5R source, which is turned off during transmit to 
reduce dissipation in Q21. Current mirror Q22 maintains the operating current of Q21 constant at 8 
mA regardless of device and temperature variations, for optimum dynamic range and noise figure.
DemodulatorCrystal
Filter  1st Mixer RF
AmpIF
Amp Preselector
FilterInterstage
 Filter
Recovered Audio
RSSI
RX from
Antenna Switch
Inj Filter
First LO
from Synthesizer
Ceramic
ResonatorCer FltrSwitching4E
6E6GBW_SEL 
						

							June, 20056880309N62-C
8-2403-440 MHz UHF Theory Of Operation: UHF Receiver
The output of the RF amplifier is applied to the interstage filter, a fixed-tuned 4-pole Butterworth 
shunt-coupled resonator design having a 3 dB bandwidth of 68 MHz centered at 462 MHz, and 
insertion loss of 3.5 dB. This filter yields an image rejection of 58 dB at 350 MHz, assisted by a 
transmission-zero at 300 MHz implemented by C524 for the reasons mentioned above.
The output of the interstage filter is connected to the passive double-balanced mixer consisting of 
components T41, T42, and CR41. This mixer has a conversion loss of 7.2 dB. Low-side injection from 
the frequency synthesizer is filtered by L40-L41 and C41-C45 to remove second harmonic energy 
that may degrade half-IF spurious rejection performance. The injection filter has a 3 dB bandwidth of 
100 MHz centered at 376.15 MHz, and an insertion loss of 2.7 dB. The second-harmonic rejection is 
typically 45 dB or greater. The filtered injection signal is applied to T42 at a level of +6 dBm.
The mixer output is applied to a diplexer network (L51-L52, C51, R51) which matches the 44.85 MHz 
IF signal to crystal filter FL51, and terminates the mixer into 50Ω at all other frequencies.
8.2.2 Receiver Back End
The receiver back end is a dual conversion design. High IF selectivity is provided by FL51, a 4-pole 
fundamental mode 44.85 MHz crystal filter with a minimum 3 dB bandwidth of ±6.7 kHz, a maximum 
20 dB bandwidth of + 12.5 kHz, and a maximum insertion loss of 3.5 dB. The output is matched to IF 
amplifier stage Q51 by L53 and C93. Q51 provides 16 dB of gain and a noise figure of 1.8 dB. The dc 
operating current is 1 mA. The output of Q51 is applied to the input of the receiver IFIC U51. Diode 
CR51 limits the maximum RF level applied to the IFIC.
The IFIC is a low-voltage monolithic FM IF system incorporating a mixer/oscillator, two limiting IF 
amplifiers, quadrature detector, logarithmic received signal strength indicator (RSSI), voltage 
regulator and audio and RSSI op amps. The second LO frequency, 44.395 MHz, is determined by 
Y51. The second mixer converts the 44.85 MHz high IF frequency to 455 kHz.
Additional IF selectivity is provided by two ceramic filters, FL52 (between the second mixer and IF 
amp) and FL53 or FL54 (between the IF amp and the limiter input). The wider filter FL53 is used for 
20/25 kHz channel spacing, and the narrower filter FL54 is used for 12.5 kHz channels. When the 
BW_SEL line is high, the two upper diodes in packages D51 and D52 are forward biased, selecting 
FL53 for 20/25 kHz channels. When the BW_SEL line is low, the two lower diodes in packages D51 
and D52 are forward biased, selecting FL54 for 12.5 kHz channels.
The ceramic filters have the following specifications:
Ceramic resonator Y70 provides phase vs. frequency characteristic required by the quadrature 
detector, with 90 degree phase shift occurring at 455 kHz. Buffer Q70 provides a lower driving 
impedance from the limiter to the resonator, improving the IF waveform and lowering the distortion of 
the recovered audio signal. The recovered audio level at the DEMOD output is 120 mV rms (25 kHz 
channel, 3 kHz deviation) or 60 mV rms (12.5 kHz channel, 1.5 kHz deviation). An additional RSSI 
output provides a DC voltage level that is proportional to RF signal level. This voltage is measured by 
an A/D converter contained in the microprocessor (PE4_AN4, U401 pin 63).FL52 FL53 FL54
Number of Elements: 4 6 6
Insertion Loss: 4 dB 4 dB 4 dB
6 dB Bandwidth: 15 kHz 15 kHz 9 kHz
50 dB Bandwidth: 30 kHz 30 kHz 22 kHz
Stopband Rejection: 27 dB 47 dB 47 dB 
						

							6880309N62-CJune, 2005
403-440 MHz UHF Theory Of Operation: UHF Transmitter 8-3
8.3 UHF Transmitter
The UHF transmitter covers the range of 403-440 MHz. Depending on model, the output power of the 
transmitter is either switchable on a per-channel basis between high power (4 watts) and low power 
(1 watt), or is factory preset to 2 watts. The transmitter is divided into four major blocks as shown in 
Figure 8-2.
• Power Amplifier
• Harmonic Filter 
• Antenna Matching Network
• Power Control.
Figure 8-2.  UHF Transmitter Block Diagram
8.3.1 Transmitter Power Amplifier
The transmitter power amplifier has three stages of amplification. The first stage, Q100, operates in 
Class A from the 5T source. It provides 17 dB of gain and an output of 50 mW. The current drain is 
typically 35mA. Components C105, C107 and L103 match the output of Q100 to the 50Ω input of the 
module U110.
U110 is a two stage Silicon MOS FET power amplifier module. Drain voltage is obtained from UNSW 
B+ after being routed through current-sense resistor R150 in the power control circuit. The output 
power of the module is controlled by varying the DC gate bias on U110 pin 2 (VGG).
8.3.2 Antenna Switch
The antenna switch consists of two pin diodes, D120 and D121. In the receive mode, both diodes are 
off. Signals applied at the antenna or at jack J140 are routed, via the harmonic filter, through network 
C122-C124 and L121, to the receiver input. In the transmit mode, Q170 is on and TXB+ is present, 
forward-biasing both diodes into conduction. The diode current is 20 mA, set by R120-R121. The 
transmitter RF from U110 is routed through D120, and via the harmonic filter to the antenna jack. 
D121 conducts, shunting RF power and preventing it from reaching the receiver. L121 is selected to 
appear as a 1/4 wave at UHF, so that the low impedance of D121 appears as a high impedance at the 
junction of D120 and the harmonic filter input. This provides a high series impedance and low shunt 
impedance divider between the power amplifier output and receiver input. 
8.3.3 Harmonic Filter
The harmonic filter consists of components C122 (Range 1 UHF) C136 and L130-L132. The 
harmonic filter is a seven-pole Chebychev low-pass configuration, optimized for low insertion loss, 
with a 3 dB frequency of approximately 600 MHz and typically less than 0.8 dB insertion loss in the 
passband.
Power Control
Harmonic Filter
Antenna
Matching
NetworkPower Amplifier Module U110Q100TX_INJ
(From VCO)5TVDD
VGG TX_ENA
PWR_SET
USWB+
RX_IN
(To Receiver)
Antenna
SwitchJ140 Antenna
Jack
Antenna 
						

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8-4403-440 MHz UHF Theory Of Operation: UHF Frequency Generation Circuitry
8.3.4 Antenna Matching Network
The harmonic filter presents a 50Ω impedance to antenna jack J140. A matching network, made up of 
C140-C141 and L140, is used to match the antenna impedance to the harmonic filter. This optimizes 
the performance of the transmitter and receiver into the impedance presented by the antenna, 
significantly improving the antennas efficiency.
8.3.5 Power Control
The power control circuit is a dc-coupled amplifier whose output is the dc gate bias voltage (VGG) 
applied to the two stages of the RF power amplifier U110.
The output power of the transmitter is adjusted by varying the setting of the power-set DAC contained 
in the ASFICcmp IC (DACG, U451 pin 6). This PWR_SET voltage is applied to U150 pin 3.
Stage U150-2 compares the voltage drop across current sense resistor R150 to the voltage drop 
across resistor R151 caused by current flow through Q150, and adjusts its output (pin 7) to maintain 
equal voltages at pins 5 and 6. Thus the current flow through Q150, and hence its emitter voltage, is 
proportional to the current drawn by stage U110, which is in turn proportional to the transmitter output 
power. The emitter voltage of Q150 is applied to U150 pin 2, where it is compared to the power set 
voltage PWR_SET at pin 3.  
The output of U150 pin 1 is divided by R110 and R111 and applied as a gate voltage to the power 
amplifier U110. By varying this gate voltage as needed to keep the voltages at U150 pins 2 and 3 
equal, power is maintained at the desired setting. Excessive final current, for example due to antenna 
mismatch, causes a lowering of the voltage at U150 pin 6, an increased voltage at pin 2, and a 
lowering of the voltage at pin 1 and of the gate voltage VGG. This prevents damage to the final stage 
due to excessive current. 
8.4 UHF Frequency Generation Circuitry
The frequency generation system, shown in Figure 8-3, is composed of two circuit blocks, the 
Fractional-N synthesizer IC U201, the VCO/Buffer IC U251, and associated circuitry. Figure 8-4 
shows the peripheral interconnect and support circuitry used in the synthesizer block, and Figure 8-5 
details the internal circuitry of the VCOBIC and its interconnections to the surrounding components. 
Refer to the schematic to identify reference designators.
The Fractional-N synthesizer is powered by regulated 5 V and 3 V provided by U310 and U330 
respectively. 5 V is applied to U201 pins 13 and 30, and 3 V is applied to pins 5, 20, 34 and 36. The 
synthesizer in turn generates a super-filtered 4.5 V supply (VSF, from pin 28) to power U251. In 
addition to the VCO, the synthesizer also interfaces with the logic and ASFICcmp circuits. 
Programming for the synthesizer is accomplished through the microprocessor SPI_DATA_OUT,  
						

							6880309N62-CJune, 2005
403-440 MHz UHF Theory Of Operation: UHF Frequency Generation Circuitry 8-5
SPI_CLK, and SYNTH_CS (chip select) lines (U409 pins 100, 1 and 47 respectively). A logic high (3 
V) from U201 pin 4 indicates to the microprocessor that the synthesizer is locked.
Figure 8-3.  UHF Frequency Generation Unit Block Diagram
Transmit modulation from the ASFICcmp (U451 pin 40) is applied to U201 pin 10 (MOD_IN). An 
electronic attenuator in the ASFICcmp adjusts overall transmitter deviation by varying the audio level 
applied to the synthesizer IC. Internally the audio is digitized by the Fractional-N synthesizer and 
applied to the loop divider to provide the low-port modulation. The audio is also routed through an 
internal attenuator for the purpose of balancing the low port and high port modulation and reducing 
the deviation by 6 dB for 12.5 kHz channels, and is available at U201 pin 41 (VCO_MOD). This audio 
signal is routed to the VCOs modulator.
8.4.1 Fractional-N Synthesizer
The Fractional-N synthesizer, shown in Figure 8-4, uses a 16.8 MHz crystal (Y201) to provide the 
reference frequency for the system. External components C201-C203, R202 and D201 are also part 
of the temperature-compensated oscillator circuit. The dc voltage applied to varactor D201 from U201 
pin 25 is determined by a temperature-compensation algorithm within U201, and is specific to each 
crystal Y201, based on a unique code assigned to the crystal that identifies its temperature 
characteristics. Stability is better than 2.5 ppm over temperatures of -30 to 60°C. Software-
programmable electronic frequency adjustment is achieved by an internal DAC which provides a 
frequency adjustment voltage from U201 pin 25 to varactor D201.
The synthesizer IC U201 further divides the 16.8 MHz signal to 2.1 MHz, 2.225 MHz, or 2.4 MHz for 
use as reference frequencies. It also provides a buffered 16.8 MHz signal at U201 pin 19 for use by 
the ASFICcmp. 
To achieve fast locking of the synthesizer, an internal adapt charge pump provides higher current at 
U201 pin 45 to quickly force the synthesizer within lock range. The required frequency is then locked 
by the normal mode charge pump at pin 43. A loop filter (C243-C245 and R243-R245) removes noise 
and spurs from the steering voltage applied to the VCO varactors, with additional filtering located in 
the VCO circuit. 
Both the normal and adapt charge pumps get their supply from the capacitive voltage multiplier made 
up of C221-C224 and D220-D221. Two 3 V square waves from U201 pins 14-15 provide the drive 
signals for the voltage multiplier, which generates 12.1 V at U201 pin 47. This voltage is filtered by 
C225-C228.
Synthesizer
U201VCOBIC
U251 Voltage
Multiplier 
Loop
Filter To Mixer
To PA Driver
VCP
Vmult1
Vmult2Aux3
MOD Out
Modulating
SignalRx VCO
Circuit 
Tx VCO
Circuit 
TRB
16.8 MHz
Ref. Osc.
Rx Out
Tx Out
Buffer
Q280 
						

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8-6403-440 MHz UHF Theory Of Operation: UHF Frequency Generation Circuitry
One of the auxiliary outputs of the synthesizer IC (AUX3, U201 pin 2) provides the TRB signal which 
determines the operating mode of the VCO, either receive or transmit.
Figure 8-4.  UHF Synthesizer Block Diagram
8.4.2 Voltage Controlled Oscillator (VCO)
The VCOBIC (U251), shown in Figure 8-5, in conjunction with the Fractional-N synthesizer (U201) 
generates RF in both the receive and the transmit modes of operation. The TRB line (U251 pin 19) 
determines which oscillator and buffer are enabled. A sample of the RF signal from the enabled 
oscillator is routed from U251 pin 12 through a low pass filter, to the prescaler input of the synthesizer 
IC (U201 pin 32). After frequency comparison in the synthesizer, a resultant DC control voltage is 
used to steer the VCO frequency. When the PLL is locked on frequency, this voltage can vary 
between 3.5 V and 10 V. L251 and C252 further attenuate noise and spurs on the steering line 
voltage.
In the receive mode, the TRB line (U251 pin 19) is low. This activates the receive VCO and the 
receive buffer of U251, which operate within the range of 358.15 to 395.15 MHz. The VCO frequency 
is determined by tank inductor L254, C253-C257, and varactor D251. The buffered RF signal at U251 
pin 8 is further amplified by Q280 and applied as RX_INJ to the low-pass injection filter in the receiver 
front end circuit.
In the transmit mode, U251-19 is driven high by U201 pin 2, enabling the transmit VCO and buffer. 
The 403-470 MHz RF signal from U251 pin 10 is applied as TX_INJ to the input of the transmitter 
circuit via matching network C290-C291 and L291. TX VCO frequency is determined by L264, C263-
DATA
CLK
CEX
MODIN
V
CC, 5V
XTAL1
WARP
PREIN
VCP Reference
Oscillator
Voltage
Multiplier Voltage
Controlled
Oscillator
2-Pole
Loop Filter DATA (U401 Pin 100)
CLOCK (U401 Pin 1)
SYNTH_CS (U401 Pin 47)
MOD IN (U451 Pin 40)
+5V (U310 Pin 5)7
8
9
10
13,30
23
25
32
47
VMULT2
VMULT1BIAS1 SFOUTAUX3 IADAPTIOUTGND FREFOUTLOCK4
19
6,22,23,24
43
45
2
28
141540Filtered 5VSteering
Line LOCK (U401 Pin 56)
Prescaler InLO RF
Injection
TX RF
Injection
(First Stage of PA) FREF (U451 Pin 34)
39
BIAS241
+3V (U330 Pin 5)
V
DD, 3VMODOUTU201
Low Voltage
Fractional-N
Synthesizer 5,20,34,36
TRB
VCO
Mod 
						

							6880309N62-CJune, 2005
403-440 MHz UHF Theory Of Operation: UHF Frequency Generation Circuitry 8-7
C267, and varactor D261. High-port audio modulation from the synthesizer IC is applied as 
VCO_MOD to varactor D262 which modulates the transmit VCO.
Figure 8-5.  UHF VCO Block Diagram
Presc
RX
TX
Matching 
Network Pin 8
Pin 14
Pin 103V (U330 Pin 5)
VCC BuffersU201 Pin 32 AUX3 (U201 Pin 2)
Prescaler Out
Pin 12 Pin 19 Pin 20
TX/RX/BS
Switching Network
U251
VCOBIC
Rx Active
Bias
Tx Active
Bias
Pin 2
Rx-I adjustPin 1
Tx-I adjustPins 9,11,17
Pin 18Vsens
Circuit Pin 15 Pin 16
TX VCO
Circuit
TX
TankRX VCO
Circuit RX
TankPin 7
Vcc-Superfilter
Collector/RF in
Pin 4
Pin 5
Pin 6RX
TX V_SF (U201 Pin 28)NC
NC
Vcc-Logic
3V 
(U330 Pin 5) Steer Line
Voltage
(V_STEER) Pin 13
Pin 3
TRB_IN
Buffer
Q280
RX INJ
V_SF
(U201 Pin 28)
TX INJ 
						

							June, 20056880309N62-C
Notes:
8-8403-440 MHz UHF Theory Of Operation: UHF Frequency Generation Circuitry