Motorola Gm Series Detailed 6864115b62 B Manual

							Controller Board Audio and Signalling Circuits 1-13
may be as high as 250 Hz, which is audible to the human ear. However, the radio receiver filters out 
any audio below 300Hz, so these tones are never heard in the actual system.
Only one type of sub-audible data can be generated by U0221 (ASFIC CMP) at any one time. The 
process is as follows, using the SPI BUS, the µP programs the ASFIC CMP to set up the proper low-
speed data deviation and select the PL or DPL filters. The µP then generates a square wave which 
strobes the ASFIC PL / DPL encode input LSIO U0221-18 at twelve times the desired data rate. For 
example, for a PL frequency of 103Hz, the frequency of the square wave would be 1236Hz.
This drives a tone generator inside U0221 which generates a staircase approximation to a PL sine 
wave or DPL data pattern. This internal waveform is then low-pass filtered and summed with voice or 
data. The resulting summed waveform then appears on U0221-40 (MOD IN), where it is sent to the 
RF board as previously described for transmit audio. A trunking connect tone would be generated in 
the same manner as a PL tone.
2.3.2 High Speed Data
High speed data refers to the 3600 baud data waveforms, known as Inbound Signalling Words 
(ISWs) used in a trunking system for high speed communication between the central controller and 
the radio. To generate an ISW, the µP first programs the ASFIC CMP (U0221) to the proper filter and 
gain settings. It then begins strobing U0221-19 (HSIO) with a pulse when the data is supposed to 
change states. U0221’s 5-3-2 State Encoder (which is in a 2-state mode) is then fed to the post-
limiter summer block and then the splatter filter. From that point it is routed through the modulation 
attenuators and then out of the ASFIC CMP to the RF board. MPT 1327 and MDC are generated in 
much the same way as Trunking ISW. However, in some cases these signals may also pass through 
a data pre-emphasis block in the ASFIC CMP. Also these signalling schemes are based on sending 
a combination of 1200 Hz and 1800 Hz tones only. Microphone audio is muted during High Speed 
Data signalling.
2.3.3 Dual Tone Multiple Frequency (DTMF) Data
DTMF data is a dual tone waveform used during phone interconnect operation. It is the same type of 
tones which are heard when using a Touch Tone telephone.
There are seven frequencies, with four in the low group (697, 770, 852, 941Hz) and three in the high 
group (1209, 1336, 1477Hz).
The high-group tone is generated by the µP (U0101-44) strobing U0221-19 at six times the tone 
frequency for tones less than 1440Hz or twice the frequency for tones greater than 1440Hz. The low 
group tone is generated by the ASFIC CMP, controlled by the µP via SPI bus. Inside U0221 the low-
group and high-group tones are summed (with the amplitude of the high group tone being 
approximately 2 dB greater than that of the low group tone) and then pre-emphasized before being 
routed to the summer and splatter filter. The DTMF waveform then follows the same path as was 
described for high-speed data. 
						

							1-14THEORY OF OPERATION
2.4 Receive Audio Circuits
Refer to Figure5-5 for reference for the following sections.
Figure 4-1 Receive Audio Paths
2.4.1 Squelch Detect
The radio’s RF circuits are constantly producing an output at the discriminator (IF IC). This signal 
(DISC AUDIO) is routed to the ASFIC CMP’s squelch detect circuitry input DISC (U0221-2). All of 
the squelch detect circuitry is contained within the ASFIC CMP. Therefore from a user’s point of view, 
DISC AUDIO enters the ASFIC CMP, and the ASFIC CMP produces two CMOS logic outputs based 
on the result. They are CH ACT (U0221-16) and SQ DET (U0221-17).
The squelch signal entering the ASFIC CMP is amplified, filtered, attenuated, and rectified. It is then 
sent to a comparator to produce an active high signal on CH ACT. A squelch tail circuit is used to 
produce SQ DET (U0221-17) from CH ACT. The state of CH ACT and SQ DET is high (logic 1) when 
carrier is detected, otherwise low (logic 0).
CH ACT is routed to the µP pin 84 while SQ DET is routed to the µP pin 83.
SQ DET is used to determine all audio mute / unmute decisions except for Conventional Scan. In 
this case CH ACT is a pre-indicator as it occurs slightly faster than SQ DET.
FLT/FLAT RX AUDIO
J050111
16
1EXTERNAL
SPEAKER
INTERNAL
SPEAKER ACCESSORY
CONNECTOR
CONTROLHEAD
CONNECTOR
HANDSET
AUDIO 7 2 3
J0401 INT
SPKR-
SPKR +
SPKR -1
9
2
J0551
41 10
INT
SPKR+
4
6
DISC
ASFIC_CMP
U0221
AUDIO 
PA
U0271
IN
OPTION
BOARD
IN OUT
VOLUME
ATTEN.
FILTER AND
DEEMPHASIS
17
MICRO 
CONTROLLER
U010180 FROM
RF
SECTION
(IF IC)
LIMITER, RECTIFIER
FILTER, COMPARATOR
SQ DETSQUELCH
CIRCUIT
16
PL  FILTER 
LIMITER
CH ACT
AUX RX43
18
LS IO
U IOAUDIO
8384
39URX OUT
17
J0451
EXPANSION
BOARDDISC
AUDIO34 28
35
85
IN
7 
						

							Controller Board Audio and Signalling Circuits 1-15
2.4.2 Audio Processing and Digital Volume Control
The receiver audio signal enters the controller section from the IF IC on DISC AUDIO. The signal is 
DC coupled by R0228 and enters the ASFIC CMP via the DISC pin U0221-2.
Inside the ASFIC CMP, the signal goes through 2 paths in parallel, the audio path and the PL/DPL 
path.
The audio path has a programmable amplifier, whose setting is based on the channel bandwidth 
being received, then a LPF filter to remove any frequency components above 3000Hz and then an 
HPF to strip off any sub-audible data below 300Hz. Next, the recovered audio passes through a de-
emphasis filter if it is enabled (to compensate for Pre-emphasis which is used to reduce the effects of 
FM noise). The IC then passes the audio through the 8-bit programmable attenuator whose level is 
set depending on the value of the volume control. Finally the filtered audio signal passes through an 
output buffer within the ASFIC CMP. The audio signal exits the ASFIC CMP at pin AUDIO (U0221-
41).
The µP programs the attenuator, using the SPI BUS, based on the volume setting. The minimum / 
maximum settings of the attenuator are set by codeplug parameters.
Since sub-audible signalling is summed with voice information on transmit, it must be separated from 
the voice information before processing. Any sub-audible signalling enters the ASFIC CMP from the 
IF IC at DISC U0221-2. Once inside it goes through the PL/DPL path. The signal first passes through 
one of 2 low pass filters, either PL low pass filter or DPL/LST low pass filter. Either signal is then 
filtered and goes through a limiter and exits the ASFIC CMP at LSIO (U0221-18). At this point the 
signal will appear as a square wave version of the sub-audible signal which the radio received. The 
microprocessor U0101-80 will decode the signal directly to determine if it is the tone / code which is 
currently active on that mode.
2.4.3 Audio Amplification Speaker (+) Speaker (-)
The output of the ASFIC CMP’s digital volume pot, U0221-41 is routed through dc blocking capacitor 
C0265 to a buffer formed by U0211-1. Resistors R0265 and R0268 set the correct input level to the 
audio PA (U0271). This is necessary because the gain of the audio PA is 46 dB, and the ASFIC CMP 
output is capable of overdriving the PA unless the maximum volume is limited. Resistor R0267 and 
capacitor C0267 increase frequency components below 350 Hz.
The audio then passes through R0269 and C0272 which provides AC coupling and low frequency 
roll-off. C0273 provides high frequency roll-off as the audio signal is routed to pins 1 and 9 of the 
audio power amplifier U0271.
The audio power amplifier has one inverted and one non-inverted output that produces the 
differential audio output SPK+ / SPK- (U0271-4/6). The inputs for each of these amplifiers are pins 1 
and 9 respectively; these inputs are both tied to the received audio. The audio PA’s DC biases are 
not activated until the audio PA is enabled at pin 8.
The audio PA is enabled via the ASFIC CMP (U0221-38). When the base of Q0271 is low, the 
transistor is off and U0271-8 is high, using pull up resistor R0273, and the Audio PA is ON. The 
voltage at U0273-8 must be above 8.5VDC to properly enable the device. If the voltage is between 
3.3 and 6.4V, the device will be active but has its input (U0273-1/9) off. This is a mute condition which 
is used to prevent an audio pop when the PA is enabled.
The SPK+ and SPK- outputs of the audio PA have a DC bias which varies proportionately with FLT 
A+ (U0271-7). FLT A+ of 11V yields a DC offset of 5V, and FLT A+ of 17V yields a DC offset of 8.5V. 
If either of these lines is shorted to ground, it is possible that the audio PA will be damaged. SPK+ 
and SPK- are routed to the accessory connector (J0501-16 and 1) and to the controlhead (connector 
J0401-2 and 3). 
						

							1-16THEORY OF OPERATION
2.4.4 Handset Audio
Certain hand held accessories have a speaker within them which require a different voltage level 
than that provided by U0271. For those devices HANDSET AUDIO is available at controlhead 
connector J0401-7.
The received audio from the output of the ASFIC CMP’s digital volume attenuator and buffered by 
U0211-1 is also routed to U0211-3 pin 9 where it is amplified 20 dB; this is set by the 10k/100k 
combination of R0261 and R0262. This signal is routed from the output of the op amp U0211-3 pin 8 
to J0401-7. The controlhead sends this signal directly out to the microphone jack. The maximum 
value of this output is 6.6Vp-p.
2.4.5 Filtered Audio and Flat Audio
The ASFIC CMP has an audio whose output at U0221-39 has been filtered and de-emphasized, but 
has not gone through the digital volume attenuator. From ASFIC CMP U0221-39 the signal is routed 
via R0251 through gate U0251-12 and AC coupled to U0211-2. The gate controlled by ASFIC CMP 
port GCB3 (U0221-35) selects between the filtered audio signal from the ASFIC CMP pin 39 
(URXOUT) or the unfiltered (flat) audio signal from the ASFIC CMP pin 10 (UIO). R0251 and R0253 
determine the gain of op-amp U0211-2 for the filtered audio while R0252 and R0253 determine the 
gain for the flat Audio. The output of U0253-7 is then routed to J0501-11 via dc blocking capacitor 
C0542 and R0531. Note that any volume adjustment of the signal on this path must be done by the 
accessory
2.4.6 RX Secure Audio (optional)
Discriminator audio, which is now encrypted audio, follows the normal receive audio processing until 
it emerges from the ASFIC CMP UIO pin (U0221-10), which is fed to the Secure board residing at 
option connector J0551-35. On the Secure board, the encrypted signal is converted back to normal 
audio format, and then fed back through (J0551-34) to AUX RX of the ASFIC CMP (U0221-43). 
From then on it follows a path identical to conventional receive audio, where it is filtered (0.3 - 3kHz) 
and de-emphasized. The signal URX SND from the ASFIC CMP (U0221-39), also routed to option 
connector J0551-28, is not used for the Secure board but for other option boards.
2.4.7 Option Board Receive Audio
Unfiltered audio from the ASFIC CMP pin UIO (U0221-10) enters the option board at connector 
J0551-35. Filtered audio from the ASFIC CMP pin URXOUT (U0221-39) enters the option board at 
connector J0551-28. On the option board, the signal may be processed, and then fed back through 
J0551-34 to AUX RX of the ASFIC CMP (U0221-43). From then on it follows a path identical to 
conventional receive audio, where it may be filtered (0.3 - 3kHz) and de-emphasized. 
						

							Controller Board Audio and Signalling Circuits 1-17
2.5 RECEIVE SIGNALLING CIRCUITS
Refer to Figure 5-6 for reference for the following sections.
Figure 4-2 Receive Signalling Paths
2.5.1 Sub-audible (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) is used to filter and limit all received data. The data enters the ASFIC CMP 
at input DISC (U0221-2). Inside U0221 the data is filtered according to data type (HS or LS), then it 
is limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221-19, where 
it connects to the µP U0101-82
The low speed limited data output (PL, DPL, and trunking LS) appears at U0221-18, where it 
connects to the µP U0101-80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch 
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236, and 
C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS data. 
The hysterisis of these limiters is programmed based on the type of received data.
2.5.2 Alert Tone  Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key 
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it 
sends an alert tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the 
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways: 
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained 
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and 
at what volume level to generate the tone. (It does not have to be related to the voice volume setting).
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is 
accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19. 
Inside the ASFIC CMP this signal is routed to the alert tone generator
The output of the generator is summed into the audio chain just after the RX audio de-emphasis 
block. Inside U0221 the tone is amplified and filtered, then passed through the 8-bit digital volume 
attenuator, which is typically loaded with a special value for alert tone audio. The tone exits at U0221-
41 and is routed to the audio PA like receive audio
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF  IC)19
18
25
2
82
80
DISC
PLCAP2LSIO HSIO DATA FILTER
AND DEEMPHASISLIMITER
FILTER
LIMITERASFIC_CMP
U0221
MICRO
CONTROLLER
U0101
85 44
8 PLCAP 
						

							1-18THEORY OF OPERATION
2.6 Voice Storage (optional)
The Voice Storage (VS) option can be used to store audio signals coming from the receiver or from 
the microphone. Any stored audio signal can be played back over the radio’s speaker or sent out via 
the radio’s transmitter.
The Voice Storage option can by placed on the controller section or on an additional option board 
which resides on option board connector J0551. Voice Storage IC U0301 provides all required 
functionality and is powered from 3.3 volts regulator U0351 which,is powered from the regulated 5 
volts. Dual shottky diode D0301 reduces the supply voltage for U0301 to 3 volts. The microprocessor 
controls U0301 via SPI bus lines CLK (U0301-8), DATA (U0301-10) and MISO (U0301-11). To 
transfer data, the µP first selects the U0301 via address decoder U0141, line VS CS and U0301 pin 
9. Then the µP sends data through line DATA and receives data through line MISO. Pin 2 (RAC) of 
U0301 indicates the end of a message row by a low state for 12.5 ms and connects to µP pin 52. A 
low at pin 5 (INT), which is connected to µP pin 55 indicates that the Voice Storage IC requires 
service from the µP.
Audio, either from the radio’s receiver or from one of the microphone inputs, emerges the ASFIC 
CMP (U0221) at pin 39, is buffered by op-amp U0341-1 and enters the Voice Storage IC U0301 at 
pin 25. During playback, the stored audio emerges U0301 at pin 20. To transmit the audio signal it is 
fed through resistive divider R0344 / R0345 and line VS MIC to input selector IC U0251. When this 
path is selected by the µP via ASFIC CMP port GCB 4, the audio signal enters the ASFIC CMP at 
pin 48 and is processed like normal transmit audio. To play the stored audio over the radio’s speaker, 
the audio from U0301 pin 20 is buffered by op-amp U0341-2 and fed via switch U0342 and line FLAT 
RX SND to ASFIC CMP pin 10 (UIO). In this case, this ASFIC CMP pin is programmed as input and 
feeds the audio signal through the normal receiver audio path to the speaker or handset. Switch 
U0342 is controlled by the µP via ASFIC CMP port GCB 4 and feeds the stored audio only to the 
ASFIC CMP port UIO when it is programmed as input. 
						

							Chapter 2
TROUBLESHOOTING CHARTS
1.0 Controller Troubleshooting  Chart 
Controller Check
Power Up 
Alert Tone
 OK?
Speaker & 
Control 
Head OK?
U0101
EXTAL= 
7.3728 MHz/ 
14.7456 
MHz? 
BUS+
activity when 
volume knob 
rotated?
MCU is OK
Not able to 
program 
RF Board ICsBefore replacing 
MCU, check SPI 
clock, SPI data, 
and RF IC select 
Replace 
Speaker / Con-
trol Head
U0221 Pin 34 = 
16.8 MHz?
Check 
FGU
Reprogram the 
correct data. & 
Check ASFIC 
and MCU
Check Control 
Head and MCU 
(U0101, U0121, 
U0122, U0111)
Press PTT. No 
RF Output Pow-
er.
Red LED 
lights up?
Check 
Control 
Head
Check 
FGU & 
Transmitter Audio
at Pin 41 
U0221?
Enable External PTT 
with CPS External PTT en-
abled with CPS?Radio could 
not PTT 
externally
DC
at as-
signed Acc. 
Con. Pin 
DC chang-
es?
Check Components 
between U0221 and 
U0271
Check Con-
nection to uP 
port
PTT
NO
YES
NO
YES
YES YESYES
NO
NO
YES
NO
YES
NO
YESNO
YES EXT
PTT RX
AUDIO
Check 
Accessories J0501
Audio at Pin 
16 & 
Pin 1
Check Spk. 
Flex Connec-
tion & Control 
Audio 
at Audio PA 
(U0271) 
input
Check AS-
FIC U0221
Check
 Audio PA 
(U0271)
Check Re-
ceiver &
 IF ICAudio at 
Pin 2 
U0221?
NO
NO
NO YESYES
NO
YES
NO
Before troubleshooting the controller section ac-
cording to this chart please check the following:
1. Check tuning and CPS settings
2. Check if Alert Tones are enabled
3. Check if Control Head is OK
4. Check board visually9.3V
DC at Pin 5 
of U0641? 
YESNO
5V DC at 
Pin OUT of 
U0651? 
YESNO
Check U0641, Q0641, 
Q0661, D0660 & 
D0661
Check U0651, D0651, 
D0621 
						

							2-2TROUBLESHOOTING CHARTS 
						

							Chapter 3
CONTROLLER SCHEMATICS / PARTS LIST
1.0Allocation of Schematics and Circuit Boards
1.1 Controller Circuits
This Chapter shows the Schematics and the the Parts Lists for the Controller circuits. 
1.2 Voice Storage Facility
The Voice Storage is fitted on all MPT radios GM640/660/1280 and on GM380 as standard.
The schematics, component layout and parts list for these circuits are shown in this chapter. 
The Voice Storage schematic is shown in Tables below.
.
.
Table 3-1   Controller T2 Diagrams and Parts Lists
Controller T2 used on PCB :
8486172B04 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Page 3-3
Page 3-4
Page 3-5
Page 3-6
Page 3-7
Par ts List
Controller T2Page 3-8
Table 3-2   Controller T5 Diagrams and Parts Lists
Controller T5 used on PCB :
8486172B06 VHF, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-10
Page 3-11
Page 3-12
Page 3-13
Page 3-14
Page 3-15
Par ts List
Controller T5Page 3-16
Table 3-3   Controller T6/7 Diagrams and Parts Lists
Controller T6/T7 used on PCB :
T6 on 8486206B06 LB1, 25-60W
T6 on 8486207B05 LB2, 25-60W
T6 on 8486140B12 VHF, 25-45W
T6 on 8480643z06 UHF B1, 25-40W
T7 on 8486172B07 VHF, 1-25W
T7 on 8485670z02 UHF B1, 1-25W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O T6
I/O T7
Microprocessor
Voice Storage (if fitted)
Page 3-18
Page 3-19
Page 3-20
Page 3-21
Page 3-22
Page 3-23
Page 3-24
Par ts List
Controller T6/T7Page 3-25 
						

							3-2Controller schematics / parts list
.
.
.Table 3-4   Controller T9 Diagrams and Parts Lists
Controller T9 used on PCB :
8486172B08 VHF, 1-25W
8486140B13 VHF, 25-45W
8485670z03 UHF B1, 1-25W
8485908Z02 LB3, 25-60W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-27
Page 3-28
Page 3-29
Page 3-30
Page 3-31
Page 3-32
Parts List
Controller T9Page 3-33
Table 3-5   Controller T11 Diagrams and Parts Lists
Controller T11 used on PCB :
8486206B08 LB1, 25-60W
8486207B07 LB2, 25-60W
8485908Z04 LB3, 25-60W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Page 3-35
Page 3-36
Page 3-37
Page 3-38
Page 3-39
Parts List
Controller T11Page 3-40
Table 3-6   Controller T12 Diagrams and Parts Lists
Controller T12 used on PCB :
8486127B01 UHF, 25-40W
8486140B15 VHF, 25-45W
SCHEMATICS
Controller Overall
Supply Voltage
Audio
I/O
Microprocessor
Voice Storage (if fitted)
Page 3-42
Page 3-43
Page 3-44
Page 3-45
Page 3-46
Page 3-47
Parts List
Controller T12Page 3-48