Motorola Gm Series Detailed 6864115b62 B Manual

							UHF (403-470MHz) Frequency Synthesis2-7
A voltage of 5V applied to the super filter input (U4201 pin 30) supplies an output voltage of 4.5 
VDC(VSF) at pin 28. It supplies the VCO, VCO modulation bias circuit (via R4322) and the 
synthesizer charge pump resistor network (R4251, R4252). The synthesizer supply voltage is 
provided by the 5V regulator U4211.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U4201-47), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry 
(D4201, C4202, C4203). This voltage multiplier is basically a diode capacitor network driven by two 
(1.05MHz) 180 degrees out of phase signals (U4201-14 and -15).
Output LOCK (U4201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. IC U4201 provides the 16.8 MHz reference frequency at 
pin 19.
The serial interface (SRL) is connected to the microprocessor via the data line DATA (U4201-7), 
clock line CLK (U4201-8), and chip enable line CSX (U4201-9).
4.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) consists of the VCO/Buffer IC (VCOBIC, U4301), the TX 
and RX tank circuits, the external RX buffer stages, and the modulation circuitry.
Figure 2-4 UHF VCO Block Diagram
 
Presc
RX
TXMatching
NetworkLow Pass
    Filter
Attenuator Pin8
Pin14
Pin10(U4201 Pin28)
VCC Buffers
TX RF Injection U4201 Pin 32 AUX3 (U4201 Pin 2)
Prescaler Out
Pin 12 Pin 19 Pin 20
      TX/RX/BS
Switching Network
U4301
VCOBIC
       Rx
Active Bias
      Tx
Active Bias
Pin2
Rx-I adjustPin1
Tx-I adjustPins 9,11,17
Pin18Vsens
Circuit Pin15Pin16 RX VCO
 Circuit
TX VCO
 Circuit RX Tank
TX TankPin7
Vcc-Superfilter
Collector/RF in
Pin4
Pin5
Pin6
RX
TX
(U4201 Pin 28)Rx-SW
Tx-SW
Vcc-Logic
(U4201 Pin 28) Steer Line 
Voltage 
(VCTRL)Pin13
Pin3TRB IN
LO RF INJECTION
Q4301
Q4332 
						

							2-8THEORY OF OPERATION
The VCOBIC together with Fractional-N synthesizer (U4201) generates the required frequencies in 
both  transmit and receive modes. The TRB line (U4301 pin 19) determines which tank circuits and 
internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and  
a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is 
routed from U4301 pin 12 (PRESC_OUT), via a low pass filter, to pin 32 of U4201 (PREIN).
A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR4311 will tune the full 
TX frequency range (TXINJ) from 403 MHz to 470 MHz, and at varactor diodes CR4301, CR4302 
and CR4303 will tune the full RX frequency range (RXINJ) from 358 MHz to 425 MHz. The tank 
circuits uses the Hartley configuration for wider bandwidth. For the RX tank circuit, an external 
transistor Q4301 is used in conjunction with the internal transistor for better side-band noise.
The external RX buffers (Q4332) are enabled by a high at U4201 pin 3 (AUX4) via transistor switch 
Q4333.  In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U4201 
pin41) is applied modulation circuitry CR4321, R4321, R4322 and C4324, which modulates the TX 
VCO frequency via coupling capacitor C4321.  Varactor CR4321 is biased for linearity from VSF.
4.4 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage FRAC-N (LVFRACN) IC, 
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop 
filter circuitry and DC supply. The output signal PRESC_OUT of the VCOBIC (U4301 pin12) is fed to 
pin 32 of U4201 (PREIN) via a low pass filter (C4229, L4225) which attenuates harmonics and 
provides the correct level to close the synthesizer loop.
The pre-scaler in the synthesizer (U4201) is basically a dual modulus pre-scaler with selectable 
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output 
of the loop divider is connected to the phase detector, which compares the loop divider´s output 
signal with the reference signal.The reference signal is generated by dividing down the signal of the 
reference oscillator (Y4261 or Y4262).
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at pin 43 of U4201 (IOUT). The loop filter (which consists of 
R4221-R4223, C4221-C4225,L4221) transforms this current into a voltage that is applied to the 
varactor diodes CR4311 for transmit, CR4301, CR4302 & CR4303 for receive and alters the output 
frequency of the VCO .The current can be set to a value fixed in the LVFRAC-N IC or to a value 
determined by the currents flowing into BIAS 1 (U4201-40) or BIAS 2 (U4201-39). The currents are 
set by the value of R4251 or R4252 respectively. The selection of the three different bias sources is 
done by software programming.
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT  (U4201-45) for a certain 
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high 
transient of the CSX line. When the synthesizer is within the lock range the current is determined 
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled 
synthesizer loop is indicated by a high level of signal LOCK (U4201-4). 
The LOCK (U4201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the 
µP determines whether LOCK  is active. In order to modulate the PLL the two spot modulation 
method is utilized. Via pin 10 (MODIN) on U4201 the audio signal is applied to both the A/D 
converter (low freq path) as well as the balance attenuator (high freq path). The A/D converter 
converts the low frequency analogue modulating signal into a digital code that is applied to the loop 
divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO’s 
deviation sensitivity to high frequency modulating signals. The output of the balance attenuator is 
present at the MODOUT port (U4201-41) and connected to the VCO modulation diode CR4321 via 
R4321, C4325. 
						

							UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W 2-9
5.0 UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W
The radio’s 40 W PA is a four stage amplifier used to amplify the output from the VCOBIC to the radio 
transmit level. It consists of the following four stages in the line-up. The first stage is a LDMOS 
predriver (U4401) that is controlled by pin 4 of PCIC (U4501) via Q4473 (CNTLVLTG). It is followed 
by another LDMOS stage (Q4421), an LDMOS stage (Q4431) and a bipolar final stage (Q4441).
Figure 2-1 UHF Transmitter Block Diagram 
Device Q4401 is surface mounted. Q4421, Q4431 and Q4441 are directly attached to the heat sink.
5.1 Power Controlled Stage
The first stage (U4401) amplifies the RF signal from the VCO (TXINJ) and controls the output power 
of the PA. The output power of the transistor U4401 is controlled by a voltage control line feed from 
the PCIC pin4(U4501). The control voltage simultaneously varies the bias of two FET stages within 
U4401. This biasing point determines the overall gain of U4401 and therefore its output drive level to 
Q4421, which in turn controls the output power of the PA. 
In receive mode the voltage control line is at ground level and turns off Q4473 which in turn switches 
off the biasing voltage to U4401.
5.2 Pre-Driver Stage
The next stage is a 13dB gain LDMOS device (Q4421) which requires a positive gate bias and a 
quiescent current flow for proper operation. The voltage of the line PCIC_MOSBIAS_1 is set in 
transmit mode by PCIC pin 24 and fed to the gate of Q4421 via the resistive network R4480, R4416 
and R4415. The bias voltage is tuned in the factory.PCIC
Pin Diode 
Antenna 
Switch
RF JackAntenna
Harmonic 
Filter
PowerSensePA-FinalStagePADriver From VCOControlledStage
VcontrolBias 1Bias 2
To Microprocessor
Temperature
Sense SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
PreDriver 
						

							2-10THEORY OF OPERATION
5.3 Driver Stage
The following stage is an enhancement-mode N-Channel MOSFET device (Q4431) providing a gain 
of 10dB. This device also requires a positive gate bias and a quiescent current flow for proper 
operation. The voltage of the line Bias_2_UHF_PA_1 is set in transmit mode by the ASFIC and fed to 
the gate of Q4431 via the resistive network R4632, R4631, R4485 and R4486. This bias voltage is 
also tuned in the factory. If the transistor is replaced, the bias voltage must be tuned using the 
Customer Programming Software (CPS). Care must be taken not to damage the device by exceeding 
the maximum allowed bias voltage. The device’s drain current is drawn directly from the radio’s DC 
supply voltage input, A+, via L4421.
5.4 Final Stage
The final stage uses the bipolar device Q4441. The device’s collector current is also drawn from the 
radio’s DC supply voltage input. To maintain class C operation, the base is DC-grounded by a series 
inductor (L4441) and a bead (L4440). A matching network consisting of C4441-C4444, C4491 and 
two striplines transforms the impedance to 50 Ohms and feeds the directional coupler.
5.5 Directional Coupler
The Bi-directional coupler is a microstrip printed circuit, which couples a small amount of the forward 
and reverse power of the RF power from Q4441. The coupled signal is rectified to an output power 
proportional DC voltage by the diodes D4451 & D4452 and sent to the RFIN of PCIC. The PCIC 
controls the gain of stage U4401 as necessary to hold this voltage constant, thus ensuring the 
forward power out of the radio to be held to a constant value.
5.6 Antenna Switch
The antenna switch consists of two PIN diodes, D4471 and D4472. In the receive mode, both 
diodes are off. Signals applied at the antenna jack J4401 are routed, via the harmonic filter, through 
network L4472, C4474 and C4475, to the receiver input. In the transmit mode, K9V1 turns on 
Q4471 which enables current sink Q4472, set to 96 mA by R4511 and VR4471. This completes a 
DC path from PASUPVLTG, through L4437, D4471, L4472, D4472, L4473, R4496 and the current 
sink, to ground. Both diodes are forward biased into conduction. The transmitter RF from the 
directional coupler is routed via D4471 to the harmonic filter and antenna jack. D4472 also 
conducts, shunting RF power and preventing it from reaching the receiver port (RXIN). L4472 is 
selected to appear as a broadband Lambda/4 wave transmission line, making the short circuit 
presented by D4472 appear as an open circuit at the junction of D4472 and the receiver path.
5.7 Harmonic Filter
Inductors L4491, L4492, L4493 and capacitors C4448, C4492,C4494, C4496 and C4498 form a 
low-pass filter to attenuate harmonic energy of the transmitter to specifications level. R4491 is used 
to drain electrostatic charge that might otherwise build up on the antenna.  The harmonic filter also 
prevents high level RF signals above the receiver passband from reaching the receiver circuits, 
improving spurious response rejection. 
						

							UHF (403-470MHz) Transmitter Power Amplifier (PA) 40W 2-11
5.8 Power Control
The transmitter uses the Power Control IC (PCIC, U4501) to control the power output of the radio. A 
portion of the forward RF power from the transmitter is sampled by the bi-directional coupler and 
rectified, to provide a DC voltage to the RFIN port of the PCIC (pin 1) which is proportional to the 
sampled RF power. 
The PCIC has internal digital to analog converters (DACs) which provide the reference voltage of the 
control loop. The reference voltage level is programmable through the SPI line of the PCIC. This 
reference voltage is proportional to the desired power setting of the transmitter, and is factory 
programmed at several points across the frequency range of the transmitter to offset frequency 
response variations of the transmitter s power detector circuitry.
The PCIC provides a DC output voltage at pin 4 (INT) which is applied as CNTLVLTG to the power-
adjust input pin of the first transmitter stage U4401. This adjusts the transmitter power output to the 
intended value. Variations in forward transmitter power cause the DC voltage at pin 1 to change, and 
the PCIC adjusts the control voltage above or below its nominal value to raise or lower output power.
Capacitors C4502-4, in conjunction with resistors and integrators within the PCIC, control the 
transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into 
adjacent channels.
U4502 is a temperature-sensing device, which monitors the circuit board temperature in the vicinity 
of the transmitter driver and final devices, and provides a dc voltage to the PCIC (TEMP, pin 29) 
proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the 
transmitter output power will be reduced so as to reduce the transmitter temperature. 
						

							2-12THEORY OF OPERATION 
						

							Chapter 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
Bad SINAD
Bad 20dB Quieting
No Recovered AudioSTART
Audio at 
pin 8 of 
U3101 ?Check Controller
(in the case of no audio)
OR ELSE go to “B” Ye s
No
Spray or inject 44.85MHz 
into XTAL Filter FL3101
Audio heard ?BYe s
No
Check 2nd LO 
(44.395MHz) at C3135 
LO present ?BYe s
 Check voltages on 
U3101Biasing OK ?
No
No
A
Ye s
Check Q3102  bias 
for faults
Replace Q3102
Go to B
Ye s
No
Check circuitry 
around U3101.
Replace 
U3101 if defectCheck circuitry around Y3101 Re-
place Y3101 if defectVoltages
 OK? 
						

							3-2TROUBLESHOOTING CHARTS
1.1Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at 
C3101?
No
RF 
Signal at 
T4051?
RF
Signal at 
C4015?
No
No
RF
Signal at 
C4025?
No or 
Check harmonic filter
L4491-L4493, C4492, J4401
and ant.switch
D4471, D4472, L4472.
Check filter between 
C4025 & C4009. 
Check tuning voltage 
at R4060.
Inject RF into J4401
Is
tuning voltage
OK?
No
Ye s
Check RF amp (Q4003) 
Stage.
Check filter between 
C4015 & T4051.
Ye s
Check T4051, T4052, 
D4051, R4052, L4008.
Ye s
1st LO level 
OK?
Locked?Ye s
Check FGU
Ye s
Trace IF signal 
from C3101 to 
Q3101. Check for 
bad XTAL filter.
No
Ye sIF
signal at Q3102 
collector?
Before replacing 
U3101, check 
U3101 voltages.
Ye s
Check for 
5VDC
Is 9V3 
present?
Check Supply Voltage 
circuitry. Check Q0681, 
U4211 and U0641.
No
No
No
Check U4501. 
Check varactor filter.
NoYe s
Ye s
Ye s
A
A
B
weak RFRF
Signal at 
C4009? 
						

							Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3) 3-3
2.0 Troubleshooting Flow Chart for 25W Transmitter (Sheet 1 of 3)
Current 
increase 
when keyed?
NO YES
START
Check if Pressure Pad closes S5440
Check Components between 
Q4441 and RF Output, 
Antenna Switch 
D4471,D4472,Q4472, >500mA & 4A
1V
Short TP4403 to 
Ground
NO
YES
Voltage at 
TP4402 
rises?Check PA StagesNO
YES
PCIC U4501 
Pin 14 9.3V 
DC?Check 9.3 V Regulator 
U0641
NO
YESPCIC U4501 
Pin 16 >4V 
DCReplace PCIC U4501
NO
YESTP4404  
9.1V DC
If U4201 Pin 2 is high,  
replace PCIC 
U4501,otherwise 
check controller and 
FGU
YES
NOTP4403 
>0.5V DC?Replace PCIC U4501
Check Forward Power 
Sense Circuit (D4451)
Check Forward Power 
Sense Circuit (D4451)
NO
YESPCIC U4501 
Pin 5 > 1V 
DC?
Check Power Setting, 
Tuning & Components 
between PCIC Pin 5 
and ASFIC (U0221) 
Pin 4 before replacing 
ASFIC
No or too low Power when keyed 
						

							3-4TROUBLESHOOTING CHARTS
2.1Troubleshooting Flow Chart for 25W Transmitter (Sheet 2 of 3)
Check PA Stages
No or too low Power when keyed
Measure DC Voltage at Pin 2 & 3 of U4401>6 YESDC Voltage 
at U4501 
Pin 23 =0?
2-6DC Voltage 
at U4402-1 
Pin 1?
YESPin 2
Voltage 0.62 
* Voltage at 
Pin 1?
If U4201 Pin 2 is high,  
replace PCIC
NOReplace U4401
YES NODC 
Voltage at 
U4402-1 Pin 
3 = 8.8V?
Check S4440, 
R4442 and R4443
YESPin 3 
Voltage 0.51 
* Voltage at 
Pin 1?
NOReplace U4401
6V
Check Components 
between U4402-2 Pin7 
and Q4421. Check 
Resistive Network at 
Pins 5 & 6 before 
replacing Q4421
YESDC 
Voltage at 
U4402-2 Pin 5