Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual
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1-1 Section 1 MODEL CHART AND TECHNICAL SPECIFICATIONS 1.0 GM338 Model Chart GM Series, Low Band Model Description AZM25BKF9AA5GM338 29.7-36.0 MHz 40-60W AZM25CKF9AA5 GM338 36.0-42.0 MHz 40-60W AZM25DKF9AA5GM338 42.0-50.0 MHz 40-60W Item Description X X X GCN6114_ Preferred Control Head Direct Mount XIMUB6000_Tanapa WM 29.7-36.0 MHz 40-60W X IMUB6001_ Tanapa WM 36.0-42.0 MHz 40-60W XIMUB6002_Tanapa WM 42.0-50.0 MHz 40-60W X RAB4002 Low Band 29.7-36.0 MHz, 1/4 Wave Base Loaded XRAB4003Low Band 36.0-42.0 MHz, 1/4 Wave Base Loaded X RAB4004 Low Band 42.0-50.0 MHz, 1/4 Wave Base Loaded XXX6804112J06GM338 User Guide x = Indicates one of each is required.
1-2Technical Specifications 2.0 Technical Specifications Data is specified for +25°C unless otherwise stated. General Specifications Channel Capacity GM338 128 Power Supply 13.2Vdc (10.8 - 15.6Vdc) Dimensions: H x W x D (mm) Depth excluding knobsGM338 60mm x 179mm x 250mm (45 - 60W) Weight GM338 2064 g Sealing:Withstands rain testing per MIL STD 810 C/D /E and IP54 Shock and Vibration: Protection provided via impact resistant housing exceeding MIL STD 810-C/D /E Dust, Salt & FogProtection provided via environment resistant housing exceeding MIL STD 810 C/D /E
Technical Specifications1-3 *Availability subject to the laws and regulations of individual countries.Transmitter Low Band *Frequencies - Full Bandsplit Low Band 1 29.7-36.0 MHz Low Band 2 36.0-42.0 MHz Low Band 3 42.0-50.0 MHz Channel Spacing12.5/20/30 kHz Frequency Stability (-30°C to +60°C, +25° Ref.)±5 ppm Power 40-60W Modulation Limiting±2.5 @ 12.5 kHz ±5.0 @ 20/30 kHz FM Hum & Noise-40 dB @ 12.5kHz -45 dB @ 20/30kHz Conducted/Radiated Emission -26 dBm 70dB (1-25W model only) Adjacent Channel Selectivity 65 dB @ 12.5 kHz 80 dB @ 20/30 kHz Spurious Rejection 70 dB @ 12.5 kHz 80 dB @ 20/30 kHz Rated Audio7.5W and 13W External Audio Distortion @ Rated Audio
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2-1 Section 2 THEORY OF OPERATION 1.0 Introduction This Chapter provides a detailed theory of operation for the Low Band circuits in the radio. For details of the theory of operation and troubleshooting for the the associated Controller circuits refer to the Controller Section of this manual. 2.0 Low Band Receiver 2.1 Receiver Front-End The low band receiver, shown in Figure 2-1, is bandsplit into three ranges depending on radio model, covering frequencies from 29.7 to 36.0 MHz, 36.0 to 42.0 MHz, or 42.0 to 50.0 MHz. The circuitry of the three models is identical except for component value differences. The receiver consists of five major blocks: front-end bandpass filters and pre-amplifier, first mixer, high-IF and blanker switches, low-IF and receiver back-end, and “Extender” (noise blanker). Two fixed-tuned bandpass filters perform antenna signal pre-selection. A cross over quad diode mixer converts the signal to the high-IF of 10.7 MHz. High-side first injection is used. Figure 2-1 Low Band Receiver Block Diagram Demodulator Delay Filter Mixer Fixed Tuned Filter RF Amp Tuned Filter Pin Diode Antenna Switch RF Jack Antenna First LO RXINJ Recovered Audio RSSI IF Second LO Crystal Filter 455kHz Filter455kHz Filter 455kHz Filter (12.5kHz)455kHz Filter (12.5kHz)SwitchSwitchSwitchSwitch Limiter IF Amp IF Amp Filter Bank Selection from Synthesizer IC BlankerNoise Blanking Pulses GateBuffer Enable 1st Fixed (25/20kHz) BWSELECT (U1201 Pin 48)4-pole(25/20kHz)
2-2Low Band Receiver There are two 2-pole 10.7 MHz crystal filters in the high-IF section and two switched pairs of 455 kHz ceramic filters in the low-IF section to provide the required adjacent channel selectivity.The second IF at 455 kHz is mixed, amplified and demodulated in the IF IC. The processing of the demodulated audio signal is performed by an audio processing IC located in the controller section. 2.2 Front-End Band-Pass Filters and Pre-Amplifier The received signal from the radio’s antenna connector is first routed through the harmonic filter and antenna switch, which are part of the RF power amplifier circuits, before being applied to the receiver 5-pole antenna filter (L1001-L1005 and associated components). This filter configuration provides more rapid attenuation above the passband to provide better rejection of the half-IF spurious response. A dual hot carrier diode (D1001) limits any inband signal to 0 dBm to prevent damage to the RF pre-amplifier. The RF pre-amplifier is an SMD device (Q1001) with collector-base feedback to stabilize gain, impedance, and intermodulation. Transistor Q1002 compares the voltage drop across resistor R1005 with a fixed base voltage from divider R1006 and R1007, and adjusts the base current of Q1001 as necessary to maintain its collector current constant at 25 mA. Operating voltage is from the regulated 9.3V supply (9V3). During transmit, 9.1 volts (9T1) turns on both transistors in U1001, turning off Q1003 and therefore Q1001-2. This protects the RF pre-amplifier from excessive dissipation during transmit mode. A second 5-pole fixed-tuned bandpass filter provides additional filtering of the amplified signal. This filter configuration also provides steeper attenuation above its passband for best half-IF attenuation. 2.3 First Mixer and High Intermediate Frequency (IF) The signal coming from the front-end is converted to the high-IF frequency of 10.7 MHz using a cross over quad diode mixer (U1051). The high-side injection signal (RXINJ) from the frequency synthesizer circuitry is filter by a 7-pole low-pass filter (L1012-14 and associated circuitry) which removes second harmonic content from the injection signal and improves half-IF rejection. The 50- ohm output of the first mixer is applied to the input of the high-IF circuit block. 2.4 High Intermediate Frequency (IF) and Blanker Switches T h e f i r s t m i x e r I F o u t p u t s i g n a l ( I F ) i s a p p l i e d t o d i p l e x e r n e t w o r k c o n s i s t i n g o f L 11 0 1 , L 1111 a n d associated components. This network has three functions: it terminates the mixer output at frequencies other than 10.7 MHz into 51-ohm resistor R1101; it matches the 50-ohm mixer output to the first IF amplifier (Q1101) input; and it provides bandpass filtering at 10.7 MHz to prevent the 5.35 MHz half-IF component of the mixer output from creating a second harmonic at 10.7 MHz in Q1101, which degrades half-IF rejection. The IF amplifier Q1101 uses ac and dc feedback to stabilize gain and quiescent current (approximately 28 mA). Operating voltage is from the regulated 9.3V supply (9V3). Its output is applied to a 10.7 MHz ceramic filter FL1101 which has a 3 dB bandwidth of 270 kHz and provides a time delay of 2.6 usec. This delay allows enough time for the “Extender” to respond to impulse noise present at the input of Q1101 and operate the blanker switches Q1102 and Q1103, muting the IF signal for the duration of the noise pulse. L1104 and L1105 also provide additional selectivity and time delay. Operation of the “Extender” circuit is explained in Section 1.0.5 below. When the blanker switches turn “on” to mute the IF signal, they momentarily change the impedance of resonant circuits L1104 and L1105 from high to very low. This abrupt impedance change, if
Low Band Receiver2-3 presented to the high-Q crystal filter FL1102, would cause ringing of the filter response, stretching an otherwise narrow impulse into a long and audible output waveform. Therefore, source follower stage Q1104 isolates the blanker switches from the crystal filters, providing a consistent source impedance via matching network L1106, L1107 and associated components. Q1104 has unity voltage gain in this configuration. Crystal filter F1102 is a module which consists of two 2-pole, 10.7 MHz units configured to provide an overall 4-pole response having a 3 dB bandwidth of approximately 12 kHz. The output is amplified by second IF amplifier Q1106 and applied to the low-IF circuitry, pin 1 of IF IC (U1103). A dual hot carrier diode (D1101) limits the amplifier output voltage swing to prevent overdriving the IF IC at RF input levels above -27 dBm. 2.5 Low Intermediate Frequency (IF) and Receiver Back End The 10.7 MHz high-IF signal from the second IF amplifier feeds the IF IC (U1103) at pin 1. Within the IF IC, the 10.7 MHz high-IF signal mixes with the 10.245 MHz second local oscillator (2nd LO) to produce the low-IF signal at 455 kHz. The 2nd LO frequency is determined by crystal Y1101. The low-IF signal is amplified and filtered by external pairs of 455 kHz ceramic filters (FL1105 and FL1107 for 20kHz channel spacing, or FL1104 and FL1106 for 12.5 kHz channel spacing). Selection of the appropriate filter pair is accomplished by U1101 and U1102, controlled by the BWSELECT line from pin 48 of the synthesizer IC U1201. The filtered output from the ceramic filters is applied to the limiter input pin of the IF IC (pin 14). The IF IC contains a quadrature detector using a ceramic phase-shift element (Y1102) to provide audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60% deviation) from U1103 pin 8 (AUDIOOUT) which is fed to the ASFIC_CMP (U0221) pin 2 (part of the Controller circuitry). A received signal strength indicator (RSSI) signal is available at U1103 pin 5, having a dynamic range of 70 dB. The RSSI is interpreted by the microprocessor (U0101 pin 63) and in addition is available at accessory connector J0501-15. 2.6“Extender” (Noise Blanker) The 10.7 MHz output from the first mixer, which is present at the input of the first IF amp Q1101, is also routed to the input of the “Extender” (noise blanker) circuitry and amplified by FET Q1610. The high input impedance of the FET stage minimizes loading of the signal in the receiver path. The output of Q1610 is further amplified by U1601, which is a wide-bandwidth, high gain differential amplifier (used in a single-ended configuration) incorporating an AGC gain control input. This gain block provides linear amplification of the instantaneous amplitude of the 10.7 MHz signal at the first mixer output. The output of U1601 is coupled to biased-detector Q1603. The bias is set so that noise impulses of a significant amplitude cause Q1603 to conduct. The following stages (Q1604 through Q1606) provide additional gain and pulse shaping which slows the turn-on and turn-off waveform applied to IF blanker switches Q1102 and Q1103. The result is that, for each noise impulse, the IF signal is smoothly ramped off and then on again, preventing the pulse from reaching the narrow IF selectivity, where ringing would cause an objectionable spike at the detector of a much longer duration than the original impulse. If the repetition rate of noise impulses is so rapid that the noise blanker can no longer blank them individually, as indicated by a large increase in high-frequency content at the output of Q1604, stage Q1607 amplifies this level and turns on level detector Q1609. Its output is highly filtered into a DC voltage level which is proportional to the repetition rate of noise impulses, and this is applied to the
2-4Transmitter Power Amplifier (PA) 60 W AGC input pin 5 of U1601, reducing its gain and therefore the amount of noise pulses which are detected and processed. 3.0 Transmitter Power Amplifier (PA) 60 W The radio’s 60W power amplifier (PA), shown in Figure 2-2, is a three-stage amplifier used to amplify the output from the VCO to the radio transmit level. The line -up consists of three stages which utilize LDMOS technology. The first stage is pre-driver (U1401) that is controlled by pin 4 of PCIC (U1503) via Q1504 and Q1505 (CNTLVLTG). It is followed by driver stage Q1401, and final stage utilizing two devices (Q1402 and Q1403) connected in parallel. Q1402 and Q1403 are in direct contact with the heat sink. To prevent damage to the final stage devices, a safety switch has been installed to prevent the transmitter from being keyed with the cover removed. Figure 2-2 Low Band Transmitter Block Diagram 3.1 Power Controlled Stage The first stage (U1401) is a 20dB gain integrated circuit containing two LDMOS FET amplifier stages. It amplifies the RF signal from the VCO (TXINJ). The output power of stage U1401 is controlled by a DC voltage applied to pin 1 from the power control circuit (U1503 pin 4, with transistor Q1504-5 providing current gain and level-shifting). The control voltage simultaneously varies the bias of two FET stages within U1401. This biasing point determines the overall gain of U1401 and therefore its output drive level to Q1401, which in turn controls the output power of the PA . Pin Diode Antenna Switch RF JackAntennaHarmonic Filter PA - F i n a l StagePADriver From VCOControlled Stage BIAS To Microprocessor Te m p e r a t u r e Sense DC AMP PA S U P LV LT G(2 Lines) SPI Bus TXINJ Sense Current Sense Current ASFIC_CMPPCICINT 24 4295 6 BIAS Power Power Adjust
Transmitter Power Amplifier (PA) 60 W2-5 3.2 Driver Stage The next stage is an LDMOS device (Q1401) providing a gain of 13dB. This device requires a positive gate bias and a quiescent current flow for proper operation. The voltage of the line MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q1401 via resistors R1402, R1447, R1449, R1458, R1459, and R1463. The bias voltage is tuned in the factory. The circuitry associated with U1402-2 and Q1404 limits the variation in the output power of the driver stage resulting from changes in the input impedance of the final stage due to changes at the antenna of the radio. The variation in the driver’s output power is limited by controlling its DC current. The driver’s DC current is monitored by measuring the voltage drop across current-sense resistors R1473-6, and this voltage is compared to a reference voltage on pin 6 of U1402-2. If the current through the sense resistors decreases, the circuit increases the bias voltage on the gate of Q1401 via Q1404. If the current increases, then the bias voltage decreases in order to keep the driver’s current constant. Since the current must increase with increasing control voltage, an input path is provided to U1402-2 pin 5 from control line VCNTRL to enable this. 3.3 Final Stage The final stage uses two LDMOS FET devises operating in parallel. Each device has its own adjustable gate bias voltage, MOSBIAS_2 and MOSBIAS_3, obtained from D/A outputs of the ASFIC. These bias voltages are also factory-tuned. If these transistors are replaced, the bias voltage must be tuned using the Tuner software. Care must be taken not to damage the device by exceeding the maximum allowed bias current. The device’s drain current is drawn directly from the radio’s DC supply voltage input, PASUPVLTG, via current-measurement resistor R1409. A matching network combines the output of the two devices and provides a 50-ohm source for the antenna switch and harmonic filter. 3.4 Antenna Switch The antenna switch is operated by the 9T1 voltage source which forward biases diodes D1401 and D1402 during transmit, causing them to appear as low impedance. D1401 allows the RF output from final stages Q1402 and Q1403 to be applied to the input of the low-pass harmonic filter (L1421-3 and associated components). D1402 appears as a short circuit at the input of the receiver (RXINJ), preventing transmitter RF power from entering the receiver. L1420 and C1456 appears as a broadband-wave transmission line, making the short circuit presented by D1402 appear as open circuit at the junction of D1401 and the harmonic filter input. During receive mode, the 9T1 voltage is not present, and D1401 and D1402 do not conduct and appear as open circuits. This allows signals from the antenna jack to pass to the receiver input, and disconnects the transmitter final stages from this path. 3.5 Harmonic Filter Components L1421- L1423 and C1449-C1455 form a seven-pole elliptic low-pass filter to attenuate harmonic energy of the transmitter to specifications level. R1411 is used to drain electrostatic charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF signals above the receiver passband from reaching the receiver circuits, improving spurious response rejection.
2-6Transmitter Power Amplifier (PA) 60 W 3.6 Power Control The transmitter uses the Power Control IC (PCIC, U1503) to control the power output of the radio. A differential DC amplifier U1502-1 compares the voltage drop across current-measuring resistor R1409, which is proportional to the transmitter final stage DC current, with the voltage drop across resistors R1508 and R1535, which is proportional to the current through transistor Q1503. This transistor is controlled by the output of the differential amplifier, which varies the transistor Q1503. This transistor is controlled by the output of the differential amplifier, which varies the transistor current until equilibrium of the two compared voltages is reached. The current through Q1503 develops a voltage across R1513 which is exactly proportional to the DC current of the final stages. This voltage is applied to the RF IN port of the PCIC (pin 1). The PCIC has internal digital to analog converters (DACs) which provide a reference voltage of the control loop. The reference voltage level is programmable through the SPI line of the PCIC. This reference voltage is proportional to the desired power setting of the transmitter, and is factory programmed at several points across the frequency range of the transmitter to offset frequency response variations of the transmitter’s power detector circuitry. The PCIC provides a DC output voltage at pin 4 (INT) which is amplified and shifted in DC level by stages Q1504 and Q1505. The 0 to 4 volt DC range at pin 4 of U1503 is transferred to a 0 to 8 volt DC range at the output of Q1505, and applied as VCNTRL to the power-adjust input pin of the first transmitter stage U1401. This adjusts the transmitter power output to the intended value. Variations in antenna impedance cause variations in the DC current of the final stages, and the PCIC adjust the control voltage above or below its normal value to reduce power if current drain increases, or raise power if current drain decreases. Capacitors C1503-4 and C1525, in conjunction with resistors and integrators within the PCIC, control the transmitter power-rise (key-up) and power-decay (de-key) characteristic to minimize splatter into adjacent channels. U1501 is a temperature-sensing device which monitors the circuit board temperature in the vicinity of the transmitter circuits and provide a dc voltage to the PCIC (TEMP, pin 29) proportional to temperature. If the DC voltage produced exceeds the set threshold in the PCIC, the transmitter output power will be reduced so as to reduce the transmitter temperature. 3.7 TX Safety Switch The TX Safety Switch consists of S1501, Q1506, and diode pairs D1502 and D1503 providing protection to the final stage divices Q1402 and Q1403. These final stage devices can be degraded or destroyed if the radio is keyed without the cover in place due to the lack of a good thermal path to the chassis. Switch S1501 is closed when the radio’s cover is screwed in place by means of the carbonized reqion on the cover’s pressure pad making contact with the finger plating on the radio’s PCB. With the cover in place, transistor Q1506 is off, back-biasing diodes D1502 and D1503, enabling proper transmitter operation. When the cover is not in place, S1501 opens, causing Q1506 to rurn on, pulling the cathodes of D1502 and D1503 to ground, resulting in the shorting of the transmitter’s bias lines and control voltage.