Motorola Gm328 Gm338 Gm398 Detailed 6804112j18 E Manual

							Frequency Synthesis2-7
4.0 Frequency Synthesis
The frequency synthesizer subsystem, shown in Figure 2-3, consists of the reference oscillator 
crystal (Y1201), the Low Voltage Fractional-N synthesizer (LVFRAC-N, U1201), and the receive and 
transmit VCOs and buffers (Q1303 through Q1308 and associated components).
Figure 2-3 Low Band Synthesizer Block Diagram
4.1 Fractional-N Synthesizer 
The LVFRAC-N synthesizer IC (U1201) consists of a reference oscillator, pre-scaler, a 
programmable loop divider, control divider logic, phase detector, a charge pump, A/D converter for 
low frequency digital modulation, a balance attenuator to balance the high frequency analog 
modulation and low frequency digital modulation, a 13V positive voltage multiplier, a serial interface 
for control, and finally a super filter for the regulated 9.3 volt supply.
Regulated 9.3 volts DC applied to the super filter input (U1201, pin 30) delivers a very low noise 
output voltage of 8.3 volts DC (VSF) at pin 28. External device Q1201 allows greater current 
sourcing capability. The VSF source supplies the receive and transmit VCOs and first buffer stages. 
The synthesizer IC supply voltage is provided by a dedicated 5V regulator (U1250) to minimize 
power supply noise.
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin 
VCP (U1201 pin 47), a capacitive voltage multiplier circuit (CR1202 and C1209) generates a voltage 
DATA
CLK
CEX
MODIN
SFIN
XTAL1
XTAL2
WARP
PREIN
VCP
REFERENCE
OSCILLATOR
 VOLTAGE
MULTIPLIER
DATA (U0101 PIN 100)
CLOCK (U0101 PIN 1)
CSX (U0101 PIN 2)
MOD IN (U0221 PIN 40)
9,3V (U641 PIN 5)7
8
9
10
 30
23
24
25
32
47
VMULT2 VMULT1BIAS1 SFOUTAUX3 AUX4 IADAPTIOUTGND FREFOUTLOCK4
19
6, 22, 33, 44
43
45
3
2
28
       14
 1540FILTERED 8,3VSTEERING LOCK (U0101 PIN 56)
PRESCALER INFREF (U0221 PIN 34)
39 BIAS2
41
 48 5, 13, 20, 34, 36
+5V (U3211 PIN 1)
AUX1 VDD, DC5VMODOUT U1201 
LOW VOLTAGE
FRACTIONAL-N
SYNTHESIZER
AUX2
TX RF INJECTION
(1ST STAGE OF PA)LO RF INJECTION
VOLTAGE 
CONTROLLED 
OSCILLATORLINE
2-POLE
LOOP
FILTER1
Q1202
BUFFERBWSELECT
VCTRL
N.C.
N.C. 
						

							2-8Frequency Synthesis
of 13 volts DC. This multiplier is driven by two 1.05 MHz clock signals from U1201 pins 15 and 14 
(VMULTI1 and VMULTI2) which are 180 degree out of phase.
Output LOCK (U1201-4) provides information about the lock status of the synthesizer loop. A high 
level at this output indicates a stable loop. A buffered output of the 16.8 MHz reference frequency is 
provided at pin 19.
The operating frequency of the synthesizer is loaded serially from the microprocessor via the data 
line (DATA, U1201-7), clock line (CLK, U1201-8) and chip select line (CSX, U1201-9).
The reference oscillator circuit within U1201 uses an external 16.8 MHz crystal (Y1201). Varactor 
CR1201 allows software-controlled frequency adjustments (warp) and temperature compensation of 
the oscillator frequency. Warp adjustment is performed using serial data from the microprocessor. 
This controls the setting of an A/D converter, with its output (WARP, pin 25) applied to CR1201.
4.2 Voltage Controlled Oscillator (VCO) and Buffers
Separate voltage controlled oscillator (VCO) and buffer circuits, shown in Figure 2-4, are used for 
receiver injection and transmitter carrier frequency generation. Since the receiver uses high-side 
injection, the receiver VCO frequency range is 10.7 MHz above the transmit VCO range. The VCO/
buffers are bandsplit into three ranges depending on radio model, covering radio operating 
frequencies of 29.7 to 36.0 MHz, 36.0 to 42.0 MHz, or 42.0 to 50.0 MHz. The corresponding three 
frequency ranges from the receive VCO are 40.4 to 46.7 MHz, 46.7 to 52.7 MHz, and 52.7 to 60.7 
MHz. 
Figure 2-4 Low Band VCO Block Diagram
STEERINGLINE
(VCTRL)RXVCO
Q1303
Q1306 TXVCOAGC 
AGC Q1304
Q1307 Q1308Q1305 BUFFER BUFFER
BUFFER
BUFFER1ST RX
2ND RX
2ND TX
1ST TX
TXINJ RXINJ
TO Q1202
PRESCALER BUFFER(TO 1ST MIXER)
(TO U1401 PIN16)
SFOUT
(U1201 PIN28)U1377-8
DC SWITCH
RX (TO Q1303-5)
TX (TO Q1306-8)
(U1201 PIN2)
~
~ 
						

							Frequency Synthesis2-9
The VCOs, together with Fractional-N synthesizer U1201, generates the required frequencies for 
transmit and receive modes. The TRB line (U1201, pin 2) determines which VCO/buffer circuit is to 
be enabled. A high level on TRB will turn on the transistors in U1378 to turn on via R1376, applying 
the 8.3 volt VSF source to the receiver VCO and first buffer. The second buffer in each string 
operates from the 9V3 source and become active when RF is applied to their inputs. 
The RF signal at the bases of the second buffers are combined and fed back to the Fractional-N 
synthesizer via PRE_IN where it is compared to the reference frequency as described below in 
“Synthesizer Operation”. The Fractional-N IC provides a DC steering voltage VCTRL to adjust and 
maintain the VCO at the correct frequency.
With a steering voltage from 2.5V to 11V at the appropriate varactor diode (CR1302 for the RX 
VCO, or CR1310 for the TX VCO), the full VCO tuning range is obtained. Each VCO uses and AGC 
circuit to maintain a constant VCO output level across the frequency band. A diode (CR1306 in the 
receive VCO, or CR1314 in the transmit VCO) is configured as a voltage doubler which rectifies the 
RF level sampled at the VCO drain and applies a proportional negative DC voltage to the VCO gate. 
Increased RF level reduces the VCO gain to compensate.
The VCO output is taken from the source and applied to the first buffer transistor (Q1304 receive, 
Q1307 transmit). The first buffer output is further amplified by the second buffer transistor (Q1305 
receive, Q1308 transmit) before being applied to the receiver first mixer or transmitter first stage 
input.
In TX mode the modulation signal coming from the LVFRAC-N synthesizer IC (MODOUT, U1201 
pin 41) is superimposed on the DC steering line voltage by capacitive divider C1215, C1208 and 
C1212, causing modulation of the TX VCO using the same varactor as used for frequency control.
4.3 Synthesizer Operation
The complete synthesizer subsystem comprises mainly of low voltage LVFRAC-N synthesizer IC, 
Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop 
filter circuitry, and voltage controlled-controlled oscillators and buffers. A sample of the VCO 
operating signal PRE_IN is amplified by feedback buffer Q1202, low-pass filtered by L1205, C1222 
and C1224, and fed to U1201 pin 32 (PREIN).
The pre-scaler in the synthesizer (U1201) is basically a dual modulus pre-scaler with selectable 
divider ratios. The divider ratio of the pre-scaler is controlled by the loop divider, which in turn 
receives its inputs via the serial interface to the microprocessor. The output of the pre-scaler is 
applied to the loop divider. The output of the loop divider is connected to the phase detector, which 
compares the loop divider´s output signal with the reference signal.The reference signal is 
generated by dividing down the signal of the reference oscillator, whose frequency is controlled by 
Y1201.
The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump. 
The charge pump outputs a current at pin 43 of U1201 (IOUT). The loop filter (consisting of R1205-
6, R1208, and C1212-14) transforms this current into a voltage that is applied to varactor diodes 
(CR1310 for transmit, CR1302, for receive) and alters the output frequency of the appropriate 
VCO.The current can be set to a value fixed in the LVFRAC-N IC or to a value determined by the 
currents flowing into BIAS 1 (U1201-40) or BIAS 2 (U1201-39). The currents are set by the value of 
R1211 or R1207 respectively. The selection of the three different bias sources is done by software 
programming. 
						

							2-10Frequency Synthesis
To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the 
magnitude of the loop current is increased by enabling the IADAPT (U1201-45) for a certain 
software programmable time (Adapt Mode). The adapt mode timer is started by a low to high 
transient of the CSX line. When the synthesizer is within the lock range, the current is determined 
only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled 
synthesizer loop is indicated by a high level of signal LOCK (U1201-4).
In order to modulate the PLL the two-spot modulation method is utilized. Via pin 10 (MODIN) on 
U1201, the audio signal is applied to both the A/D converter (low frequency path) and the balanced 
attenuator (high frequency path). The A/D converter converts the low frequency analog modulating 
signal into a digital code that is applied to the loop divider, thereby causing the carrier to deviate. 
The balance attenuator is used to adjust the VCO’s deviation sensitivity to high frequency 
modulating signals. The output of the balance attenuator is present at the MODOUT port (U1201-
41) and superimposed on the VCO steering line voltage by a divider consisting of C1215, C1208 
and C1212. 
						

							3-1
Section 3
TROUBLESHOOTING CHARTS
1.0 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2) 
Bad SINAD
Bad 20dB Quieting
No Recovered AudioSTART
Audio at pin 8 
of U1103?Check Controller (in the case of no audio).
Or else go to “B” Ye s
No
Spray or inject 10.7MHz 
into XTAL Filter FL1102.
Audio heard?BYe s
No
Check 2nd LO 
(10.245MHz) at C1129. 
LO present?BYe s
 Check volt-
ages on 
U1103. OK?
Biasing OK?
No
No
A
Ye s
Check Q1106 bias 
for faults.
Replace Q1106.
Go to B
Ye s
No
Check cir-
cuitry around 
U1103. 
Replace 
U1103 if 
defect.
Check circuitry around Y1101. 
Replace Y1101 if defect. 
						

							3-2 Troubleshooting Flow Chart for Receiver (Sheet 1 of 2)
1.1Troubleshooting Flow Chart for Receiver (Sheet 2 of 2)
IF Signal at 
pin 2 of 
U1051
No
RF Signal 
at pin 3 of 
U1051?
RF Signal at 
C1017?
No
RF Signal at 
C1013?
No
RF Signal at 
C1002?
No or 
Check harmonic filters J1401 and ant.switch 
Check preselector and RF 
amp.
Inject RF into J1401
No
Ye s
Check RF amp (Q1001) 
Stage.
Check filter between C1017 
& mixer U1051
Ye s
Check for detailed mixer.
Ye s
1st LO level 
OK?
Locked?Ye s
Check FGU
Ye s
Trace IF signal from 
C1036 to Q1106. 
Check for bad 
XTAL filter.
No
Ye sIF signal at 
Q1106 collec-
tor?
Before replacing 
U1103, check 
U1103 voltages.
Ye s
Is 9V3 present?
Check Supply Voltage cir-
cuitry. Check U0681, 
U3211 and U0641.
No
No
Ye s
A
B
weak RF 
						

							Troubleshooting Flow Chart for Transmitter3-3
2.0 Troubleshooting Flow Chart for Transmitter  
No
 DC Voltage
@ Gate of
Q1401
NoYe s
              START
        No or Low 
  
  TX DC Voltage 
      @Drains of 
Q1402 &
Q1403
@ Cathode of 
D1401 &
D1402 DC Voltage
Drains of Q1402 &AC Voltages @
Q1403 both sine or
both distorted
Check 9T1 and
Diode Bias Circuit
Verify RF Continuity
   to gates of
Q1402 & Q1403
 
Check circuitry
between Q1402 &
Q1403 and 
Antenna Port
CheckMOSBIAS_1
Supply and
Feed Network
No
 1 A
Look for
   short on
Supply Line
Check Pressure Pad
and/or
Switch Circuitry
Ye sNo TX
Safefy
Switch 
						

							3-4Troubleshooting Flow Chart for Synthesizer
3.0 Troubleshooting Flow Chart for Synthesizer
5V
 at pin 6 of 
CR1202
Is information
from uP U0101
correct?
Is U1201 Pin 47
at = 13VDC
Is U1377, Pin 2
4.5 VDC in TX?  (at 
VCO section)
Start
Vi s u a l  
check of the 
Board OK?Correct
Problem
Check 9.3V
Regulator
U0641
+9.3V at 
U1201
Pin 30?
Is 16.8MHz
Signal at
U1201 Pin 19?
Check Y1201, C1204, 
C1206,C1207, 
CR1201. & R1203
Are signals
at Pin’s 14 &
15 of U1201?
Check 
R1218
Check C3319
Is U1201 pin 2>4.5 
VDC in Tx & 
						

							Troubleshooting Flow Chart for VCO3-5
4.0 Troubleshooting Flow Chart for VCO
LOW OR NO RF SIGNAL
           AT U1051
VISUAL CHECK
OF BOARD
OK?
8.5V DC AT 
U1378 PIN 3

						

							3-6Troubleshooting Flow Chart for VCO
THIS PAGE INTENTIONALLY LEFT BLANK