Yamaha Dx7 Service Manual

							DX7 CIRCUIT DESCRIPTION
1. Keyboard and Panel Switch Scanning
The 4 bits BO ~ B3 from the sub-CPU (6805S) are input to the decoder (40H138).
The decoder output is sent to the keyboard transfer contacts and the panel switches.
The on or off state of the keyboard break contacts, make contacts and panel switches are sent to
the sub-CPU AO  ~ A7 lines via a line driver (40H240) when the sub-CPU B4 and B5 lines are
low.
2. Key ON/OFF and Touch Data
The time it takes for the transfer contact to connect with the make contact after separating from
the break contact is recorded by the sub-CPU timer. This value is the Touch data.
The key ON signal is generated when the transfer contact connects with the make contact, and
the key OFF signal is generated when the transfer contact connects with the break contact.
3. ADC
Data entry
Pitch bend wheel
Modulation wheel
Foot controller
Breath controller
After-touch controller
Battery voltage
The 7 analog control voltages given above are fed to the ADC (M58990P-l). The analog input
selected by the sub-CPU BO~ B2 bits is converted to a digital value when the sub-CPU B7 line
goes low. The ADC outputs a high level to the sub-CPU C3 line when the conversion is complete.
The ADC sends the 8-bit digital value to the sub-CPU when the sub-CPU B6 line goes low.
4. Data Transmission from Sub-CPU to Main CPU
4-1. When a key event occurs the sub-CPU CO line goes high, changing the state of the
ready flag (R S F/F) causing the main CPU IRQ and P21 lines to go low.
4-2. The main CPU accepts one byte of data on lines AO~ A7 from the sub-CPU when
the P21 line goes low.
4-3. Once this byte is accepted, pin 9 of IC24 goes low, changing the state of F/F and
forcing the sub-CPU Cl line low.
4-4. When the sub-CPU Cl line goes low, step 4-1 (above) is repeated and then in step
4-2 a second byte of data is accepted by the main CPU.
4-5. During the IRQ routine the main CPU P20 line holds C2 on the sub-CPU line low
until the second byte has been transferred. 
						

							4-6. Data is not accepted from the panel switches and keys while the sub-CPU C2 line is
low.
5. Main CPU Operation
The main CPU mode is set by externally initializing lines P20~P22. When “L, L, H” is applied to
the P20~P22 lines and latched into the CPU on the rising edge of RES, the Extended Multiplex
Mode is selected.
In this mode, P40 ~ P47 function as address lines. The lower address bits are multiplexed with the
data on lines P30 ~ P37, and are separated by the address strobe signal SCI.
P20 ~ P24 and P10 ~ P17 function as I/O lines.
6. RAM
M5M511BP-15 X 8-bit CMOS RAM.
7. ROM
2764 8K X 8-bit NMOS EROM
8. LED
The LED display is created via software. The LEDs are lit by data latched from the
main CPU.    
						

							9. LCD
Data from the main CPU is decoded and displayed at the LCD unit.
10. EGS (Envelope Generator)
8 bits of data are received from the main CPU, and envelope and frequency data are
sent to OPS.
11. OPS (Operator)
The OPS uses a sine table to generate waveform data to be sent to the DAC from the
received envelope and frequency data.
The OPS permits combining the 6 operators in 32 different combinations. The combina-
tions are called “algorithms”. One of the 6 operators is able to feed the sine table output
back to the input. The feedback level and algorithm data is received from the main
CPU.
12. DAC
A BA9221 DAC is used. The DAC converts the digital waveform data from the OPS to an
actual analog waveform. The amplitude scale factor of the analog waveform is controlled
via SF0 ~  SF3. This signal is then fed to the sample & hold and low-pass filter circuits
from which it is sent to the output terminal. A reference voltage is applied to pin 14 of the
DAC.  8 reference voltages are generated by the muPD405 1, and the total level is exter-
nally controlled.
13. MIDI (Musical Instrument Digital Interface)
Permits data transfer with other devices. Data is received by P3 of the main CPU via a
photo-coupler, and data is output from main CPU pin P24.
EGS
1 EGS Functions
Receives data from the CPU, generates envelope & frequency data, & transmits the gener-
ated data to OPS.
(see EGS block diagram)
Data received from the CPU is latched in the EGS & sent to the internal data buss.
2 EGS Rate/Level Buffer
Rate refers to the time required for the next level to be reached. For example, Rl is the time