Yamaha Ysp1 Service Manual

							A
1
2
3
4
5
6
7
8
910BCDE FGH I J K
L
MN
YSP-1
SCHEMATIC DIAGRAM (DSP 1/2)
51
★All voltages are measured with a 10MΩ/V DC electronic volt meter.
★Components having special characteristics are marked s and must be replaced 
with parts having specifications equal to those originally installed.
★Schematic diagram is subject to change without notice.
Page 54
to AMP_CB3 to AMP_CB3
F2Page 54
to DSP_CB302 (
T, A, G, J models
)
G1
Page 54
F2 This part can not be supplied
\w
æ
¼xÍ”À™…`‡dœ

IC3 and IC4 can not be supplied. / 
*$t|*$xÍ”À™…`‡dœ{



This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ
This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

This part can not be supplied\w
æ
¼xÍ”À™…`‡dœ

POINT A-2 pin 3 of IC5
3.3
3.0
3.2
3.1
3.1
0
3.1
3.1
3.2
3.1
3.1
0
3.1
3.3
3.1
3.1
0
3.2
3.2
0
3.2
0
0
0
0
3.2
3.2
3.3
3.1
0
3.1
3.1
3.2
3.1
3.1
0
3.1
3.1
3.2
3.2
3.3
0
0
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.1
3.0
3.2
3.2
03.2
0
3.2
0 0
0
0
0
0
0
0
0
3.2
3.2
0
3.2
0
0
1.6
1.6
2.1
3.1
3.2
3.2
00
3.1
0
3.3
3.203.2
3.3
03.3
A-23.3 3.3
1.7
0 1.7 1.6 1.6
3.33.3
1.7
1.73.31.6
1.6
3.23.2
0 3.2
3.2
1.60
00
1.3
2.6
2.6
0
1.3
0 3.3
3.33.3
1.3
2.5 2.52.53.3
2.52.6
3.2 3.3 0000
0.9 3.3
2.8
3.3
3.3
3.3
0
0
0 0
0
2.6
2.6
2.6
2.6 0
1.33.3 3.3
3.3
3.33.3 3.3
3.3
3.3
2.8
3.3
3.3
3.3
0
0
0 1.3 3.3
0
1.3 1.3
1.3
1.3
1.3
03.0
0
3.03.3
3.3
0
3.3
0.1
3.3
0
3.03.21.6
1.6
1.6
3.1
3.1
3.2
3.1
0
3.1
3.1
3.2
3.1
0
3.2
3.2
0
0
0
0
0
0
0
3.2
0
3.1
3.2
3.2
3.0
0
3.0
3.0
3.2
3.2
3.1
0
3.1
0
L
SYNCHRONOUS
DRAMPWM
IC1: MT48LC2M32B2P-6
SYNCHRONOUS DRAMIC2: MBM29LV160BE-70
16M-bit, 3.0 V-only Flash memory
11
RAS#CAS#CLK
CS#WE#CKE
8 A0-A10,
BA0, BA1
DQM0-
DQM3
13
256
(x32)8192I/O GATING
DQM MASK LOGIC
READ DATA L ATCH
WRITE DRIVERSCOLUMN
DECODERBANK0
MEMORY
ARRAY
(2,048 x 256 x 32)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER2048
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0-
DQ31
32
32
D ATA
INPUT
REGISTERD ATA
OUTPUT
REGISTER
32
BANK1
BANK0BANK2BANK3
11
8
2
4
4
2
REFRESH
COUNTER11 11
MODE REGISTER
CONTROL
LOGIC
COMMAND
DECODE
ROW-
ADDRESS
MUX
ADDRESS
REGISTER
COLUMN-
ADDRESS
COUNTER/
LATCH
VDDDQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDDQM0
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10
A0
A1
A2
DQM2
VDDNC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
4386
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSSDQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSDQM1NCNC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSSNC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
2448
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25 A
15A14A13A12A11A10A9A8A19N.C.
WE
RESET
N.C.
N.C.
RY/BY
A18A17A7A6A5A4A3A2A1
A16BYTE
VSSDQ
15/A-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
VCCDQ
11
DQ
3
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
OE
VSSCE
A0
A-1
VSSVCCWE
CE
A
0 to A
19OEState
Control
Command
Register
Erase Voltage
GeneratorInput/Output
Buffer
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix DQ0 to DQ
15
Low V
CC DetectorProgram Voltage
Generator
Timer for
Program/Erase
Chip Enable
Output Enable
LogicData Latch
BYTERESET
RY/BY
Buffer
RY/BY
STB
STB
Address
Latch
I/O
Block
ORP ORP16
16
GOE0
GOE1
V
CC
GND
TCK
TMS
TDI
TDO
36 Generic
Logic
BlockGeneric
Logic
Block
I/O
Block
ORP ORP16
36 Generic
LogicBlockGeneric
Logic
Block
I/O
Block
I/O Bank 0
I/O Bank 1
I/O
Block
36 36
CLK0/I
CLK1/I
CLK2/I
CLK3/I
16 16
Global Routing Pool
VCCO0
GND
V
CCO1
GND
16 1616
IC6: LC4032V-75TN48C   
Complex Programmable Logic Device
T_SUNTBias UVLO
BG GOODDelay
VIN UVLO
Comparator
VIN
Falling
Edge
Delay
s
1–4
SS_DIS
VIN_UVLO
0.8 VEnable
Comparator
VIN
+
–
MUX
Error
AmplifierReference/DAC
SHUTDOWNPWM
Comparator
Rising
Edge
DelayRising
Edge
Delay
RQ
S
OSC
Ct
Iset
SS/ENA
SHUTDOWN
ILIM
Comparator
Deadtime
SHUTDOWN
Highin VI(LIM)
SamplingHighin HighdrSHUTDOWN
VPHASE
SHUTDOWN
Falling
Edge
Delay
SHUTDOWN
VSENSE
Vpgd
Powergood
Comparators
20–50
REG
UVLO
UVLO
VBIAS
VBIAS
VIN
BOOT
PHPWRGD
RT
SYNC
AGNDVSENSE
L(out)
CoVO
Logic
VIN
PGND
OffsetHighdr
1
2
3
4 
5
6
7
8
9
1020
19
18
17
16
15
14
13
12
11
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PHRT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
IC7, 8: TPS54310PWPR   
Low-input-voltage high-output-current synchronous-buck PWM converter
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLOCharge
Pump
CS
Thermal
Sense Power Switch
†
†
Current Sense
IC9: TPS2034D
POWER-DISTRIBUTION SWITCHES
1
2
3
4
5
6
714
13
12
11
10
9
8 1CLR
1D
1CLK
1PRE1Q
1QGNDVCC
2CLR
2D
2CLK
2PRE2Q
2Q
TGC
C
TGC
C
TGCC
C
TGC
C
PRECLK
D
CLR
Q
Q
C
IC5: SN74LVC74APWR
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS 
						

							A
1
2
3
4
5
6
7
8
910BCDE FGH I J K
L
MN
YSP-1
SCHEMATIC DIAGRAM (DSP 2/2)
52
★All voltages are measured with a 10MΩ/V DC electronic volt meter.
★Components having special characteristics are marked s and must be replaced 
with parts having specifications equal to those originally installed.
★Schematic diagram is subject to change without notice.
Page 53
to INPUT (2)_W10
I7 Page 53
to INPUT (2)_CB9
G7Page 53
to INPUT (3)_W11
F7
POINT A-1 pin 28 of IC300POINT C-1 pin 13 of IC304
A-1
C-1
0
0
0 3.3 3.3
3.3
3.2
3.3
3.3
3.3
3.3 1.5 3.3 0.4
0
0
0 4.3
3.3
4.1
3.3
3.3
3.3
3.3 0
0
0 1.7
1.7
1.7
1.6
1.6
0 3.3
3.2
3.4
0
0.1
3.2
3.3
3.4
1.6
0
0
0
0
0
0
0
0
0
0
0
0
0
3.2
3.2
0
0.1
3.2
0.1
0
0
0
0
0
3.3
0.1
3.3
0
3.2
0.1
3.2
3.23.3
3.3
3.2
3.3
0
0
1.6
0
0
3.3
3.3
3.3
3.2
3.2
3.2
1.4
0
1.6
3.2
3.2
3.2
0.1
0
3.2
0.1
0.9
0.1
3.2
3.2
3.2
3.3
0.13.4 3.2
0
3.3
3.3
3.3
3.3
2.3
3.4
3.3
3.3
3.3
3.3
0
0
3.2
0 03.2 0
0
0
1.3
1.3
1.3
0
0
0
0
0
1.3 1.3
~0
1.6 0
0
0
0
0
1.7
1.7
1.70
3.3
1.3
1.3
3.3
1.61.3
1.3
1.3 0 0
1.3
1.3
0 0
1.3
1.3
0 0
1.3
1.3
0
1.3
1.3
0
0
1.3
1.3
0
0 3.3
3.3
0
~
0
0
~
1.2
1.63.0
0
0 0 3.3
3.3
2.5
3.2
3.2
3.2
3.3 0
0
0
0
0
0
03.2
3.2
3.2 3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
0
3.3
3.2
0.5
3.2
3.3
3.2
~
0
0
0
0
~
~
1.2
2.5 1.6
1.6
~
~ 0.6
0
0 2.5
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.3
1.6
1.7 3.23.2
3.214.2
7.0
13.7
13.74.3
0 4.30
~
1.6
1.6
1.7
3.2
5.0
5.0
05.0
2.5
2.50 0.1
0.1
5.0
5.02.5
2.5
0
0 5.0
0
2.5
0
2.5
2.50
2.6
2.6 5.0 1.6
1.7
1.6
1.6
3.2
3.2
3.2
3.2
3.4
3.2
0.1
3.2
1.1
0
0
3.2
0
1.6
1.7
~
3.2
3.2
0 3.20
3.2
0
0
0 1.6
1.7
1.6
3.2 3.2
3.23.2
1.1
0
3.2
0
1.6
1.7
0.6
3.2
3.2
0 3.20
3.2
0
0
0 1.6
1.7
1.6
3.2 3.2
3.23.2
1.1
0
0
3.2
0
1.6
1.7
~
3.2
3.2
0 3.20
3.2
0
0
0 1.6
1.7
1.6
3.2 3.2
3.2
0
0
0 1.3
1.3
3.3
3.3
1.3
1.3
0
0
03.3
3.2
3.3
1.3
0
0
0 3.3
3.30.5
1.3
3.33.3 3.3
0
0
0
2.5
3.3
3.2
3.2
3.2
2.5 1.6
0.1
3.2
3.2
3.2
3.3
3.2
3.1
3.2
0
0
0 0
0
3.3 1.6
1.63.3 0
0 00
0.1
0.1 03.33.3
3.3
3.3
3.2
3.33.2
3.22.5
0
2.6
0.1
0
3.4
3.2
14.2
2.9
3.3
3.1
2.3
0
0.4
4.3
4.1
0.1
3.2
3.4
3.4
0.1
3.2
0.1
0.1
0.1
3.4
2.7 3.2
3.2
3.2
0.9
0.9
0.9 3.2
DIGITAL IN
SUBWOOFER OUT
ANALOG IN
100/6.3
1
7 4 3 2
5
68
DIR
MAIN DECODER
POST
PROSESSER CPUDAC
A/D
Key Input (A-D) Pull-Up Resistance 10 k-ohms
Ohm
V
ADKEY 0
94pin A/D2
ADKEY 0
95pin A/D1
0 k
~ 0.30
VOLUME
+
VOLUME
-+1.2 k
~ 0.70
INPUT
–
CSSK
DI
DO1
2
3
48
7
6
5VCC
NC
TEST
GND
IC303: S-29630AFJA
CMOS SERIAL EEPROM
Memory arrayAddress
decoder
Data registerOutput buffer
Mode decode logic
Clock generator
VCC
GND
DI
SK CS
DO
IC310: AK4381VT
192kHz 24Bit 2ch DAC
Audio
Data
InterfaceµP
Interface
CSN
De-emphasis
ControlClock
Divider
MCLK
CCLK
8X
Interpolator
ModulatorModulator
SCFSCF
8X
Interpolator
CDTI
AOUTL+VDD
VSS
AOUTL-AOUTR+AOUTR-
6
PDN5
1
78
LRCKBICKSDTI
423
91011121314DZFL
DZFR1516
IC312: NJM2068MD
Dual OP-Amp.
– +
OUT1–IN1–VCC
+VCCOUT2
1234
5
+IN1
–IN2+IN2
–+6 7 8
IC311: AK5381VT-E2
96kHz 24Bit ∆Σ A/D Converter
Serial I/O
InterfaceClock
DividerMCLK
AINL
Decimation
Filter
Modulator
SDTO
CKS13
CKS016
CKS215
PDN13
DIF1411
VA6
AGND5
VD7DGND8
2
AINR
Decimation
Filter
Modulator
1
VCOM
Voltage
Reference
4
9LRCK
SCLK1210
PDN
IDIF2 IDIF1 IDIF0 ODIF1 ODIF0 PDN
ILRCK
IBICK
AVSS
FILTDEM0 DEM1 SMUTE TVDD VDD DNSS
(MCLK)
SDTO
OLRCK
OBICK
CMODE2
CMODE1
CMODE0
De-em
filterSample
Rate
Convertersoft
mute
PLL Serial
Audio
I/FSerial
Audio
I/F
IC307-309: AK4121VF
Asynchronous Sample Rate Converter
FILT
AV S S
PDN
SMUTE
DEM0
MEM1
ILRCK
IBICK
SDTI
IDIF0
IDIF1
 IDIF2VDD
DVSS
TVDD
MCLK
OLRCK
OBICK
SDTO
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0 1
2
3
4
5
6
7
8
9
10
11
1224
23
22
21
20
19
18
17
16
15
14
13
IC305: YSS930-SZ
DSP
MICROPROCESSOR
INTERFACE
EXTERNAL RAM
INTERFACE
CONTROL REGISTER
SDBCKO MPLOAD
/CS
SO
SI
SCK
IOPORT19~0
CASN
RASNRAMWENRAMOEN
SDO0 SDI0
SDI1
SDI2
SDI3
SDI4
SDI5
SDI6
SDI7 SDBCK
SDWCK
XO
XI
CPOSDI  INTERFACE
SDO1SDO2SDO3SDO4SDO5SDO6SDO7
32 bit DSP Core
PLL DSP INTERNAL
OPERATING CLOCK
CK (30.72~40.96MHz)
COEFFICIENT
RAM16 bit Î1024
XPSE
PROGRAM
RAM50 bit Î1024
XPSE
ADDRESS
RAM17 bit Î256
XPSE
CONTROL
SIGNALS
RAMD15~0
RAMA17~0
BCKOPSDWCKOWCKOP
OVFEND
DATA RAM32 bit Î1024
XPSE
SDO  INTERFACE
ZEROF7R-0L
IC300: LC89057W-VF4-E
192kHz 24Bit 8ch DAC
Control
Register
10MCLK
3-wire
or 12C Audio
I/F
DAC
LOUT1+
DATT
SCF
PCM
17LRCK9BICK14SDTI115SDTI216SDTI313SDTI422DCLK25DSDL126DSDR127DSDL228DSDR229DSDL330DSDR323DSDL424DSDR4
DSD
2
LOUT1–
1
DAC
ROUT1+
DATT
SCF
SCF
SCF
48
ROUT1–
47
DAC
LOUT2+
DATT
46
LOUT2–
45
DAC
ROUT2+
DATT
44
ROUT2–
43
DAC
LOUT3+
DATT
SCF
42
LOUT3–
41
DAC
ROUT3+
DATT
SCF
40
ROUT3–
39
DAC
LOUT4+
DATT
SCF
38
LOUT4–
37
DAC
ROUT4+
DATT
SCF
33
ROUT4–
32
DZF
 
XI
XO
nIC
TEST
SDI3-0
SDIMCK
SDIBCK
SDIWCKnMUTE
ZEROFLG
nINT
STATUS7-0
SDO3-0
SDOMCK
SDOBCK
SDOWCK
MEMA18-0
MEMD7-0
nMEMWE
nMEMCE
nMEMOE
nMICS
MISI
MISCK
MISO
IOPORT7-0
ClkGen
SDI SDOMicomIF
PLL
EMS
Firmware download circuit Regiser
Format conversion
ZERO detectionDelay control
Delay control
Automatic muting
Detector
DSP
memory
User muting
Format conversion
Bypass
Output ch change
Decoder
Dividing/Switcing to each control section Internal operation clock
 Result of Status change detection
IC302: YSS948-VZ
Post Processor
1
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GNDVcc
OE
B1
B2
B3
B4
B5
B6
B7
B82345678910
20191817161514131211
IC301: SN74LV245APWR
Octal Bus Transceiver with 3-state Outputs 
						

							Page 52
to DSP_CB303
H1
Page 52
to DSP_CB300
B1
Page 52
to DSP_CB302
G1
Page 54
to AMP_CB7
K3 Page 54
to AMP_CB7
K3
1
2
3
4
5
6
7
816
15
14
13
12
11
10
9 C1+
V+
C1
C2+
C2
V
DOUT2
RIN2VCC
GND
DOUT1
RIN1
ROUT1
DIN1
DIN2
ROUT2
IC2: MAX3232CDWR
On Screen Display Controller
52
Display
controller
Segment
digit
select/
output
circuit
Serial
receive
circuit
Digit  
output
circuit Clock
generator
DIG11/
SEG4251DIG12/
SEG4150DIG13/
SEG4049DIG14/
SEG3948DIG15/
SEG3847DIG16/
SEG3746DIG17/
SEG3645SEG35
XOUT
6
Vcc1
8
Vcc2
18
Vss
5Vp64
XIN
7
CSSCK
3
S DATA
4
RESET
1
SEG00449SEG34 SEG261719SEG25
Segment
output
circuit
Display  code
RAM
(8-bit x 60)
CGROM
(35 bit x 166)
CGROM
(35 bit x 16)
code
select
Code
writeCode/
command
control 
circuit
DIG006353DIG10
IC1: M66003-0101FP
FL Display Driver
2
data
timing
clockdot data
write
scan pulse
POINT A-3 pin 3 of IC3POINT B-1
ƒ
Q14(E)
AC cable ON „ Q13(C)
AC cable ON
AC cable OFF
A
1
2
3
4
5
6
7
8
910BCDE FGH I J K
L
MN
YSP-1
SCHEMATIC DIAGRAM (INPUT)
53
★All voltages are measured with a 10MΩ/V DC electronic volt meter.
★Components having special characteristics are marked s and must be replaced 
with parts having specifications equal to those originally installed.
★Schematic diagram is subject to change without notice.
2.7
0.4
4.3
0
5.0
4.1
0
5.0
3.4
15.0
11.2
0.1
3.1
3.1
-25.5
-25.5
-25.5
-25.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.4
-22.4
-25.5
-20.9
-20.8
-16.1
-20.8
-22.4
-19.3
-22.4
-20.8
-20.8
-19.3
-17.7
22.4
-19.3
-22.4
-17.7
-17.7
-24.0
-20.8
-24.0
-17.6
-17.7
-24.0
-19.2
-24.0
-17.7
-17.7
-23.9
-20.8
-24.0
-17.6
-17.7
-17.7
-17.7
-17.7
-17.7
-18.0
-18.0
3.2 3.2 3.23.2
3.2 3.23.2 3.2
-17.7
-17.7 -20.8-17.8
-17.7-20.9-24.0
-17.7-23.9-24.4
-19.3
13.7
5.7
5.70.3
3.3 3.3 5.9
5.3 5.9
00 -17.7
-22.4-22.4
-19.3
-22.4
-17.7
-17.7
-24.0
-20.8
-24.0
-17.6
-17.7
-24.0
-19.2
-24.0
-17.7
3.2
-20.9
-20.9
-24.0
-17.6
-17.7
-17.7
-17.7
-17.7
-17.8
3.2
1.5
1.5
0
3.2
3.2
3.2
3.2 -20.8 -20.8
-20.8
-20.8
-20.8
-20.8
-20.8
-20.8
-20.9
-22.5
-22.5
-22.4
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-22.5
-25.5
-25.5
-25.5
-25.5
-17.7
-19.3
-22.4
-22.4-22.5-22.50.1 11.2
11.2
00
0 10.6
3.4
5.70
0
0.1
0 -5.7 -5.50
3.4
3.2
0.1
3.4
-5.5
-5.5
3.25.0
07.8
7.8
7.87.8
7.8 7.814.1
0
5.0
2.0
5.0
0
0
1.9
0 2.6
1.9
5.0
000
15.0
5.0
3.3
0 0
3.4
3.2
3.2
3.3
3.10 0
15.0
5.0
3.3
0
3.4
3.2
3.2
3.3
3.1 0
0
3.2 0
0
5.0
0 5.0 5.0 5.0
0
2.5
5.0
0
0
5.0 2.52.5 2.40
10.4
10.410.4
10.4 7.8
7.8
7.8
7.8 7.8
7.97.9
14.2
14.2
14.2 0
0
0
014.2 14.2
0
0
14.9
4.0
0
0 3.4
3.4
3.4
3.40 4.04.02.9
7.0
14.9
14.9
14.9
14.9
5.0
0
3.2
3.24.0
9.0
13.34.1
AC 8.2
4.1
4.0
3.9
0 12.7
0.1
0.8
00.1 12.6 4.0
13.313.4
13.4
9.0
3.2
6.76.3
6.3
0 00
0
00 4.05.015.0
15.0 -24.3 0 0 5.0
-24.33.3 3.31.1 0.8 0.8
0
3.4
0 7.0
4.0
7.8 7.9 7.8
8.4
8.48.48.4
8.4
A-3
B-1
1 2
VCRL
R
L
R
SUBWOOFER
OUT
SYSTEM
CONNECTORVIDEO
OUT
DV D AUDIO
INPUTTV
TV
RS-232CAUX  DIGITAL
INPUT
OPTICAL
ANALOG IN
DIGITAL IN
SUBWOOFER OUT
INPUT(1)
INPUT(5)
INPUT(2)
INPUT(3)
INPUT(4)
2
115
7
1114
12
13
1
2
5
11
9
10
7 3
6
8 8
5
6
1
4
14
15 510
2
14
1 8 963
2 5
34
114
10
3
OSD
FL DRIVER
IC26: TC4053BF
TRIPLE 2-CHANNEL MULTIPLEXER/DEMULTIPLEXER
X-COMMON
0X
1X
0Y
1Y
0Z
1Z
Z-COMMON
Y-COMMON 14
12
13
2
1
5
3
4
15
OUT   c   IN
OUT   c   IN
OUT   c   IN
OUT   c   IN
OUT   c   IN
OUT   c   IN
7 8 11
6 9 10 A
INHCB16 VDD
VSS VEE
LOGIC LEVEL CONVERTER
IC39: TC74HCT08AF
Quad 2-Input And Gate
Vcc 144B 134A 124Y 113B 103A 93Y 8
1A 11B 21Y 32A 42B 52Y 6GND 7
– +
OUT
1–IN1–VCC
+VCCOUT
2
1234
5
+IN1
–IN2+IN2
–+
6 7 8
IC27: µPC4570G2
Dual OP-Amp
IC40: BP5319FDC / DC converter for LCDs
1
2
3
4
7
8 56
9
CO VOUT VREF GND VCTLGND NC NC VIN
IC4: TC74HCU04AF
Hex Inverters
1A1Y
2YVCC
6A
1234
11
2A 6Y
5A
12 13
14
3A
3Y5Y
4A
567
4Y8 9 10
GND
IC6: NJM79M05FA
Voltage Regulator
IC5: AN77L04
Low Dropout Voltage Regulator
IC3: LC74781-9798
On Screen Display ControllerCS9
RST
23
VSS1
1
SIN11
SCLK
10
OSCIN
6
OSCOUT
7
SYNIN
17
SEPC
18
SEPOUT
19
CHARA
8
VDD2
12
SEPIN
20
CTRL3
22
4CTRL1
XtalIN XtalOUT BLANK CVIN CVOUT CTRL2
21
2
3
5
15
13
VDD1
24
Serial
parallel
converter
8-bits
latch
+
command
decoder
Horizontal
character
size
registerHorizontal
size
counter
Horizontal
display
position
registerHorizontal
dot
counter
Vertical
display
position
registerVertical
dot
counter
Blinking
and inversion
control
registerBlinking
and inversion
control
circuit
Blinking
and inversion
control
register
Blinking
and inversion
control
registerCharacter
control
counter
Line
control
counter
Timing generator
Synchronisation
signal generator
Character output control
Background control
Video output control
Display
control
register
RAM
write
address
counter
Display
RAM
Vertical
character
size
registerVertical
size
counter
DecoderFont
RAMShift
register
Decoder
Horizontal
character
size
registerHorizontal
character
size
register
Horizontal
character
size
registerHorizontal
character
size
registerIC7: MD3221N
Voltage Regulator
COMMON
OUTPUT
INPUT
- +
Error Amp.
Starter
Voltage
Reference
Input Short Circuit
Protection
Over Current
Protection
Over Current
Protection
Rush Current
Protection
Thermal
Protection
IN 1
GND3
OUT 2 
						

							DC/DC
controllerNEGATIVE
CHPMP
TRANSDUCER
H-bridge0
Oscillator
Bios FLAGxN
Reference
TRANSDUCER
H-bridge1TRANSDUCER
H-bridge3 TRANSDUCER
H-bridge2 TRANSDUCER
H-bridge9
Protection
logic TRANSDUCER
H-bridge8TRANSDUCER
H-bridge6
TRANSDUCER
H-bridge5
TRANSDUCER
H-bridge4 TRANSDUCER
H-bridge7
VVOLMIN4
TSD
CLK
time-out
POR
CLK CLK1
TEST logic
LVDS
receiverLVDS
receiverCLK DATA
DESERIALISER
&
PWM ENGINE
IS+
IS-
VVOL
V+
TXP0
GND
GND
TXN0
V+
V+
TXP1
GND
GND
TXN1
V+
V+
TXP2
GND
GND
TXN2
V+
V+
TXP3
GND
GND
TXN3
V+
TESTENA
TESTCLK
TESTMODE0CP1
VSS
VDD
V+
TXN8
GND
GND
TXP8
V+
V+
TXN7
GND
GND
TXP7
V+
V+
TXN6
GND
GND
TXP6
V+
V+
TXN5
GND
GND
TXP5
V+
FLAG3N
FLAG1N
D ATA N
TESTMODE1
TESTMODE2
TESTIN1
TESTOUT1
TESTOUT2
TESTSENSE1
TESTSENSE2
V+
TXP4
GND
GND
TXN4
V+
VREFEXT
VSS
PCLK
NCLK
VDD
D ATA P
VSSGND
PFETGATE
B+
SELECTDC
DCREF
FB
FLAG2N
V+
TXN9
GND
GND
TXP9
V+
VOLMIN4
VSSA
VSS
VDDA
VDD
VNEG
CP2
A
1
2
3
4
5
6
7
8
910BCDE FGH I J K
L
MN
SCHEMATIC DIAGRAM (AMP)
54 

All voltages are measured with a 10MΩ/V DC electronic volt meter.

Components having special characteristics are marked s and must be replaced 
with parts having specifications equal to those originally installed.

Schematic diagram is subject to change without notice.YSP-1
Page 51
to DSP_CB1, CB2
E7
F7
J7 Page 53
to INPUT (2)_W8, W9
I7
IC4: SN74LVC2G08DCUR
DUAL 2-INPUT POISITIVE-AND GATE
Vcc 8
765
5
1A 11B 2
1Y
32A
42B 2Y
GND
IC1, 3: TAD108
Sound Projector Transducer Amplifier
0
6.8
9.4
3.3
15.0
9.4
9.4
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.40
3.3
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
3.3
3.3
1.2
0
1.2
3.3
1.2
1.2
0
3.3
9.4
0.3
0
0
0.3
9.4
0 0
0
3.3
3.3
0.1
0.1
3.3
3.30
0 0
0
3.1
03.2 0
00
3.2
3.3
3.1 14.8
14.8
3.2
15.0
0.50.5
0.5
0.5 14.80
15.0
15.0 14.8
0 3.1 0
0
0
0
0
9.40
0 0.3
0.3
9.4
15.0
0 10.8
9.4 10.8
02.02.00 3.3 3.3 -2.2 -1.11.6
3.3
0 3.3 0 0
0
1.2
3.3 3.3
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
3.3
00
0
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
0.3
0
0
0.3
9.4
9.4
9.4
9.4
00
10.8
15.015.010.8 9.49.4
15.0
2.0
2.0
3.3
9.4
0.3
0
0
0.3
9.4
0
3.3
3.3
-2.2
-1.1 6.8
0
1.6 0.3 9.4
0
0.3
9.4
3.3
0
1.2
1.2
3.3
1.2
0 000
L
DRIVER
(WOOFER) DRIVER
(TWEETER)
DRIVER
(TWEETER)DRIVER
(TWEETER) DRIVER
(TWEETER)
3 8156
4
7 2
10CH D-CLASS IC 10CH D-CLASS IC
H-BRIDGE 
						

							YSP-1
55
YSP-1

 WARNING
Components having special characteristics are marked s and must be replaced with parts having specifications equal to
those originally installed.
Ôs
						

							YSP-1
56
YSP-1
✻ New Partsy
						

							YSP-1
57
YSP-1
✻ New Partsy
						

							YSP-1
58
YSP-1



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							YSP-1
59
YSP-1


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							YSP-1
60
YSP-1