Motorola Astro Digitalport Saber Detailed 68p81076c10 A Manual
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6-4 of U205 via bypass C213. The mixer’s LO port is matched to the radio’s PLL by a capacitive tap, C207 and C206. A balun transformer (T202) is used to couple the RF signal into the mixer. The primary of T202 is matched to the preceding stage by capacitor C223, with C227 providing a dc block to ground. The secondary of T202 provides a differential output, with a 180° phase differential being achieved by setting the secondary center tap to virtual ground using bypass capacitors C210, C211 and C212. The secondary of transformer T202 is connected to pins 1 and 15 of the mixer IC, which drives the source leg of dual FETs used to toggle the paralleled differential amplifier configuration within the Gilbert Cell. The final stage in the receiver front end is a 2-pole crystal filter (FL1). The crystal filter provides some of the receiver’s adjacent channel selectivity. The input to the crystal filter is matched to the 1st mixer using components L605, C611 and C614. The output of the crystal filter is matched to the input of IF buffer amplifier transistor Q601 by components L600, C609, and C610. Receiver Back EndThe IF frequency on the collector of Q601 is applied to a second crystal filter (FL2) through a matching circuit consisting of L601, L602, C604, and C612. The filter supplies further attenuation at the IF sidebands to increase the radio’s selectivity. The output of FL2 is routed to pin 32 of U401 through a matching circuit which consists of L603, C605, and C606 and dc block capacitor C613. In the ABACUS IC, (U401) the first IF frequency is amplified and then down converted to 450kHz, the second IF frequency. At this point, the analog signal is converted into two digital bit streams via a sigma-delta A/D converter. The bit streams are then digitally filtered and mixed down to baseband and filtered again. The differential output data stream is then sent to the ADSIC (U406) on the VOCON board where it is decoded to produce the recovered audio. The ABACUS IC (U401) is electronically programmable, and the amount of filtering which is dependent on the radio channel spacing and signal type is controlled by the microcomputer. Additional filtering, which used to be provided externally by a conventional ceramic filter, is replaced by internal digital filters in the ABACUS IC. The ABACUS IC contains a feedback AGC circuit to expand the dynamic range of the sigma-delta converter. The differential output data contains the quadrature (I and Q) information in 16-bit words, the AGC information in a 9-bit word, imbedded word sync information and fill bits dependent on sampling speed. A fractional-n synthesizer is also incorporated on the ABACUS IC for 2nd LO generation. The second LO/VCO is a Colpitts oscillator built around transistor Q1. The VCO has a varactor diode (VR401), which is used to the adjust the VCO frequency. The control signal for the varactor is derived from a loop filter consisting of C426, C428, and R413.
6-5 TransmitterThe 800MHz RF power amplifier (PA) is a 5-stage amplifier (U502). The RF power amplifier has a nominal input and output impedance of 50 ohms. An RF input drive level of approximately +3dBm, supplied from the VCO buffer IC (U303), is applied to pin 1 of U502. The dc bias for the internal stages of U502 is applied to pins 2, 5, and 6 of the module. Pins 2 and 5 being switched through Q502 and pin 6 being unswitched B+ to the final amplifier stage. Power control is achieved through the varying of the dc bias to pins 3 and 4, the third and fourth amplifier stages of the module. The amplified RF signal leaves the PA module via pin 7 and is applied to the directional coupler (U501). The purpose of U501 is to sample both the forward power and the reverse power. The reverse power will be present when there is other than a 50-ohm load at the antenna port. The sampling will be achieved by coupling some of the reflected power, forward and/or reverse, to a coupled leg on the coupler. The sampled RF signals are applied to diode CR501 for rectification and summing. The resultant dc signal is applied to the ALC IC (U504 pin 2) as RFDET to be used as an strength indicator of the RF signal being passed through the directional coupler (U501). The transmit ALC IC (U504) is the heart of the power control loop. The REF V line (U504 pin 7), a dc signal supplied from the D/A IC (U503), and the RF DET signal described earlier, are compared internally in the ALC IC to determine the amount of C BIAS, pin 4, to be applied to the base of transistor Q501. Transistor Q501 responds to the base drive level by varying the dc control voltages applied to pin 3 and 4 of the RF PA, controlling the RF power level of module, U502. The ALC IC also controls the base switching to transistor Q502 via pin 12, BIAS. The D/A IC (U503) controls the dc switching of the transceiver board. Its outputs, SC1 and SC3, pins 12 and 14 respectively, control transistor Q503, which then supplies TX 5V and RX 5V to the transceiver board. The D/A also supplies the dc bias to the detector diode (CR501) via pin 7, and the REF V signal to the ALC IC (U504).
7-1 VOCON Board Detailed Theory of Operation 7 IntroductionThis section of the manual provides a detailed circuit description of an ASTRO Digital SABER VOCON (Vocoder/Controller) Board. When reading the theory of operation, refer to your appropriate schematic and component location diagrams located in the back section of this manual. This detailed theory of operation will help isolate the problem to a particular component. However, first use the ASTRO Digital SABER Portable Radios Basic Service Manual to troubleshooting the problem to a particular board. GeneralThe VOCON board consists of two subsystems: •vocoder •controller Although these two subsystems share the same printed circuit board and work closely together, it helps to keep their individual functionality separate in describing the operation of the radio. The controller section is the central interface between the various subsystems of the radio. It is very similar to the digital logic portion of the controllers on many existing Motorola radios. Its main task is to interpret user input, provide user feedback, and schedule events in the radio operation, which includes programming ICs, steering the activities of the DSP and driving the display. The vocoder section performs the functions which previously were performed by analog circuitry. This includes all tone signaling, trunking signalling, and conventional analog voice, etc. All analog signal processing is done digitally utilizing a DSP56001. In addition it provides a digital voice plus data capability utilizing VSELP or IMBE voice compression algorithms. Vocoder is a general term used to refer to these DSP based systems and is short for voice encoder. In addition, the VOCON board provides the interconnect between the microcontrol unit (MCU), DSP, and the encryption board on secure- equipped radios.
7-2 Controller SectionRefer to Figure 4 and your specific schematic diagram. The controller section of the VOCON board consists entirely of digital logic comprised of a microcontrol unit (MCU-U204), a custom support logic IC (SLIC-U206), and memory consisting of: SRAM (U202), EEPROM (U201), and FLASH memory (U205, U210). The MCU (U204) memory system is comprised of a 32k x 8 SRAM (U202), 32k x 8 EEPROM (U201), and 512k x 8 FLASH ROM (U205,U210). The MCU also contains 1024 bytes of internal SRAM and 512 bytes of internal EEPROM. The EEPROM memory is used to store customer specific information and radio personality features. The FLASH ROM contains the programs which the HC11F1 executes. The FLASH ROM allows the controller firmware to be reprogrammed for future software upgrades or feature enhancements. The SRAM is used for scratchpad memory during program execution. The SLIC (U206) performs many functions as a companion IC for the MCU. Among these are expanded input/output (I/O), memory decoding and management, and interrupt control. It also contains the universal asynchronous receiver transmitter (UART) used for the RS232 data communications. The SLIC control registers are mapped into the MCU (U204) memory space. Figure 4 . VOCON Board - Controller Section U205 256Kx8 FLASH U210 256Kx8 FLASHU202 32Kx8 SRAMU201 32Kx8 EEPROM Address/Data/ Control ResetsClocks Controls Chip Selects/ Bank ControlGeneral Purpose I/O RS232 U206 SLIC IV SPI SCI A/D Address/Data/ Control ClocksGeneral Purpose I/O 512 Bytes EEPROM 1024 Bytes SRAM U204 MC68HC11F1 HC11/DSP InterfaceUniversal Connector Universal Connector Transceiver/Display MAEPF-24337-O ADSIC
7-3 The controller performs the programming of all peripheral ICs. This is done through a serial peripheral interface (SPI) bus. ICs programmed through this bus include the synthesizer, DAIC, reference oscillator, display, and ADSIC. On secure-equipped model, the encryption board is also controlled through the SPI bus. In addition to the SPI bus, the controller also maintains two asynchronous serial busses; the SB9600 bus and an RS232 serial bus. The SB9600 bus is for interfacing the controller section to different hardware option boards, some of which may be external to the radio. The RS232 is used for the function of a common data interface for external devices. User input is handled by the controller through top rotary controls and side buttons. On models with a display, an additional 3 x 2 or 3 x 6 keypad are also read. User feedback is provided by a single bicolor LED on the top and a two-line, fourteen-character display if equipped. The controller schedules the activities of the DSP through the host port interface. This includes setting the operational modes and parameters of the DSP. The controlling of the DSP is analogous to programming analog signaling ICs on standard analog radios. Vocoder SectionRefer to Figure 5 and your specific schematic diagram. The vocoder section of the VOCON board is made up of a digital signal processor (DSP-U405), 24k x24 static-RAM (SRAMs-U414, U403, and U402), 256kB FLASH ROM (U404), ABACUS/DSP support IC (ADSIC- U406), and an audio PA (U401). The FLASH ROM (U404) contains the program code executed by the DSP. As with the FLASH ROM used in the controller section, the FLASH ROM is reprogrammable so new features and algorithms can be updated in the field as they become available. Depending on the mode and operation of the DSP, corresponding program code is moved from the FLASH ROM into the faster SRAM, where it is executed at full bus rate. The ADSIC (U406) is basically a support IC for the DSP. It provides among other things, the interface from the digital world of the DSP to the analog world. The ADSIC also provides some memory management and provides interrupt control for the DSP processing algorithms. The configuration programming of the ADSIC is performed by the MCU. However some components of the ADSIC are controlled through a parallel memory mapped register bank by the DSP. In the receive mode, The ADSIC (U406) acts as an interface to the ABACUS IC, which can provide IF data samples directly to the DSP for processing. Or the IF data can be filtered and discriminated by the ADSIC and data provided to the DSP as raw discriminator sample data. The latter mode, with the ADSIC performing the IF filtering and discrimination, is the typical mode of operation.
7-4 In the transmit mode, the ADSIC (U406) provides a serial digital-to- analog (D/A) converter. The data generated by the DSP is filtered and reconstructed as an analog signal to present to the VCO as a modulation signal. Both the transmit and receive data paths between the DSP and ADSIC are through the DSP SSI port. The only analog device in the vocoder section is the audio PA (U401). This IC is an audio amplifier for the microphone analog input and speaker analog output. The audio PA allows steering between the internal and external microphone and internal and external speaker. Steering is accomplished through four control lines provided by the ADSIC and controlled by the DSP through the ADSIC parallel registers. The amplified microphone signal is provided to the ADSIC, which incorporates an analog-to-digital (A/D) converter to translate the analog waveform to a series of data. The data is available to the DSP through the ADSIC parallel registers. In the converse way, the DSP writes speaker data samples to a D/A in the ADSIC, which provides an analog speaker audio signal to the audio PA. Figure 5 . VOCON Board - Vocoder Section SSI SERIAL EXTAL MODB MODA HC11/DSP Interface D0-D23 BUS CONTROLA0-A15 U405 DSP56001SCI SERIALEncryption Interface Host Port U401 Audio PA System Clock Gata Array Logic ABACUS Rx InterfaceTx D/A General Purpose I/O Speaker D/AMicrophone A/DSerial Config. U406 ADSICABACUS Interface Modulation Out External Microphone Internal Microphone External Speaker Internal Speaker U414 8Kx24 SRAM U404 256Kx8 FLASHU403 8Kx24 SRAMU402 8Kx24 SRAM HC11 SPI MAEPF-24338-O
7-5 Switched RegulatorAll of the digital circuitry on the VOCON is supplied 5 volt regulated dc by a switched mode regulator (refer to Figure 3 on page 5 of Chapter 4). The fundamental parts of the regulator are U409, L402, C470, CR403, C463, and U407. Module U409 is a pulse width modulating (PWM) switched regulator controller. Coil L402 is an energy storage element, C470 is an output ripple filter, and CR403 is a Schottky diode switch. Capacitor C463 is added for UNSW_B+ ripple filter and is necessary for stability of the regulator. Module U407 is a supply supervisory IC, which provides a system reset function when the output of the regulator falls out of regulation, typically around 4.6Vdc. This switched mode regulator works by supplying just sufficient energy to the storage element to maintain the output power of the regulator at 5Vdc. It can be related to a flywheel in the sense that just enough energy can be added to a spinning flywheel to keep it spinning at a constant speed. In contrast to a typical linear type regulator, which basically shunts unused current to ground through an active resistive divider. The switched mode regulator is much more energy efficient. It can be noted that input current to the regulator is less than the load current. In fact, as input voltage to the regulator goes up, current supplied to the regulator actually goes down for a constant load. Module U409 works off of a clock with a nominal operating frequency of 160kHz (kit number NTN7749E), or 260kHz (kit numbers NTN7749F and NTN7749G). This may vary a little based on the load and input voltage. It maintains regulation by varying the duty cycle of a clock output driving L402. This signal is referred to as Lx on U409 (refer to Waveform W1). As long as the clock output is high, current flows from the supply into L402 allowing energy to be stored. When the clock output goes low, the diode CR403 conducts, allowing current to continue to flow from ground through L402. A pulse width on the Lx signal can be obtained, which provides the correct amount of energy to keep the output in regulation. Capacitor C470 is an output filter to reduce ripple on the output from the clock transitions. Module U409 is supplied directly from the unswitched battery supply. It is turned on and off through the control line connected to SHDN*/ ON/OFF. This is the same control line from the MCU, which controls the series pass element Q207, which switches SW_B+. A voltage level of approximately 2Vdc is required to turn the regulator on.
7-6 RX Signal PathThe vocoder processes all received signals digitally. This requires a unique back end from a standard analog radio. This unique functionality is provided by the ABACUS IC with the ADSIC (U406) acting as the interface to the DSP. The ABACUS IC located on the transceiver board provides a digital back end for the receiver section. It provides a digital output of I (In phase) and Q (Quadrature) data words which represent the IF (Intermediate Frequency) signal at the receiver back end (refer to appropriate transceiver section for more details on ABACUS operation). This data is passed to the DSP through an interface with the ADSIC (U406) for appropriate processing. The ADSIC interface to the ABACUS is comprised of the four signals SBI, DIN, DIN*, and ODC (refer to Figure 6). NOTE:An asterisk symbol (*) next to a signal name indicates a negative or NOT logic true signal. ODC is a clock ABACUS provides to the ADSIC. Most internal ADSIC functions are clocked by this ODC signal at a rate of 2.4MHz and is available as soon as power is supplied to the circuitry. This signal may initially be 2.4 or 4.8MHz after power-up. It is programmed by the ADSIC through the SBI signal to 2.4MHz when the ADSIC is initialized by the MCU through the SPI bus. For any functionality of the ADSIC to exist, including initial programming, this reference clock must be present. SBI is a programming data line for the ABACUS. This line is used to configure the operation of the ABACUS and is driven by the ADSIC. The MCU programs many of the ADSIC operational features through the SPI interface. There are 36 configuration registers in the ADSIC of which four contain configuration data for the ABACUS. When these particular registers are programmed by the MCU, the ADSIC in turn sends this data to the ABACUS through the SBI. Figure 6 . DSP RSSI Port - RX Mode 48KHz TX Data Interrupt Serial Transmit DataSerial Receive Data 2.4 MHz Receive Data Clock 20 KHz RX Data Interrupt 1.2 MHz Tx Data Serial Clock D8-D23 A0-A2,A13-A15,RD*,WR* SCKR RFS TFS SCKT RXD TXD ADSIC U406GCB0-GCB3 To Audio PA U401 SDO SC0 SC1 SC2 SCK SRD STD SSI SERIAL DSP56001 U405 IRQB IRQB8KHz SBI DIN DIN- IDCODCData In Data In*SBI ABACUS II Interface J401-1 J401-2 J401-8 J401-4 MAEPF-24339-O
7-7 DIN and DIN* are the data lines in which the I and Q data words are transferred from the ABACUS. These signals make up a deferentially encoded current loop. Instead of sending TTL type voltage signals, the data is transferred by flowing current one way or the other through the loop. This helps reduce internally generated spurious emissions on the transceiver board. The ADSIC contains an internal current loop decoder which translates these signals back to TTL logic and stores the data in internal registers. In the fundamental mode of operation, the ADSIC transfers raw IF data to the DSP. The DSP can perform IF filtering and discriminator functions on this data to obtain a baseband demodulated signal. However, the ADSIC contains a digital IF and discriminator function and can provide this baseband demodulated signal directly to the DSP, this being the typical mode of operation. The internal digital IF filter is programmable up to 24 taps. These taps are programmed by the MCU through the SPI interface. The DSP accesses this data through its SSI serial port. This is a 6 port synchronous serial bus. It is actually used by the DSP for both transmit and receive data transferal, but only the receive functions will be discussed here. The ADSIC transfers the data to the DSP on the SRD line at a rate of 2.4MHz. This is clocked synchronously by the ADSIC which provides a 2.4MHz clock on SC0. In addition, a 20kHz interrupt is provided on SC1 signaling the arrival of a data packet. This means a new I and Q sample data packet is available to the DSP at a 20kHz rate which represents the sampling rate of the received data. The DSP then processes this data to extract audio, signaling, etc. based on the 20kHz interrupt. In addition to the SPI programming bus, the ADSIC also contains a parallel configuration bus consisting of D8-D23, A0-A2, A13-A15, RD*, and WR*, This bus is used to access registers mapped into the DSP memory starting at Y:FFF0. Some of these registers are used for additional ADSIC configuration controlled directly by the DSP. Some of the registers are data registers for the speaker D/A. Analog speaker audio is processed through this parallel bus where the DSP outputs the speaker audio digital data words to this speaker D/A and an analog waveform is generated which is output on SDO (Speaker Data Out). In conjunction with the speaker D/A, the ADSIC contains a programmable attenuator to set the rough signal attenuation. However, the fine levels and differences between signal types is adjusted through the DSP software algorithms. The speaker D/A attenuator setting is programmed by the MCU through the SPI bus. The ADSIC provides an 8kHz interrupt to the DSP on IRQB for processing the speaker data samples. IRQB is also one of the DSP mode configuration pins at start up. This 8kHz signal must be enabled through the SPI programming bus by the MCU and is necessary for any audio processing to occur. For secure messages, the analog signal data may be passed to the secure module prior to processing speaker data for decryption. The DSP transfers the data to and from the secure module through its SCI port consisting of TXD and RXD. The SCI port is a two wire duplex asynchronous serial port. Configuration and mode control of the secure module is performed by the MCU through the SPI bus.