Motorola Astro Digitalport Saber Detailed 68p81076c10 A Manual

							7-8
The ADSIC contains four general purpose I/O labeled GCB0 -GCB3. 
These are connected to the AUDIO PA and are used for enabling the 
speaker and microphone amplifiers in the IC and for steering the 
speaker and microphone audio paths from internal to external. These 
I/O are controlled by the DSP through the ADSIC parallel 
configuration bus. The DSP then writes speaker data samples to the 
speaker D/A register through the parallel bus at an 8kHz rate and 
configures the AUDIO PA enable lines by writing the same bus to the 
register controlling the I/O.
The audio PA provides about 20dB of gain and a dual ended 
differential output; SPKR_COMMON, and EXT_SPKR or INT_SPKR. 
Internal or external speaker drive is achieved by changing the phase of 
the outputs on INT_SPKR and EXT_SPKR to be either in phase or out 
of phase with SPKR_COMMON. The signal which is out of phase with 
SPKR_COMMON will be driven.
Since all of the audio and signaling is processed in DSP software 
algorithms, all types of audio and signaling follow this same path. 
TX Signal PathThe transmit signal path follows some of the same design structure as 
the receive signal path described above in section D (refer to Figure 7). 
It is advisable to read through the section on RX Signal Path prior to 
this section. 
The ADSIC contains a microphone A/D with a programmable 
attenuator for coarse level adjustment. As with the speaker D/A 
attenuator, the microphone attenuator value is programmed by the 
MCU through the SPI bus. The analog microphone signal from the 
Audio PA (U401) is input to the A/D on MAI (Mic Audio In). The 
microphone A/D converts the analog signal to a series of data words 
and stores them in internal registers. The DSP accesses this data 
through the parallel data bus parallel configuration bus consisting of 
D8-D23, A0-A2, A13-A15, RD*, and WR*. As with the speaker data  Figure 7 .  DSP RSSI Port - TX Mode
48KHz TX Data Interrupt
Serial Transmit DataSerial Receive Data 2.4 MHz Receive Data Clock
20 KHz RX Data Interrupt
1.2 MHz Tx Data Serial Clock
D8-D23
A0-A2,A13-A15,RD*,WR*
SCKR
RFS
TFS
SCKT
RXD
TXD
ADSIC
U406GCB0-GCB3
To
Audio PA
U401 MAI
VVOMODIN
J401-15
SC0
SC1
SC2
SCK
SRD
STD SSI
SERIAL
DSP56001
U405
IRQB
IRQB8KHz
SBI
DIN
DIN-
IDCODCData In
Data In*SBI
ABACUS II
Interface
J401-1 J401-2
J401-8 J401-4
MAEPF-24340-O 
						

							7-9
samples, the DSP reads the microphone samples from registers 
mapped into its memory space starting at Y:FFF0. The ADSIC provides 
an 8kHz interrupt to the DSP on IRQB for processing these 
microphone data samples.
As with the received trunking low speed data, low speed data is 
processed by the MCU and returned to the DSP at the DSP SCLK port 
connected to the MCU port PA0. 
For secure messages, the analog signal may be passed to the secure 
module for encryption prior to further processing. The DSP transfers 
the data to and from the secure module through its SCI port 
consisting of TXD and RXD. Configuration and mode control of the 
secure module is performed by the MCU through the SPI bus.
The DSP processes these microphone samples and generates and mixes 
the appropriate signaling and filters the resultant data. This data is 
then transferred to the ADSIC IC on the DSP SSI port. The transmit 
side of the SSI port consists of SC2, SCK, and STD. The DSP SSI port is 
a synchronous serial port. SCK is the 1.2MHz clock input derived from 
the ADSIC which makes it synchronous. The data is clocked over to 
the ADSIC on STD at a 1.2MHz rate. The ADSIC generates a 48kHz 
interrupt on SC2 so that a new sample data packet is transferred at a 
48kHz rate and sets the transmit data sampling rate at 48Ksp. These 
samples are then input to a transmit D/A which converts the data to 
an analog waveform. This waveform is actually the modulation out 
signal from the ADSIC port VVO and is connected directly to the VCO. 
The transmit side of the transceiver is virtually identical to a standard 
analog FM radio.
Also required is the 2.4MHz ODC signal from the ABACUS IC. 
Although the ABACUS IC provides receiver functions it is important to 
note that this 2.4MHz reference is required for all of the ADSIC 
operations. 
						

							7-10
Controller 
Bootstrap and 
Asynchronous BusesThe SB9600 bus is an asynchronous serial communications bus 
utilizing a Motorola proprietary protocol. Its purpose is a means for 
the MCU to communicate with other hardware devices. In the ASTRO 
Digital SABER radio, it communicates with hardware accessories 
connected to the universal connector.
The SB9600 bus utilizes the UART internal to the MCU operating at 
9600 baud. The SB9600 bus consists of a LH_DATA (J201-4) and 
SB9600_BUSY (J201-6) signals. LH_DATA is actually the SCI TXD and 
RXD ports (U204 - PD0 and PD1) tied together through the MUX U208 
(see Figure 8). This makes the bus a simplex single-wire system. 
SB9600_BUSY (U204 - PA3) is an active low signal, which is pulled low 
when a device wants control of the bus. 
The same UART internal to the MCU is used in the controller bootstrap 
mode of operation. This mode is used primarily in downloading new 
program code to the FLASH ROMs on the VOCON board. In this mode, 
the MCU accepts special code downloaded at 7200 baud through the 
SCI bus instead of operating from program code resident in its ROMs. 
It however must operate in a two wire duplex configuration.
A voltage applied to J201-13 (Vpp) of greater than 10 Vdc will trip the 
circuit consisting of Q203, Q204, and VR207. This circuit sets the 
MODA and MODB pins of the MCU to bootstrap mode (logic 0,0) and 
configures the MUX, U208 to separate the RXD and TXD signals of the  Figure 8 .  Host SB9600 and RS232 Ports
PD1 (TXD)
PD0 (RXD)
HC11F1
U204
SLIC IV
U206 U208
J201-4
LH_DATA/BOOT_DATA_OUT
J201-15
RS232_DATA_OUT/BOOT_DATA_INBOOT_DATA_IN BOOT_DATA_OUT J201-15
SB9600_BUSYPA3
J201-10
RTS_IN*J201-8
RS232_DATA_IN
J201-14
CTSOUT*RXDIN
PJ3
RTSBIN
SLIC IV
U206
MAEPF-24341-O 
						

							7-11
MCU SCI port. Now if the Vpp voltage is raised to 12Vdc required on 
the FLASH devices for programming; the circuit comprised of VR208, 
Q211, and Q208 will trip supplying Vpp to the FLASH devices U205, 
U210, and U404. One more complication exists in that the 
BOOT_DATA_IN signal, RXD is multiplexed with the RS232 data out 
signal RS232_DATA_OUT. This multiplex occurs in the SLIC IV U206, 
which must also be properly configured.
The ASTRO Digital SABER radio has an additional asynchronous serial 
bus which utilizes RS232 bus protocol. This bus utilizes the UART in 
the SLIC IC (U206). It is comprised of RS232_DATA_OUT (15), 
RS232_DATA_IN (J201-8), CTSOUT* (J201-14), and RTSIN* (J201-10). 
It is a two wire duplex bus used to connect to external data devices. 
Vocoder BootstrapThe DSP has two modes of bootstrap; from program code stored in the 
FLASH ROM U404 or retrieving code from the host port.
During normal modes of operation, the DSP executes program code 
stored in the FLASH ROM U404. Unlike the MCU, however, the DSP 
moves the code from the FLASH ROM into the three SRAMs U402, 
U403, and U414 where it is executed from. Since at initial start-up, the 
DSP must execute this process before it can begin to execute system 
code, it is considered a bootstrap process. In this process, the DSP 
fetches 512 words, 1536 bytes, of code from the FLASH ROM starting 
at physical address $C000 and moves it into internal P memory. This 
code contains the system vectors including the reset vector. It then 
executes this piece of bootstrap code which basically in turn moves 
additional code into the external SRAMs.
A second mode of bootstrap allows the DSP to load this initial 512 
words of data from the host port, being supplied by the MCU. This 
mode is used for FLASH programming the DSP ROM when the ROM 
may initially be blank. In addition, this mode may be used for 
downloading some diagnostic software for evaluating that portion of 
the board.
The bootstrap mode for the DSP is controlled by three signals; MODA/
IRQA*, MODB/IRQB*, and D23 (kit number NTN8250D), or MODC 
(kit numbers NTN8250E and NTN8250F). All three of these signals are 
on the DSP (U405). MODA and MODB configure the memory map of 
the DSP when the DSP reset become active. These two signals are 
controlled by the ADSIC (U406) during power-up, which sets MODA 
low and MODB high for proper configuration. Later these lines 
become interrupts for analog signal processing. D23/MODC controls 
whether the DSP will look for code from the MCU or will retrieve code 
from the FLASH ROM. D23 high, or MODC low out of reset, will cause 
the DSP to seek code from the FLASH ROM (U404). For the second 
mode of bootstrap, the MCU drives BOOTMODE low, causing D23 to 
go low and MODC to go high. 
						

							7-12
SPI Bus InterfaceThis bus is a synchronous serial bus made up of a data, a clock, and an 
individual IC unique select line. Its primary purpose is to configure 
the operating state of each IC. ICs programmed by this include; 
display module, ADSIC, Fractional N Synthesizer, Pendulum Reference 
Oscillator, DAIC, and if equipped, the secure module.
The MCU (U204) is configured as the master of the bus. It provides the 
synchronous clock (SPI_SCK), a select line, and data (MOSI [Master 
Out Slave In]). In general the appropriate select line is pulled low to 
enable the target IC and the data is clocked in. Actually the SPI bus is 
a duplex bus with the return data being clocked in on MISO (Master In 
Slave Out). The only place this is used is when communicating with 
the secure module. In this case, the return data is clocked back to the 
MCU on MISO (master in slave out).
Universal Connector 
and Option SelectsThe universal connector is located on the back of the radio. It is the 
external port or interface to the outside and is used for programming 
and interfacing to external accessories. The signals are outlined in the 
following diagram. The universal connector connects to the VOCON 
board at J201 through a flex circuit routed down the back of the 
external housing. Connections to the universal connector and J201 on 
the VOCON board are shown in Figure 9 and Figure 10.
Figure 9 .  Universal Connector
1
23
45
6
78
9
10 11
12
VIEW FROM BACK OF
RADIO 1.   Speaker Common
2.   External Speaker
3.   LH data/ Boot data out
4.   External MIC
5.   CTSOUT*
6.   SB9600 Busy
7.   Option Select 1
8.   Opt B+/ Boot Sel/ Vpp
9.   RTSIN*/ Keyfail
10.   Opt sel2 (Keyload)
11.   RS232 data out/ Boot data in
12.   RS232 data in
SIGNAL NAMES
MAEPF-24343-O
Figure 10 .  VOCON Board Connector - J201
VOCON BOARD CONNECTOR
J201-1     N.C
J201-2     N.C.
J201-3     N.C.
J201-4     LH_DATA/BOOT_DATA_OUT
J201-5     Ext Mic
J201-6     SB9600_BUSY
J201-7     Option Select 1
J201-8     RS232_DATA_IN
J201-9     Option Sel 2 (Keyload*)
J201-10   RTSIN*/KEYFAIL*
J201-11   Speaker Common
J201-12   External Speaker
J201-13   OPTB+/Boot Sel/Vpp
J201-14 
CTSOUT*
J201-15   RS232 Data Out/ Boot Data In
2 14
1 15
MAEPF-24344-O 
						

							7-13
Most of the signals are extensions of circuits described in other areas 
of this manual. However there are two option select pins used to 
configure special modes; Option Select 1 and Option Select 2. These 
pins are controlled by accessories connected to the universal 
connector. The following table outlines their functions as defined at 
the universal connector:
Keypad and Display 
ModuleThe front cover assembly contains the internal speaker, and internal 
microphone. An optional integral 2 line by 14 character LCD display 
is available with either a 3 x 2 keypad or 3 x 6 keypad. This unit is not 
considered field repairable.
The internal speaker and microphone are connected to the VOCON 
connector J701 through a flex circuit. This flex circuit along with J701 
also contain the keypad control lines. The keypad is read though a row 
and column matrix made up of ROW1, ROW2, ROW3, ROW4, ROW5, 
ROW6, and COL1, COL2, and COL3. These signals are input to I/O 
ports on the SLIC (U206) and individually pulled to a high state 
through resistors. When a key is pressed the respective signals for a 
single row and a single column are set to logic zero. The MCU reads 
these ports through the SLIC parallel registers, provides for key 
debounce, and determines which key has been pressed.
The display is controlled by the MCU which programs the display 
through the SPI bus, DISP_EN* (select) and DISP_RST*. In addition 
display backlighting is provided by two white LEDs controlled by the 
BL_EN signal. SW_B+ routed to the display is used to power these 
LEDs. All other circuitry on the display is powered by 5Vdc provided 
by the VOCON board. The display is connected to the VOCON board 
at J601 through a separate flex circuit.Table 1 . Option Select Functions
Opt Sel 1Opt Sel 2
Keyload10
No Function11
External PTT01 
						

							7-14
Controls and 
Control Top FlexThe control top controls include an on/off switch, volume, 16 position 
mode select switch with two position toggle, and ergo code/clear mode 
switch with additional emergency switch. The side controls include 
three momentary push button switches (monitor, RAT1, RAT2) and 
PTT. These components are connected through a flex circuit to the 
controller at J901, see Figure 11. 
UNSW_B+ is routed through S901 to provide the B+_SENSE signal 
which provides radio power control. Refer to the power distribution 
section for further details.
Volume control is provides by R901 which is a potentiometer biased 
between +5Vdc and ground. The VOL signal is a voltage level between 
+5Vdc and 0Vdc dependent on the position of the rotary knob. VOL 
is an input to an A/D port on the MCU (U204). The MCU sends the 
appropriate message to the DSP to adjust speaker volume based on this 
setting.
Switch S903 is the two-position programmable switch typically used 
for code or clear mode selection. It is an input to a control I/O with a 
pull up resistor so the logic defaults high. Selecting clear mode pulls 
this signal to a logic low. Appropriate operation is configured by the 
MCU. In addition, this switch contains an additional momentary 
button typically used for emergency. This button is connected along 
with the PTT, and programmable side buttons on a resistor divider 
network biased between +5Vdc and ground. This network made up of 
R902, R903, and R904 provides a voltage level to an A/D port on the 
MCU dependent on which button is pressed. The MCU determines 
which button is pressed based on the value at the A/D port.Figure 11 .  Control Top Flex
R902
91K
R904
150KSB1
(MON)
SB2
SB3
S903 TOP BUTTON
PTT
1
2
4
8
BS902
Zone/Channel
Select
CC
A
R901 VOL S901
ON/OFF
1
2 3
4 5
UNSW_B+ (1)
+5V (5)
PROG_SWITCH (2)
VOL (3)
EMERG (4)
B+_SENSE (10)
GREEN_LED (8)
RED_LED (12)
INT_PTT* (6)
RTA0 (11)
RTA1 (13)
RTA2 (15)
RTA3 (7)
A/B SWITCH (9)
DGND (14)
CR901
RED CR902
GREEN
1
2 3 To Controller
J901
R903
68K
MAEPF-24345-O 
						

							7-15
S902 is a binary coded switch. The output pins from this switch are 
connected to I/O ports on the controller. It provides a 4 bit binary 
word to the MCU indicating which of the 16 positions the rotary is set 
to. This switch provides an additional output, A/B_SWITCH, which 
effectively doubles its range by providing decoding for two sets of 16 
positions. A/B_SWITCH is also read by the MCU on an I/O port.
Controller Memory 
MapFigure 12 depicts the controller section memory map for the parallel 
data bus as used in normal modes of operation. There are three maps 
available for normal operation, but map 2 is the only one used. In 
bootstrap mode, the mapping is slightly different and will be 
addressed later.
The external bus for the host controller (U204)) consists of one 32Kx8 
SRAM (U202), one 32Kx8 EEPROM (U201), two 256Kx8 FLASH ROMs 
(U205, U210), and SLIC (U206) configuration registers. In addition the 
DSP host port is mapped into this bus through the SLIC address space. 
The purpose of this bus is to interface the MCU (U204) to these 
devices.
The MCU executes program code stored in the FLASH ROMs. On a 
power-up reset, it fetches a vector from $FFFE, $FFFF in the ROMs and 
begins to execute code stored at this location. The external SRAM 
along with the internal 1Kx8 SRAM is used for temporary variable 
storage and stack space. The internal 512 bytes of EEPROM along with 
the external EEPROM are used for non volatile storage of customer 
specific information. More specifically the internal EEPROM space 
contains transceiver board tuning information and on power-down 
some radio state information is stored in the external EEPROM.
The SLIC is controlled through sixteen registers mapped into the MCU 
memory at $1400 - $14FF. This mapping is achieved by the following 
signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8, HA9. Upon 
power-up, the MCU configures the SLIC including the memory map 
by writing to these registers.
The SLIC memory management functions in conjunction with the 
chip selects provided by the MCU provide the decoding logic for the 
memory map which is dependent upon the “map” selected in the 
SLIC. The MCU provides a chip select, CSGEN*, which decodes the 
valid range for the external SRAM. In addition CSI01* and CSPROG* 
are provide to the SLIC decoding logic for the external EEPROM and 
FLASH ROM respectively. The SLIC provides a chip select and banking 
scheme for the EEPROM and FLASH ROM. The FLASH ROM is banked 
into the map in 16KB blocks with one 32KB common ROM block. The 
external EEPROM may be swapped into one of the banked ROM areas. 
This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT, 
HA15_OUT, HA16, and HA17 from the SLIC (U206) and D0-D8 and 
A0-16 from the MCU (U204).
The SLIC provides three peripheral chip selects; XTSC1B, XTCS2B, and 
XTCS3B. These can be configure to drive an external chip select when 
its range of memory is addressed. XTSC1B is used to address the host 
port interface to the DSP. XTSC2B is used to address a small portion of  
						

							7-16
external SRAM through the gate U211. XTSCB3 is used as general 
purpose I/O for interrupting the secure module.
In bootstrap mode the memory map is slightly different. Internal 
EEPROM is mapped at $FE00-$FFFF and F1 internal SRAM starts at 
$0000-$03FF. In addition a special bootstrap ROM appears in the ROM 
space from $B600-$BFFF. For additional information on bootstrap 
mode refer to the section Controller Bootstrap and Asynchronous 
Buses.
Figure 12 .  Controller Memory Mapping
$1060
$1500
$1600 HOST PORT$0000
$1800
$3fff
Ext RAM$1000
$1400
F1
INT RAM
F1 REGS
**
$0000
$1000
$2000
$3000
$4000
$5000
$6000
$7000
$8000
$9000
$A000
$B000
$C000
$D000
$E000
$F000
$FFFF
MAP 2 NON-MUX 32K COMMON
Int EE$0E00
COMMON ROM
BANKED ROM/EEPROM
CONTROLLED BY SLICRAM
EXTERNAL EEPROM
CONTROLLED BY F1 F1 REGISTERS
AND MEMORY:
*
SLIC III REGISTER
$1400 - $14FF
INT RAM: $1060-$13FF
INT EE: $0E00-$0FFF
REGISTERS: $1000-$105F
External
RAM
MAEPF-24346-O *
SLIC REG
External
RAM
External
RAM 
						

							7-17
The SLIC is controlled through sixteen registers mapped into the MCU 
memory at $1400 - $14FF. This mapping is achieved by the following 
signals from the MCU: R/W*, CSIO1*, HA0-HA4,HA8, HA9. Upon 
power-up, the MCU configures the SLIC including the memory map 
by writing to these registers.
The SLIC memory management functions in conjunction with the 
chip selects provided by the MCU provide the decoding logic for the 
memory map which is dependent upon the “map” selected in the 
SLIC. The MCU provides a chip select, CSGEN*, which decodes the 
valid range for the external SRAM. In addition CSI01* and CSPROG* 
are provide to the SLIC decoding logic for the external EEPROM and 
FLASH ROM respectively. The SLIC provides a chip select and banking 
scheme for the EEPROM and FLASH ROM. The FLASH ROM is banked 
into the map in 16KB blocks with one 32KB common ROM block. The 
external EEPROM may be swapped into one of the banked ROM areas. 
This is all controlled by EE1CS*, ROM1CS*, ROM2CS*, HA14_OUT, 
HA15_OUT, HA16, and HA17 from the SLIC (U206) and D0-D8 and 
A0-16 from the MCU (U204).
The SLIC provides three peripheral chip selects; XTSC1B, XTCS2B, and 
XTCS3B. These can be configure to drive an external chip select when 
its range of memory is addressed. XTSC1B is used to address the host 
port interface to the DSP. XTSC2B is used to address a small portion of 
external SRAM through the gate U211. XTSCB3 is used as general 
purpose I/O for interrupting the secure module.
In bootstrap mode the memory map is slightly different. Internal 
EEPROM is mapped at $Fe00-$FFFF and F1 internal SRAM starts at 
$0000-$03fff. In addition a special bootstrap ROM appears in the ROM 
space from $B600-$BFFF. For additional information on bootstrap 
mode refer to the section Controller Bootstrap and Asynchronous 
Buses.
Vocoder Memory 
MapThe vocoder (DSP) external bus consists of three 8k x 24 SRAMs (U402, 
U403, U414), one 256k x 8 FLASH ROM (U404), and ADSIC (U406) 
configuration registers.
The DSP56001 (U405) has a 24 bit wide data bus (D0-D23) and a 16 bit 
wide address bus (A0 - A15).   The DSP can address three 64k x 24 
memory spaces: P (Program), Dx (Data X), and Dy (Data Y). These 
additional RAM spaces are decoded using PS* (Program Strobe), DS* 
(Data Strobe), and X/Y*. RD* and WR* are separate read and write 
strobes. 
The ADSIC provides additional memory decoding logic for the RAMs 
in the form of RSEL* used in decoding U403. RSEL* provides the logic 
A13
 x A14. U415 provides logic in the form of A13 + A14 for decoding 
U414. RSEL* logic is programmed by the MCU through the SPI bus 
interface.
The ADSIC also provides memory decoding for the FLASH ROM 
(U404). EPS* provides the logic A15 x (A14 » A13)
 and is use as a select 
for the ROM. The ADSIC provide three bank lines for selecting 16k 
byte banks from the ROM. This provides decoding for 128K bytes from