Samsung Exynos 5 User Manual

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Exynos 5250_UM 5 Clock Controller 
 5-25  
5.5.1 Clock Gating 
Exynos 5250 can disable the clock operation of each IP if it is not required. Disabling the clock operation reduces 
the dynamic power. 
There are two types of clock gating control registers to Disable/Enable clock operation: 
 Clock gating control register for function block 
 Clock gating control register for IP 
These two registers are AND operated together to generate a final clock gating enable signal. As a result, if either 
of the two register field is turned OFF, the resulting clock is stopped. For example, to stop clocks that are provided 
to MIXER module, you may set CLK_MIXER field in CLK_GATE_IP_DISP1 register to 0 or CLK_DISP1 field in 
CLK_GATE_BLOCK register to 0.  
NOTE: For latter case, all clocks in DISP1 block including MIXER clocks are turned off. 
Caution: It should be guaranteed that S/W does not access IPs whose clock is gated. It may cause system 
failure. 
 
5.5.2 Clock Diving 
Whenever clock divider control register is changed, it is recommended that you verify clock divider status registers 
before using the new clock output. This guarantees the corresponding divider finishes changing to a new dividing 
value before its output is used by other modules. 
  
						

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Exynos 5250_UM 5 Clock Controller 
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5.6 Special Clock Description 
Special Clock Description section describes special clocks in Exynos 5250. 
 
5.6.1 Special Clock Table 
Table 5-11 describes the special clocks in Exynos 5250. 
Table 5-11   Special Clocks in Exynos 5250 
Name Description Range Source 
SCLK_CAM0, 1 Reference clock for external 
CAM device CAM spec All possible clock sources 
SCLK_CAM_BAYER Reference clock for external 
CAM device CAM spec All possible clock sources 
SCLK_GSCL_WRAP_A, B CSIS operating clock to 266 MHz All possible clock sources 
SCLK_FIMD1 FIMD operating clock to 100 MHz All possible clock sources 
SCLK_MIPI1 MIPI DSIM clock to 100 MHz All possible clock sources 
SCLK_MIPIDPHY1 MIPI DPHY 1 Lane clock to 920 MHz All possible clock sources 
SCLK_DP1_EXT_MST_VID DPTX LINK clock – All possible clock sources 
SCLK_MIXER MIXER clock 54 MHz (TV) to 
148.5 MHz (HDMI) 
SCLK_VPLL, HDMI PHY 
output 
SCLK_JPEG JPEG clock to 166 MHz All possible clock sources 
SCLK_HDMI HDMI LINK clock to 148.5 MHz All possible clock sources 
SCLK_PIXEL HDMI PIXEL clock to 148.5 MHz All possible clock sources 
SCLK_SPDIF SPDIF operating clock to 83 MHz SCLK_AUDIO0, 1, 2 
SCLK_MMC0, 1, 2, 3 HSMMC operating clock to 50 MHz All possible clock sources 
SCLK_USBDRD30 USB DRD 3.0 Suspend clock 0.032 to  
125 MHz 
SCLK_MPLL_USER or 
SCLK_CPLL 
SCLK_AUDIO0 AUDIO operating clock (I2S) to 100 MHz 
AUDIOCLK0 and All 
possible clock sources 
except SCLK_HDMIPHY  
SCLK_PCM0, 1, 2 AUDIO operating clock (PCM) to 5 MHz SCLK_AUDIO0, 1, 2 
SCLK_PWM PW M clock in PERIC_BLK – All possible clock sources 
SCLK_PW M_ISP PW M clock in ISP_BLK – All possible clock sources 
SCLK_SPI0, 1, 2 SPI operating clock to 100 MHz All possible clock sources 
SCLK_SPI0, 1_ISP SPI operating clock in ISP_BLK to 100 MHz All possible clock sources 
SCLK_UART0, 1, 2, 3 UART operating clock to 200 MHz All possible clock sources 
SCLK_UART_ISP UART operating clock in 
ISP_BLK to 200 MHz All possible clock sources 
  
						

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Exynos 5250_UM 5 Clock Controller 
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 All possible clock sources are:  
 XXTI  
 SCLK_HDMI24M  
 SCLK_DPTXPHY  
 SCLK_UHOSTPHY  
 SCLK_HDMIPHY  
 SCLKMPLL_USER  
 SCLKCPLL  
 SCLKEPLL  
 SCLKGPLL 
 SCLKVPLL 
 XXTI refers to external crystal 
 SCLK_DPTXPHY refers to DPTX PHY output clock 
 SCLK_UHOSTPHY refers to USB PHY 48 MHz output clock 
 SCLK_HDMI24M refers to HDMI PHY output clock 
 SCLK_HDMIPHY refers to HDMI PHY (PIXEL_CLK) output clock 
 SCLKMPLL_USER, SCLKCPLL, SCLKEPLL, SCLKGPLL, and SCLKVPLL refer to the output clock of MPLL, CPLL, EPLL, 
GPLL and VPLL, respectively. 
Table 5-12 describes the I/O clocks in Exynos 5250. 
Table 5-12   I/O Clocks in Exynos 5250 
Name I/O PAD GPIO Function Range Description 
IOCLK_AC97 In Xi2s1SCLK Func2: AC97BITCLK 12.288 MHz AC97-bit clock 
IOCLK_I2S0, 1, 2 In 
Xi2s0CDCLK 
Xi2s1CDCLK 
Xpcm2EXTCLK 
Func0: I2S_0_CDCLK 
Func0: I2S_1_CDCLK 
Func2: I2S_2_CDCLK 
to 83.4 MHz I2S CODEC clock 
IOCLK_PCM0, 1, 2 In 
Xi2s0CDCLK 
Xi2s1CDCLK 
Xpcm2EXTCLK 
Func1: PCM_0_EXTCLK 
Func1: PCM_1_EXTCLK 
Func0: PCM_2_EXTCLK 
to 83.4 MHz PCM CODEC clock 
IOCLK_SPDIF In Xpcm2EXTCLK Func1: SPDIF_EXTCLK 36.864 MHz SPDIF input clock 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
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5.7 CLKOUT 
You can monitor certain clocks in Exynos 5250 using XCLKOUT port. Each of the nine CMUs in Exynos 5250 
contains CLKOUT control logic where one of the clocks in that CMU is selected and divided if necessary. The 
generated CLKOUT signal from each CMU is fed to power management unit and multiplexed with other CLKOUT 
signals and XXTI, RTC_TICK_SRC, and RTCCLK clocks. Figure 5-4 illustrates CLKOUT control logic in Exynos 
5250. Clock selection information is listed in Table 5-13 & Table 5-14. 
Figure 5-6 illustrates the Exynos 5250 CLKOUT control logic. 
 
    Figure 5-6   Exynos 5250 CLKOUT Control Logic DIV(1~64)
DIV(1~64)
DIV(1~64)
DIV(1~64)
DIV(1~64)
XXTI
RTC_TICK_SRC                
RTCCLK   
XCLKOUT
CMU_TOP
CMU_LEX
CMU_R0X
CMU_R1X
CMU_CDREX
PMU
DIV(1~64)
CMU_ISP
DIV(1~64)
CMU_ACP
DIV(1~64)
CMU_CORE
DIV(1~64)
CMU_CPU  
						

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Exynos 5250_UM 5 Clock Controller 
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Table 5-13 lists the CLKOUT input clock selection information. 
Table 5-13   CLKOUT Input Clock Selection Information (Part 1) 
NO CMU_CPU CMU_CORE CMU_CDREX CMU_ISP CMU_TOP PMU 
0 APLL_FOUT MPLL_FOUT 
_RGT MCLK_CDREX ACLK_266 EPLL_FOUT PMU_DEBUG 
1 – – ACLK_CDREX ACLK_DIV0 VPLL_FOUT CMU_CDREX 
2 – – PCLK_CDREX ACLK_DIV1 CPLL_FOUT CMU_CORE 
3 – – RCLK_CDREX SCLK_MPW M 
_ISP SCLK_HDMI24M CMU_ISP 
4 ARMCLK – – – SCLK_DPTXPHY CMU_LEX 
5 ACLK_CPUD ACLK_CORED – – SCLK_UHOSTPHY CMU_R0X 
6 – ACLK_COREP – – SCLK_HDMIPHY CMU_R1X 
7 ATCLK SCLK_RSVD3 
_CORE – – AUDIOCDCLK0 CMU_TOP 
8 PERIPHCLK ACLK_R1BX – – AUDIOCDCLK1 CMU_CPU 
9 PCLK_DBG C2C_CLK – – AUDIOCDCLK2 CMU_ACP 
10 SCLK_HPM – – – SPDIF_EXTCLK – 
11 – – – – ACLK_400_G3D – 
12 – – – – ACLK_333 – 
13 – – – – ACLK_266 – 
14 – – – – GPLL_FOUT – 
15 – – – – ACLK_400_ISP – 
16 – – – – ACLK_400_IOP XXTI 
17 – – – – SCLK_JPEG – 
18 – – – – RX_HALF_BYTE 
_CLK_A 
RTC_TICK 
_SRC 
19 – – – – RX_HALF_BYTE 
_CLK_B RTCCLK 
20 – – – – CAM_A_PCLK – 
21 – – – – CAM_B_PCLK  
22 – – – – S_RXBYTECLKHS0 
_2L – 
23 – – – – S_RXBYTECLKHS0 
_4L – 
24 – – – – ACLK_300_DISP1 – 
25 – – – – ACLK_300_GSCL – 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
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Table 5-14 lists the CLKOUT input clock selection information (Part 2). 
Table 5-14   CLKOUT Input Clock Selection Information (Part 2) 
NO CMU_LEX CMU_R0X CMU_R1X CMU_ACP 
0 ACLK_266 ACLK_266 ACLK_266 SCLK_MPLL_LFT 
1 ACLK_DLEX ACLK_DR0X ACLK_DR1X ACLK_ACP 
2 ACLK_PLEX ACLK_PR0X ACLK_PR1X PCLK_ACP 
3 – – – ACLK_SYSLFT 
4 – – – PCLK_SYSLFT 
5 – – – EFCLK_SYSLFT 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
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5.8 I/O Description 
Signal I/O Description Pad Type 
XXTI Input External oscillator pad XXTI Dedicated 
EPLLFILTER Input/Output Pad for EPLL loop Filter capacitor XEPLLFILTER Dedicated 
VPLLFILTER Input/Output Pad for VPLL loop Filter capacitor XVPLLFILTER Dedicated 
XCLKOUT Output Clock Out pad XCLKOUT Dedicated 
 
  
						

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Exynos 5250_UM 5 Clock Controller 
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5.9 Register Description 
Clock controller controls PLLs and clock generation units. This section describes how to control these parts using 
Special Functional Registers (SFRs) in the clock controller. Do not change any reserved area. Changing value of 
reserved area may lead to unexpected behavior. 
Figure 5-5 illustrates the address map of Exynos 5250 clock controller. There are nine CMUs in Exynos 5250 and 
each CMU uses 16 KB address space for SFRs. The nine CMUs are CMU_CPU, CMU_CORE, CMU_ACP, 
CMU_ISP, CMU_TOP, CMU_LEX, CMU_R0X, CMU_R1X, and CMU_CDREX. The internal structure of the 
address space for each CMU is similar to all CMUs. This structure is illustrated in the right part of Figure 5-5. The 
internal structure is divided into these categories: 
 0x000 to 0x1FF is used for PLL control: PLL lock time and control 
 0x200 to 0x4FF is used for mux control: Mux selection, output masking, and status 
 0x500 to 0x6FF is used for clock division: Divider ratio and status 
 0x700 to 0x8FF is reserved and user is not allowed to access the region. 
 0x900 to 0x9FF is used for clock gating control: Clock gating of IPs and function blocks 
 0xA00 to 0xAFF is used for CLKOUT: CLKOUT input clock selection and divider ratio 
NOTE: For CMU_ACP, CMU_ISP, CMU_LEX and CMU_R0X/R1X, CLK_GATE_IP_XXX registers are located at 0x800. 
Additionally, some CMUs use addresses beyond 0xAFF for other functions such as CPU in CMU_CPU. Refer to 
register description for more information. 
  
						

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Exynos 5250_UM 5 Clock Controller 
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In Figure 5-7, XXX means function block name that is LEX, R0X/R1X, TOP, GSCL, MFC, G3D, GEN, DISP1, 
MAU, FSYS, PERIC, and PERIS.  
Figure 5-7 illustrates the Exynos 5250 clock controller address map. 
 
    Figure 5-7   Exynos 5250 Clock Controller Address Map 
 
 0x1001_4000
0x1002_4000
CMU_ACP
CMU_ISP
CMU_TOP
CMU_LEX
0x1001_8000
0x1001_C000
0x1002_0000
0x1002_8000
0x000
Reserved
CLK_DIV_XXX
CLK_DIV_STAT_XXX
CLK_GATE_IP_XXX
CLKOUT_CMU_XXX
0x100
0x200
0x300
0x400
0x500
0x600
0x700
0x800
0x900
0xA00
0x000
CLK_DIV_STAT_XXX
CLK_GATE_IP_XXX
CLKOUT_CMU_XXX
0x100
0x200
0x300
0x400
0x500
0x600
0x700
0x800
0x900
0xA00
0x000
Reserved
CLK_DIV_STAT_XXX
CLKOUT_CMU_XXX
0x100
0x200
0x300
0x400
0x500
0x600
0x700
0x800
0x900
0xA00
Divider status
IP clock gating
CLKOUT control
CMU_R0X
xPLL_LOCK
CLK_SRC_XXX
CLK_MUX_STAT_XXX
xPLL_CON
CLK_SRC_MASK_XXX
Divider ratio
Mux selection
Mux output masking
Mux status
PLL lock time
PLL control
* XXX : function block name
CMU_R1X
0x1002_C000
CMU_CDREX
0x1003_4000
0x1003_0000
CMU_CORE
CMU_CPU
0x1001_0000  
						

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Exynos 5250_UM 5 Clock Controller 
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5.9.1 Register Map Summary 
 Base Address: 0x1001_0000 
Register Offset Description Reset Value 
APLL_LOCK 0x0000 Control PLL Locking period for APLL 0x0000_0FFF 
RSVD 0x0004 
to 0x00FC Reserved Undefined 
APLL_CON0 0x0100 Control PLL output frequency for APLL 0x00C8_0601 
APLL_CON1 0x0104 Control PLL AFC 0x0020_3800 
RSVD 0x0108 
to 0x01FC Reserved Undefined 
CLK_SRC_CPU 0x0200 Select Clock Source for CMU_CPU 0x0000_0000 
RSVD 0x0204 
to 0x03FC Reserved Undefined 
CLK_MUX_STAT_CPU 0x0400 Clock MUX Status for CMU_CPU 0x0011_0001 
RSVD 0x0404 
to 0x04FC Reserved Undefined 
CLK_DIV_CPU0 0x0500 Set Clock Divider ratio for CMU_CPU 0x0000_0000 
CLK_DIV_CPU1 0x0504 Set Clock Divider ratio for CMU_CPU 0x0000_0000 
RSVD 0x0508 
to 0x05FC Reserved Undefined 
CLK_DIV_STAT_CPU0 0x0600 Clock Divider Status for CMU_CPU 0x0000_0000 
CLK_DIV_STAT_CPU1 0x0604 Clock Divider Status for CMU_CPU 0x0000_0000 
RSVD 0x0608 
to 0x07FC Reserved Undefined 
CLK_GATE_SCLK_CPU 0x0800 Control Special Clock Gating for CMU_CPU 0xFFFF_FFFF 
RSVD 0x0804 
to 0x09FC Reserved Undefined 
CLKOUT_CMU_CPU 0x0A00 CLKOUT control register 0x0001_0000 
CLKOUT_CMU_CPU 
_DIV_STAT 0x0A04 Clock Divider Status for CLKOUT  0x0000_0000 
RSVD 0x0A08 
to 0x0FFC Reserved Undefined 
ARMCLK_STOPCTRL 0x1000 ARM Clock Stop Control register 
 0x0000_0044 
RSVD 0x1008 
to 0x100C Reserved Undefined 
PARITYFAIL_STATUS 0x1010 PARITYFAIL Status register 0x0000_0000 
PARITYFAIL_CLEAR 0x1014 PARITYFAIL Status register 0x0000_0000 
RSVD 0x1018 
to 0x101C Reserved Undefined 
PWR_CTRL 0x1020 Power Control register 0x0000_0033