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Samsung Exynos 5 User Manual

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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-79  
15.5.2.14 VIDOSD1B 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0054, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_RightBotX 
_F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotY 
_F_E [22] RW Specifies the extended vertical screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotX 
_F [21:11] RW Specifies the horizontal screen coordinate for the Right 
Bottom pixel of OSD image. 0 
OSD_RightBotY 
_F [10:0] RW Specifies the vertical screen coordinate for the Right 
Bottom pixel of OSD image. 0 
NOTE: Registers must contain word boundary X position. 
Therefore, ensure that the:  
  24-bpp mode contains X position by 1 pixel (for example, X = 0, 1, 2, 3….) 
  16-bpp mode contains X position by 2 pixel (for example, X = 0, 2, 4, 6….) 
  8-bpp mode contains X position by 4 pixel (for example, X = 0, 4, 8, 12….) 
 
15.5.2.15 VIDOSD1C 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0058, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA0_R_H_F=[23:20]=RW=Specifies the upper value of=Red Alpha=(case AEN ===
0)=0=
ALPHA0_G_H_F=[19:16]=RW=Specifies the upper value of=Green Alpha (case AEN 
== 0)=0=
ALPHA0_B_H_F=[15:12]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
0)=0=
ALPHA1_R_H_F=[11:8]=RW=Specifies the upper value of=Red Alpha (case AEN ===
1)=0=
ALPHA1_G_H_F=[7:4]=RW=Specifies the upper value of=Green Alpha (case AEN 
== 1)=0=
ALPHA1_B_H_F=[3:0]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
1)=0=
NOTE: Refer to VIDW1ALPHA0, 1 register for more information.
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Exynos 5250_UM 15 Display Controller 
 15-80  
15.5.2.16 VIDOSD1D 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x005C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved (should be 0)=0=
OSDSIZb=[25:0]=RW=Specifies the Window Size.=
For=example,=Height= W idth (number of words) 0 
 
15.5.2.17 VIDOSD2A 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0060, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_LeftTopX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for the 
Left Top pixel of OSD image. 0 
OSD_LeftTopX_ 
F [21:11] RW Specifies the horizontal screen coordinate for the Left 
Top pixel of OSD image. 0 
OSD_LeftTopY_F [10:0] RW Specifies the vertical screen coordinate for the Left Top 
pixel of OSD image. 0
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Exynos 5250_UM 15 Display Controller 
 15-81  
15.5.2.18 VIDOSD2B 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0064, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_RightBotX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for the 
Right Bottom pixel of OSD image. 0 
OSD_RightBotX_F [21:11] RW Specifies the horizontal screen coordinate for the Right 
Bottom pixel of OSD image. 0 
OSD_RightBotY_F [10:0] RW Specifies the vertical screen coordinate for the Right 
Bottom pixel of OSD image. 0 
NOTE: Registers must contain word boundary X position. Therefore, ensure that: 
  24-bpp mode contains X position by 1 pixel (for example, X = 0, 1, 2, 3….) 
  16-bpp mode contains X position by 2 pixel (for example, X = 0, 2, 4, 6….) 
  8-bpp mode contains X position by 4 pixel (for example, X = 0, 4, 8, 12….) 
 
15.5.2.19 VIDOSD2C 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0068, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA0_R_H_F=[23:20]=RW=Specifies the upper value of Red Alpha=(case AEN====
0).=0=
ALPHA0_G_H_F=[19:16]=RW=Specifies the upper value of=Green Alpha (case AEN ===
0).=0=
ALPHA0_B_H_F=[15:12]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
0).=0=
ALPHA1_R_H_F=[11:8]=RW=Specifies the upper value of=Red Alpha (case AEN ===
1).=0=
ALPHA1_G_H_F=[7:4]=RW=Specifies the upper value of=Green Alpha (case AEN ===
1).=0=
ALPHA1_B_H_F=[3:0]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
1).=0=
NOTE: Refer to VIDW2ALPHA0, 1 register, for more information.
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Exynos 5250_UM 15 Display Controller 
 15-82  
15.5.2.20 VIDOSD2D 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x006C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved (should be 0)=0=
OSDSIZb=[25:0]=RW=Specifies the Window Size.=
For=example,=Height= W idth (number of words) 0 
 
15.5.2.21 VIDOSD3A 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0070, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_LeftTopX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopX_F [21:11] RW Specifies the horizontal screen coordinate for the Left 
Top pixel of OSD image. 0 
OSD_LeftTopY_F [10:0] RW Specifies the vertical screen coordinate for the Left Top 
pixel of OSD image. 0
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Exynos 5250_UM 15 Display Controller 
 15-83  
15.5.2.22 VIDOSD3B 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0074, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_RightBotX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotX_ 
F [21:11] RW Specifies the horizontal screen coordinate for the Right 
Bottom pixel of OSD image. 0 
OSD_RightBotY_F [10:0] RW Specifies the vertical screen coordinate for the Right 
Bottom pixel of OSD image. 0 
NOTE: Registers must contain word boundary X position.  
Therefore, ensure that the:  
  24-bpp mode contains X position by 1 pixel (for example, X = 0, 1, 2, 3….) 
  16-bpp mode contains X position by 2 pixels (for example, X = 0, 2, 4, 6….) 
  8-bpp mode contains X position by 4 pixels (for example, X = 0, 4, 8, 12….) 
 
15.5.2.23 VIDOSD3C 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0078, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA0_R_H_F=[23:20]=RW=Specifies the upper value of Red=Alpha=(case AEN == 
0).=0=
ALPHA0_G_H_F=[19:16]=RW=Specifies the upper value of=Green Alpha (case AEN ===
0).=0=
ALPHA0_B_H_F=[15:12]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
0).=0=
ALPHA1_R_H_F=[11:8]=RW=Specifies the upper value of=Red Alpha (case AEN ===
1).=0=
ALPHA1_G_H_F=[7:4]=RW=Specifies the upper value of=Green Alpha (case AEN ===
1).=0=
ALPHA1_B_H_F=[3:0]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
1).=0=
NOTE: Refer to VIDW3ALPHA0, 1 register for more information.
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    							Samsung Confidential  
Exynos 5250_UM 15 Display Controller 
 15-84  
15.5.2.24 VIDOSD4A 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0080, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_LeftTopX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for 
the Left Top pixel of OSD image. 0 
OSD_LeftTopX_F [21:11] RW Specifies the horizontal screen coordinate for the Left 
Top pixel of OSD image. 0 
OSD_LeftTopY_F [10:0] RW Specifies the vertical screen coordinate for the Left Top 
pixel of OSD image. 0 
 
15.5.2.25 VIDOSD4B 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0084, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
OSD_RightBotX_ 
F_E [23] RW Specifies the extended horizontal screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotY_ 
F_E [22] RW Specifies the extended vertical screen coordinate for 
the Right Bottom pixel of OSD image. 0 
OSD_RightBotX_ 
F [21:11] RW Specifies the horizontal screen coordinate for the Right 
Bottom pixel of OSD image. 0 
OSD_RightBotY_F [10:0] RW Specifies the vertical screen coordinate for the Right 
Bottom pixel of OSD image. 0 
NOTE: Registers must contain word boundary X position.  
Therefore, ensure that the:  
  24-bpp mode contains X position by 1 pixel (for example, X = 0, 1, 2, 3….) 
  16-bpp mode contains X position by 2 pixels (for example, X = 0, 2, 4, 6….) 
  8-bpp mode contains X position by 4 pixels (for example, X = 0, 4, 8, 12….)
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Exynos 5250_UM 15 Display Controller 
 15-85  
15.5.2.26 VIDOSD4C 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0088, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [24] –=Reserved=0=
ALPHA0_R_H_F=[23:20]=RW=Specifies the upper value of Red Alpha=(case AEN ===
0).=0=
ALPHA0_G_H_F=[19:16]=RW=Specifies the upper value of=Green Alpha (case AEN ===
0).=0=
ALPHA0_B_H_F=[15:12]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
0).=0=
ALPHA1_R_H_F=[11:8]=RW=Specifies the upper value of=Red Alpha (case AEN ===
1).=0=
ALPHA1_G_H_F=[7:4]=RW=Specifies the upper value of=Green Alpha (case AEN ===
1).=0=
ALPHA1_B_H_F=[3:0]=RW=Specifies the upper value of=Blue Alpha (case AEN == 
1).=0=
NOTE: Refer to VIDW4ALPHA0, 1 register, for more information.
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Exynos 5250_UM 15 Display Controller 
 15-86  
15.5.2.27 VIDWxxADD0n (n = 0 to 2) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x00A0, 0x00A4, 0x20A0, 
Reset Value = 0x0000_0000 (VIDW00ADD0B0, VIDW00ADD0B1, VIDW00ADD0B2) 
 Address = Base Address + 0x00A8, 0x00AC, 0x20A8, 
Reset Value = 0x0000_0000 (VIDW01ADD0B0, VIDW01ADD0B1, VIDW01ADD0B2) 
 Address = Base Address + 0x00B0, 0x00B4, 0x20B0, 
Reset Value = 0x0000_0000 (VIDW02ADD0B0, VIDW02ADD0B1, VIDW02ADD0B2) 
 Address = Base Address + 0x00B8, 0x00BC, 0x20B8, 
Reset Value = 0x0000_0000 (VIDW03ADD0B0, VIDW03ADD0B1, VIDW03ADD0B2) 
 Address = Base Address + 0x00C0, 0x00C4, 0x20C0, 
Reset Value = 0x0000_0000 (VIDW04ADD0B0, VIDW04ADD0B1, VIDW04ADD0B2) 
Name Bit Type Description Reset Value 
VBASEU_F [31:0] RW Specifies A[31:0] of the start address for Video frame buffer. 0 
 
 
15.5.2.28 VIDWxxADD1n (n = 0 to 2) 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x00D0, 0x00D4, 0x20D0, 
Reset Value = 0x0000_0000 (VIDW00ADD1B0, VIDW00ADD1B1, VIDW00ADD1B2) 
 Address = Base Address + 0x00D8, 0x00DC, 0x20D8, 
Reset Value = 0x0000_0000 (VIDW01ADD1B0, VIDW01ADD1B1, VIDW01ADD1B2) 
 Address = Base Address + 0x00E0, 0x00E4, 0x20E0, 
Reset Value = 0x0000_0000 (VIDW02ADD1B0, VIDW02ADD1B1, VIDW02ADD1B2) 
 Address = Base Address + 0x00E8, 0x00EC, 0x20E8, 
Reset Value = 0x0000_0000 (VIDW03ADD1B0, VIDW03ADD1B1, VIDW03ADD1B2) 
 Address = Base Address + 0x00F0, 0x00F4, 0x20F0, 
Reset Value = 0x0000_0000 (VIDW04ADD1B0, VIDW04ADD1B1, VIDW04ADD1B2) 
Name Bit Type Description Reset Value 
VBASEL_F [31:0] RW 
Specifies A[31:0] of the end address for Video frame buffer.  
VBASEL = VBASEU + (PAGEWIDTH + OFFSIZE)  
(LINEVAL + 1) 
0x0
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Exynos 5250_UM 15 Display Controller 
 15-87  
15.5.2.29 VIDWxxADD2 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0100, 0x0104, 0x0108, 0x010C, 0x0110, 
Reset Value = 0x0000_0000 (VIDW00ADD2, VIDW01ADD2, VIDW 02ADD2, VIDW03ADD2, VIDW04ADD2) 
Name Bit Type Description Reset Value 
OFFSIZE_F_E [27] RW Specifies the extended virtual screen Offset Size 
(number of byte). 0 
PAGEWIDTH_F_E [26] RW Specifies the extended virtual screen Page W idth 
(number of byte). 0 
OFFSIZE_F [25:13] RW 
Specifies the virtual screen Offset Size (number of byte). 
This value defines the difference between address of the 
last byte displayed on the previous video line, and 
address of the first byte to be displayed in the new video 
line. 
Ensure that the OFFSIZE_F contains value that is 
multiple of 4-byte size or 0. 
0 
PAGEWIDTH_F [12:0] RW 
Specifies the virtual screen Page W idth (number of 
byte). 
This value defines the width of view port in the frame. 
Ensure that the PAGEWIDTH contains higher value than 
the burst size. The size must be aligned word boundary. 
0 
NOTE:  Ensure that PAGEWIDTH + OFFSET is double-word aligned (8 bytes).
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Exynos 5250_UM 15 Display Controller 
 15-88  
15.5.2.30 VIDINTCON0 
 Base Address: 0x1440_0000 
 Address = Base Address + 0x0130, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0=
FIFOINTERVAL=[25:20]=RW=Controls=the interval of the FIFO interrupt.=0=
SYSMAINCON=[19]=RW=
Sends=complete interrupt enable bit to Main LCa=
0 = Disables=Interrupt                 ==
1 = Enables Interrupt=
NOTE:=This bit is meaningful if both INTEN and=
I80IFDONE are high.=
0=
SYSSrBCON=[18]=RW=
Sends=complete interrupt enable bit to Sub LCD=
0 = Disables=Interrupt.  = = = = = = = = = = = = = = = ==
1 = Enables Interrupt.=
NOTE: This bit is meaningful if both INTEN and=
I80IFDONE are high.=
0=
I80IFDONb=x17]=RW=
Enables the I80 Interface Interrupt (only=for I80 Interface 
mode).=
0 = Disables=Interrupt.=
1 = Enables Interrupt.=
NOTE: This bit is meaningful if INTEN is high.=
0=
FRAMESEL0=[1S:15]=RW=
Specifies the Video=Frame Interrupt 0=at start of:=
00 = BACK Porch  ==
01 = VSYNC=
10 = ACTIVE =
11 = FRONT Porch=
0=
FRAMESEL1=x14:13]=RW=
Specifies the Video=Frame Interrupt 1 at start of:=
00 = None  ==
01 = BACK Porch  ==
10 = VSYNC==
11 = FRONT Porch=
0=
INTFRMEN=x12]=RW=
Specifies the Video=Frame Interrupt enable control bit.=
0 = Disables=video=frame interrupt=
1 = Enables video=frame interrupt =
NOTE: This bit is significant,=when INTEN is high.=
0=
FIFOSEi=x11:5]=RW=
Specifies the FIFO Interrupt=control=bit.=bach bit contains=
a significance:=
[11] Window 4 control (0 = disables, 1 = enables)=
[10] Window 3 control (0 = disables,=1 = enables)=
[9] t indow 2 control (0 = disables, 1 = enables)=
[8] Reserved=
[7] Reserved=
[6] t indow 1 control (0 = disables, 1 = enables)=
[5] t indow 0 control (0 = disables, 1 = enables) =
NOTE: This bit is significant, when=both INTEN and=
0=
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