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Samsung Exynos 5 User Manual

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Page 486 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-120
5.9.1.99 CLK_SRC_PERIC1
 Base Address: 0x1002_0000
 Address = Base Address + 0x0254, Reset Value = 0x0000_0011
Name Bit Type Description Reset Value
RSVD [31:28] –=Reserved=0x0=
SPI2_SEL=[27:24]=RW=
Control MUX_SPI2, the source clock of SPI2=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001== SCLK_CPLi=...

Page 487 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-121
Name Bit Type Description Reset Value
AUDIO2_SEL [7:4] RW
Control MUX_AUDIO2, the source clock of
AUDIO2
0000 = AUDIOCDCLK2
0001 = XXTI
0010 = SCLK_HDMI24M
0011 = SCLK_DPTXPHY
0100 = SCLK_UHOST20PHY
0101 = SCLK_HDMIPHY
0110 = SCLK_MPLL_USER
0111 = SCLK_EPLL
1000 = SCLK_VPLL
1001 = SCLK_CPLL
Others = Reserved
0x1
AUDIO1_SEL [3:0] RW
Control MUX_AUDIO1, the source clock of
AUDIO1
0000 = AUDIOCDCLK1
0001 = XXTI
0010 =...

Page 488 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-122
5.9.1.100 SCLK_SRC_ISP
 Base Address: 0x1002_0000
 Address = Base Address + 0x0270, Reset Value = 0x0000_0000
Name Bit Type Description Reset Value
RSVD [31:16] –=Reserved=0x0=
PW M_ISm_SEL=x15:12]=RW=
Control MUX_PWM_ISm, the source clock of
PW M_ISm=
0000 = XXTf=
0001 = XXTI=
0010 = SCLK_HDMI24M=
0011 = SCLK_DPTXPHY=
0100 = SCLK_USBHOST20PHY=
0101 = SCLK_HDMIPHY=
0110 = SCLK_MPLL_USEo=
0111 = SCLK_EPLL=
1000 = SCLK_VPLL=
1001==...

Page 489 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-123
Name Bit Type Description Reset Value
0100 = SCLK_USBHOST20PHY
0101 = SCLK_HDMIPHY
0110 = SCLK_MPLL_USER
0111 = SCLK_EPLL
1000 = SCLK_VPLL
1001 = SCLK_CPLL
Others = Reserved

Page 490 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-124
5.9.1.101 CLK_SRC_MASK_TOP
 Base Address: 0x1002_0000
 Address = Base Address + 0x0310, Reset Value = 0x0000_0001
Name Bit Type Description Reset Value
RSVD [31:1] –=Reserved=0x0=
VPLLSRC_MASK=[0]=RW=
Masks output clock of MUX_VPLLSRC=
0 = Masks=
1 = Unmasks=
0x1=
=
5.9.1.102 CLK_SRC_MASK_GSCL
 Base Address: 0x1002_0000
 Address = Base Address + 0x0320, Reset Value = 0x1111_0000
Name Bit Type Description Reset Value
RSVD...

Page 491 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-125
5.9.1.103 CLK_SRC_MASK_DISP1_0
 Base Address: 0x1002_0000
 Address = Base Address + 0x032C, Reset Value = 0x0001_1115
Name Bit Type Description Reset Value
RSVD [31:21] –=Reserved=0x0=
HDMI_MASh=x20]=RW=
Masks output clock of MUX_HDMI=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x19:17]=–=Reserved=0x0=
DP1_EXT_MST=
_VID_MASh=[1S]=RW=
Masks output clock of MUX_DP1_EXT_MST_VIa=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[15:13]=–=Reserved=0x0=...

Page 492 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-126
5.9.1.105 CLK_SRC_MASK_FSYS
 Base Address: 0x1002_0000
 Address = Base Address + 0x0340, Reset Value = 0x1100_1111
Name Bit Type Description Reset Value
RSVD [31:29] –=Reserved=0x0=
USBDRD30_MASh=[28]=RW=
Masks output clock of MUX_USBDRD30=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[31:25]=–=Reserved=0x0=
SATA_MASh=[24]=RW=
Masks output clock of MUX_SATA=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:13]=–=Reserved=0x0=
MMC3_MASh=[12]=RW=
Masks...

Page 493 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-127
5.9.1.107 CLK_SRC_MASK_PERIC0
 Base Address: 0x1002_0000
 Address = Base Address + 0x0350, Reset Value = 0x0100_1111
Name Bit Type Description Reset Value
RSVD [31:25] –=Reserved=0x0=
PW M_MASh=x24]=RW=
Masks output clock of MUX_PWM=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x23:13]=–=Reserved=0x0=
UART3_MASK=[12]=RW=
Masks output clock of MUX_UART3=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART2_MASK=[8]=RW=
Masks output...

Page 494 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-128
5.9.1.108 CLK_SRC_MASK_PERIC1
 Base Address: 0x1002_0000
 Address = Base Address + 0x0354, Reset Value = 0x0111_0111
Name Bit Type Description Reset Value
RSVD [31:25] –=Reserved=0x0=
SPI2_MASh=[24]=RW=
Masks output clock of MUX_SPI2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:21]=–=Reserved=0x0=
SPI1_MASh=[20]=RW=
Masks output clock of MUX_SPI1=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[19:17]=–=Reserved=0x0=
SPI0_MASh=[16]=RW=
Masks output...

Page 495 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-129
5.9.1.109 SCLK_SRC_MASK_ISP
 Base Address: 0x1002_0000
 Address = Base Address + 0x0370, Reset Value = 0x0000_1111
Name Bit Type Description Reset Value
RSVD [31:13] –=Reserved=0x0=
PW M_ISm_MASh=[12]=RW=
Masks output clock of MUX_PWM_ISm=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART_ISP_MASh=[8]=RW=
Masks output clock of MUX_UART_ISP=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
SPI1_ISP_MASh=[4]=RW=...

Page 496 Samsung Confidential
Exynos 5250_UM 5 Clock Controller
5-130
5.9.1.110 CLK_MUX_STAT_TOP0
 Base Address: 0x1002_0000
 Address = Base Address + 0x0410, Reset Value = 0x1011_1100
Name Bit Type Description Reset Value
RSVD [31] –=Reserved=0x0=
ACLK_300_GSCi=
_MID_SEL=[30:28]=o=
Selection signal status of=MUX_ACLK_300_GSCL_=
MIa=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLL_USER=
1xx = On changing=
0x1=
RSVD=[27]=–=Reserved=0x0=
ACLK_300_GSCi=
_SEL=[26:24]=o=
Selection signal status of=MUX_ACLK_300=...

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Exynos 5250_UM 5 Clock Controller 
 5-125  
5.9.1.103 CLK_SRC_MASK_DISP1_0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x032C, Reset Value = 0x0001_1115 
Name Bit Type Description Reset Value 
RSVD [31:21] –=Reserved=0x0=
HDMI_MASh=x20]=RW=
Masks output clock of MUX_HDMI=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x19:17]=–=Reserved=0x0=
DP1_EXT_MST=
_VID_MASh=[1S]=RW=
Masks output clock of MUX_DP1_EXT_MST_VIa=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[15:13]=–=Reserved=0x0=
MIPI1_MASK=[12]=RW=
Masks output clock of MUX_MIPI1=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:1]=–=Reserved=0x0=
FIMD1_MASK=[0]=RW=
Masks output clock of MUX_FIMD1=
0 = Masks=
1 = Unmasks=
0x1=
=
5.9.1.104 CLK_SRC_MASK_MAU 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0334, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
AUDIO0_MASh=[0]=RW=
Masks output clock of MUX_AUDIO0=
0 = Masks=
1 = Unmasks=
0x1=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-126  
5.9.1.105 CLK_SRC_MASK_FSYS 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0340, Reset Value = 0x1100_1111 
Name Bit Type Description Reset Value 
RSVD [31:29] –=Reserved=0x0=
USBDRD30_MASh=[28]=RW=
Masks output clock of MUX_USBDRD30=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[31:25]=–=Reserved=0x0=
SATA_MASh=[24]=RW=
Masks output clock of MUX_SATA=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:13]=–=Reserved=0x0=
MMC3_MASh=[12]=RW=
Masks output clock of MUX_MMC3=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
MMC2_MASh=[8]=RW=
Mask output clock of=MUX_MMC2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
MMC1_MASh=[4]=RW=
Masks output clock of MUX_MMC1=
0 ==Masks=
1 = Unmasks=
0x1=
RSVD=[3:1]=–=Reserved=0x0=
MMC0_MASh=[0]=RW=
Masks output clock of MUX_MMC0=
0 = Masks=
1 = Unmasks=
0x1=
=
5.9.1.106 CLK_SRC_MASK_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0344, Reset Value = 0x0000_0001 
Name Bit Type Description Reset Value 
RSVD [31:1] –=Reserved=0x0=
JPEG_MASh=x0]=RW=
Masks output clock of MUX_JPEG=
0 = Masks=
1 = Unmasks=
0x1=
=

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Exynos 5250_UM 5 Clock Controller 
 5-127  
5.9.1.107 CLK_SRC_MASK_PERIC0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0350, Reset Value = 0x0100_1111 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
PW M_MASh=x24]=RW=
Masks output clock of MUX_PWM=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=x23:13]=–=Reserved=0x0=
UART3_MASK=[12]=RW=
Masks output clock of MUX_UART3=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART2_MASK=[8]=RW=
Masks output clock of MUX_UART2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
UART1_MASK=[4]=RW=
Masks output=clock of MUX_UART1=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[3:1]=–=Reserved=0x0=
UART0_MASK=[0]=RW=
Masks output clock of MUX_UART0=
0 = Masks=
1 = Unmasks=
0x1=
=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-128  
5.9.1.108 CLK_SRC_MASK_PERIC1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0354, Reset Value = 0x0111_0111 
Name Bit Type Description Reset Value 
RSVD [31:25] –=Reserved=0x0=
SPI2_MASh=[24]=RW=
Masks output clock of MUX_SPI2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[23:21]=–=Reserved=0x0=
SPI1_MASh=[20]=RW=
Masks output clock of MUX_SPI1=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[19:17]=–=Reserved=0x0=
SPI0_MASh=[16]=RW=
Masks output clock of MUX_SPI0=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[15:9]=–=Reserved=0x0=
SPDIF_MASK=[8]=RW=
Mask output clock of=MUX_SPDIc=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
AUDIO2_MASh=[4]=RW=
Masks output clock of MUX_AUDIO2=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[3:1]=–=Reserved=0x0=
AUDIO1_MASh=[0]=RW=
Masks output clock of MUX_AUDIO1=
0 = Masks=
1 = Unmasks=
0x1=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-129  
5.9.1.109 SCLK_SRC_MASK_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0370, Reset Value = 0x0000_1111 
Name Bit Type Description Reset Value 
RSVD [31:13] –=Reserved=0x0=
PW M_ISm_MASh=[12]=RW=
Masks output clock of MUX_PWM_ISm=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[11:9]=–=Reserved=0x0=
UART_ISP_MASh=[8]=RW=
Masks output clock of MUX_UART_ISP=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[7:5]=–=Reserved=0x0=
SPI1_ISP_MASh=[4]=RW=
Masks output clock of MUX_SPI1_ISP=
0 = Masks=
1 = Unmasks=
0x1=
RSVD=[3:1]=–=Reserved=0x0=
SPI0_ISP_MASh=[0]=RW=
Masks output=clock of MUX_SPI0_ISP=
0 = Masks=
1 = Unmasks=
0x1=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-130  
5.9.1.110 CLK_MUX_STAT_TOP0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0410, Reset Value = 0x1011_1100 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_GSCi=
_MID_SEL=[30:28]=o=
Selection signal status of=MUX_ACLK_300_GSCL_=
MIa=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLL_USER=
1xx = On changing=
0x1=
RSVD=[27]=–=Reserved=0x0=
ACLK_300_GSCi=
_SEL=[26:24]=o=
Selection signal status of=MUX_ACLK_300=
001==ACLK_300_GSCL_MID=
010 =ACLK_300_GSCL_MID1=
1xx = On changing=
0x1=
RSVD=[23]=–=Reserved=0x0=
ACLK_400_G3D_M
ID_SEi=[22:20]=o=
Selection signal status of=
MUX_ACLK_400_G3D_MIa=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
ACLK_333_SEL=[18:16]=o=
Selection signal status of=MUX_ACLK_333=
001 = SCLK_CPLi=
010 = SCLK_MPLL_USER=
1xx = On changing=
0x1=
RSVD=[15]=–=Reserved=0x0=
ACLK_200_SEL=[14:12]=o=
Selection signal status of=MUX_ACLK_200=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=[11]=–=Reserved=0x0=
ACLK_16S_SEL=x10:8]=o=
Selection signal status of=MUX_ACLK_16S=
001 = SCLK_CPLi=
010 = SCLK_MPLL_USER=
1xx = On changing=
0x1=
RSVD=[7]=–=Reserved=0x0=
ACLK_300_DISP1=
_MID_SEi=x6:4]=o=
Selection signal status of=MUX_ACLK_300_DISP1=
_MID=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=x3]=–=Reserved=0x0=

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Exynos 5250_UM 5 Clock Controller 
 5-131  
Name Bit Type Description Reset Value 
ACLK_300_DISP1 
_SEL [2:0] R 
Selection signal status of MUX_ACLK_300_DISP1 
001 = ACLK_300_DISP1_MID 
010 = ACLK_300_DISP1_MID1 
1xx = On changing 
0x1

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Exynos 5250_UM 5 Clock Controller 
 5-132  
5.9.1.111 CLK_MUX_STAT_TOP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0414, Reset Value = 0x1111_1100 
Name Bit Type Description Reset Value 
RSVD [31:27] –=Reserved=0x0=
ACLK_400_G3D_S
EL=[30:28]=o=
Selection signal status of=MUX_ACLK_400_G3D=
001 = MUX_ACLK_400_G3D_MID=
010 = MUX_ACLK_400_G3D_MID1=
1xx = On changing=
0x1=
RSVD=[31:27]=–=Reserved=0x0=
ACLK_400_ISP=
_SEL=x26:24]=o=
Selection signal status of=MUX_ACLK_400_ISP=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=x23]=–=Reserved=0x0=
ACLK_400_IOm=
_SEi=[22:20]=o=
Selection signal status of=MUX_ACLK_400_IOm=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
ACLK_MIPI_HSI=
_TXBASE_SEi=[18:16]=o=
Selection signal status of=MUX_ACLK_MIPI_HSI_=
TXBASE=
001 = SCLK_MPLL_USER=
010 = SCLK_BPLi_USEo=
1xx = On changing=
0x1=
RSVD=[15]=–=Reserved=0x0=
ACLK_300_GSCL_
MID1_SEL=x14:12]=o=
Selection signal status of=
MUX_ACLK_300_GSCL_MID1=
001 = SCLK_VPLi=
010 = SCLK_CPLi=
1xx = On changing=
0x1=
RSVD=x11]=–=Reserved=0x0=
ACLK_300_DISP1_
MID1_SEL=x10:8]=o=
Selection signal status of=
MUX_ACLK_300_DISP1_MID1=
001 = SCLK_VPLi=
010 = SCLK_CPLi=
1xx = On changing=
0x1=
RSVD=x7:0]=–=Reserved=0x0=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-133  
5.9.1.112 CLK_MUX_STAT_TOP2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0418, Reset Value = 0x1111_1100 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
GPLL_SEi=x30:28]=o=
Selection signal status of=MUX_GPLL=
001 = XXTI=
010 = FOUT_GPLi=
1xx = On changing=
0x1=
RSVD=[31:27]=–=Reserved=0x0=
BPLL_USEo_SEL=x26:24]=o=
Selection signal status of=MUX_BPLL_USEo=
001 = XXTI=
010 = SCLK_BPLi=
1xx = On changing=
0x1=
RSVD=x23]=–=Reserved=0x0=
MPLL_USEo_SEL=x22:20]=o=
Selection signal status of=MUX_MPLL_USEo=
001 = XXTI=
010 = SCLK_MPLi=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
VPLL_SEL=x18:17]=o=
Selection signal status of=MUX_VPLL=
001 = XXTI=
010 = FOUT_VPLi=
1xx = On changing=
0x1=
RSVD=[15]=–=Reserved=0x0=
EPLL_SEL=x14:12]=o=
Selection signal status of=MUX_EPLL=
001 = XXTI=
010 = FOUT_EPLi=
1xx = On changing=
0x1=
RSVD=[11]=–=Reserved=0x0=
CPLL_SEL=x10:8]=o=
Selection signal status of=MUX_CPLL=
001 = XXTI=
010 = FOUT_CPLi=
1xx = On changing=
0x1=
RSVD=x7:0]=–=Reserved=0x0=
=
=

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Exynos 5250_UM 5 Clock Controller 
 5-134  
5.9.1.113 CLK_MUX_STAT_TOP3 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x041C, Reset Value = 0x1111_1111 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_GSCi=
_SUB_SEL=[30:28]=o=
Selection signal status of=MUX_ACLK_300_GSCi=
001== XXTI=
010 = ACLK_300_GSCi=
1xx = On changing=
0x1=
RSVD=x27]=–=Reserved=0x0=
ACLK_333_SUB=
_SEL=x26:24]=o=
Selection signal status of=MUX_ACLK_333_SUB=
001 = XXTI=
010 = ACLK_333=
1xx = On changing=
0x1=
RSVD=x23]=–=Reserved=0x0=
ACLK_400_ISP=
_SUB_SEL=x22:20]=o=
Selection signal status of=MUX_ACLK_400_ISP=
_SUB=
001 = XXTI=
010 = ACLK_400_ISP=
1xx = On changing=
0x1=
RSVD=[19]=–=Reserved=0x0=
ACLK_266_ISP=
_SUB_SEL=x18:16]=o=
Selection signal status of=MUX_ACLK_266_ISP=
_SUB=
001 = XXTI=
010 = ACLK_266_ISP=
1xx = On changing=
0x1=
RSVD=[15:11]=–=Reserved=0x0=
ACLK_266_GSCi=
_SUB_SEL=x10:8]=o=
Selection signal status of=MUX_ACLK_266_GSCL 
_SUB=
001 = XXTI=
010 = ACLK_266_GSCi=
1xx = On changing=
0x1=
RSVD=x7]=–=Reserved=0x0=
ACLK_200_DISP1=
_SUB_SEL=xS:4]=o=
Selection signal status of=MUX_ACLK_200_DISP1=
_SUB=
001 = XXTI=
010 = ACLK_200_DISP1=
1xx = On changing=
0x1=
RSVD=x3]=–=Reserved=0x0=
ACLK_300_DISP1=
_SUB_SEL=x2:0]=o=
Selection signal status of=MUX_ACLK_300_DISP1=
_SUB=
001 = XXTI=
010 = ACLK_300_DISP1=
1xx = On changing=
0x1=

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