Samsung Exynos 5 User Manual

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-7  
10.3.3 Auto-Reload and Double Buffering 
The PWM Timers includes a double buffering feature, which changes the reload value for the next Timer operation 
without stopping the current Timer operation.  
The Timer value is written into TCNTBn (Timer Count Buffer register) and the current counter value of the Timer is 
read from TCNTOn (Timer Count Observation register). If TCNTBn is Read, the Read value does not reflect the 
current state of the counter. It reflects the reload value for the next Timer duration. 
Auto-reload copies the TCNTBn into TCNTn, when TCNTn reaches 0. The value written to TCNTBn, is loaded to 
TCNTn when the TCNTn reaches 0 and auto-reload is enabled. When the TCNTn is 0 and the auto-reload bit is 0, 
the TCNTn does not operate further. 
Figure 10-4 illustrates an example of Double-Buffering: 
 
    Figure 10-4   Double Buffering 
 
 
 W rite
TCNTBn=100W rite
TCNTBn=200Start
auto_reload
TCNTBn=150
150200100100
interrupt
 
If TCNT is 0, interrupt signal isgenerated and then load the nextTCNTB  
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-8  
10.3.4 Timer Operation  
Figure 10-5 illustrates an example of Timer Operation: 
 
    Figure 10-5   Timer Operation 
Steps in Timer Operation: 
1. Enable the Auto-reload feature. Set the TCNTBn as 159 (50 + 109) and TCMPBn as 109. Set the manual  
 update bit On and set the manual update bit Off. Set the inverter On/Off bit. The manual update bit sets  
 TCNTn and TCMPn to the value of TCNTBn and TCMPBn.  
2. Set TCNTBn and TCMPBn as 79 (40 + 39) and 39, respectively. 
3. Start Timer: Set the start bit in TCON. 
4. When TCNTn and TCMPn have the same value, the logic level of TOUTn is changed from low to high. 
5. When TCNTn reaches 0, it generates interrupt request. 
6. TCNTn and TCMPn are automatically reloaded with TCNTBn and TCMPBn as (79 (40 + 39)) and 39,  
 respectively. In the Interrupt Service Routine (ISR), the TCNTBn and TCMPBn are set as 79 (20 + 59) 
 and 59, respectively. 
7. When TCNTn and TCMPn have the same value, the logic level of TOUTn is changed from low to high 
8. When TCNTn reaches 0, it generates interrupt request. 
9. TCNTn and TCMPn are automatically reloaded with TCNTBn and TCMPBn as (79 (20 + 59)) and 59,  
 respectively. The Auto-reload and interrupt request are disabled to stop the Timer in the ISR.  
10. When TCNTn and TCMPn have the same value, the logic level of TOUTn is changed from low to high  
11. Even if TCNTn reaches 0, no interrupt request is generated. 
12. TCNTn is not reloaded and the Timer is stopped because Auto-reload is disabled. TOUTn
1234
5
67
8
910
50109
110
4039
40
20
60
59
11
   
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-9  
10.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) 
User must define the starting value of the TCNTn, because an Auto-reload operation of the Timer occurs when the 
down counter reaches 0. In this case, the starting value must be loaded by manual update bit.  
The sequence to start a Timer is: 
1. Write the initial value into TCNTBn and TCMPBn. 
2. Set the manual update bit and clear only manual update bit of the corresponding Timer. 
NOTE: It is recommended to set the inverter On/Off bit (whether inverter is used or not).  
 
3. Set the start bit of the corresponding Timer to start the Timer.  
 
10.3.6 PWM (Pulse Width Modulation) 
Figure 10-5 illustrates an example of PWM: 
 
    Figure 10-6   PWM 
Use TCMPBn to implement the Pulse W idth Modulation (PWM) feature. PWM frequency is determined by 
TCNTBn. A PW M value is determined by TCMPBn as shown in the Figure 10-6.  
For a higher PWM value, decrease the TCMPBn value. For a lower PWM value, increase the TCMPBn value. 
When the output inverter is enabled, the increment/ decrement can be reverse. 
Due to the Double Buffering feature, TCMPBn, for a next PWM cycle is written by ISR at any point of current PW M 
cycle. Write TCMPBn=60
Write TCMPBn=50
Write TCMPBn=40
Write TCMPBn=30
Write TCMPBn=30
Write TCMPBn
= next PWM
6050403030  
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-10  
10.3.7 Output Level Control 
Figure 10-7 illustrates an example of inverter On/Off: 
 
    Figure 10-7   Inverter On/Off 
Steps to maintain TOUT as high or low (assume that inverter is off): 
1. Turn-off the Auto-reload bit. The TOUTn goes to high level and the Timer is stopped after TCNTn reaches 0.  
 This method is recommended. 
2. Stop the timer by clearing the timer start/stop bit to 0. When TCNTn TCMPn, the output level is low. 
3. TOUTn is inverted by the inverter on/off bit in TCON. The inverter removes the additional circuit to adjust  
 the output level. 
 
 
 Initial State
Inverter off
Inverter on
Timer stopPeriod 2Period 1
   
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-11  
10.3.8 Dead Zone Generator 
This feature inserts the time gap between a Turn-off and Turn-on of two different switching devices. This time gap 
prohibits the two switching device turning on simultaneously, even for a very short time. 
TOUT_0 specifies the PWM output. nTOUT_0 specifies the inversion of the TOUT_0. When the dead-zone is 
enabled, the output wave-form of TOUT_0 and nTOUT_0 is TOUT_0_DZ and nTOUT_0_DZ, respectively. 
TOUT0_DZ and nTOUT_0_DZ cannot be turned on simultaneously by the dead zone interval. For functional 
correctness, the dead zone length must be set smaller than compare counter value. 
Figure 10-8 illustrates the waveform when a dead zone feature is enabled: 
 
    Figure 10-8   Waveform when a Dead Zone Feature is Enabled 
 
 
 TOUT0
nTOUT0
DEADZONE
INTERVAL
TOUT0_DZ
nTOUT0_DZ
   
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-12  
10.4 I/O Description 
Signal I/O Description Pad Type 
TOUT_0 Output PW MTIMER TOUT[0] XpwmTOUT[0] muxed 
TOUT_1 Output PW MTIMER TOUT[1] XpwmTOUT[1] muxed 
TOUT_2 Output PW MTIMER TOUT[2] XpwmTOUT[2] muxed 
TOUT_3 Output PW MTIMER TOUT[3] XpwmTOUT[3] muxed 
NOTE: Type field indicates whether pads are dedicated to the signal, or pads are connected to the multiplexed signals.  
 
 
 
 
  
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-13  
10.5 Register Description 
10.5.1 Register Map Summary 
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
Register Offset Description Reset Value 
TCFG0 0x0000 Specifies the timer configuration register 0 that configures the 
two 8-bit prescaler and dead zone length 0x0000_0101 
TCFG1 0x0004 Specifies the timer configuration register 1 that controls 5 MUX 
select bit 0x0000_0000 
TCON 0x0008 Specifies the timer control register. 0x0000_0000 
TCNTB0 0x000C Specifies the timer 0 count buffer register 0x0000_0000 
TCMPB0 0x0010 Specifies the timer 0 compare buffer register 0x0000_0000 
TCNTO0 0x0014 Specifies the timer 0 count observation register 0x0000_0000 
TCNTB1 0x0018 Specifies the timer 1 count buffer register 0x0000_0000 
TCMPB1 0x001C Specifies the timer 1 compare buffer register 0x0000_0000 
TCNTO1 0x0020 Specifies the timer 1 count observation register 0x0000_0000 
TCNTB2 0x0024 Specifies the timer 2 count buffer register 0x0000_0000 
TCMPB2 0x0028 Specifies the timer 2 compare buffer register 0x0000_0000 
TCNTO2 0x002C Specifies the timer 2 count observation register 0x0000_0000 
TCNTB3 0x0030 Specifies the timer 3 count buffer register 0x0000_0000 
TCMPB3 0x0034 Specifies the timer 3 compare buffer register 0x0000_0000 
TCNTO3 0x0038 Specifies the timer 3 count observation register 0x0000_0000 
TCNTB4 0x003C Specifies the timer 4 count buffer register 0x0000_0000 
TCNTO4 0x0040 Specifies the timer 4 count observation register 0x0000_0000 
TINT_CSTAT 0x0044 Specifies the timer interrupt control and status register 0x0000_0000 
 
  
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-14  
10.5.1.1 TCFG0  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0000, Reset Value = 0x0000_0101 
Name Bit  Type Description Reset Value 
RSVD [31:24] –=Reserved Bits=0x00=
Dead zone length=[23:16]=RW=Dead Zone Length==0x00=
Prescaler 1=[15:8]=RW=Prescaler 1=value for Timer=2, 3=and=4=0x01=
Prescaler 0=[7:0]=RW=Prescaler 0=value for Timer 0=and=1=0x01=
=
Timer fnput=Clock Frequency = PCLK/({prescaler value=+ 1})/{divider value}=
{prescaler value} ==1=to=255==
{divider value} = 1,=2,=4,=8,=16==
Dead=wone iength===0=to=254==
NOTE: If Dead Zone Length is set as n, Real Dead Zone Length is n + 1 (n = 0 to 254).  
 
 
 
  
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-15  
10.5.1.2 TCFG1  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0004, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
RSVD [31:20] –=Reserved Bits=0x000=
Divider MUX4=[19:16]=RW=
Selects=MUX input for PWM Timer 4=
0000== 1/1=
0001== 1/2=
0010 = 1/4=
0011== 1/8=
0100 = 1/1S=
0x0=
Divider MUX3=[15:12]=RW=
Selects=MUX input for PWM Timer 3=
0000== 1/1=
0001== 1/2=
0010 = 1/4=
0011== 1/8=
0100 = 1/1S=
0x0=
Divider=MUX2=[11:8]=RW=
Selects=MUX input for PWM Timer 2=
0000== 1/1=
0001== 1/2=
0010 = 1/4=
0011== 1/8=
0100 = 1/1S=
0x0=
Divider MUX1=[7:4]=RW=
Selects=MUX input for PWM Timer 1=
0000== 1/1=
0001== 1/2=
0010 = 1/4=
0011== 1/8=
0100 = 1/1S=
0x0=
Divider MUX0=[3:0]=RW=
Selects=MUX input for PWM Timer 0=
0000== 1/1=
0001== 1/2=
0010 = 1/4=
0011== 1/8=
0100 = 1/1S=
0x0=
=
=
= 
						

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Exynos 5250_UM 10 Pulse Width Modulation Timer 
 10-16  
10.5.1.3 TCON  
 Base Address: 0x12DD_0000 (PWM) 
 Base Address: 0x1316_0000 (PWM_ISP) 
 Address = Base Address + 0x0008, Reset Value = 0x0000_0000 
Name Bit  Type Description Reset Value 
RSVD [31:23] –=Reserved Bits=0x000=
Timer 4=auto=
reload on/off =[22]=RW=0===lne-phot=
1== fnterval Mode=(Auto-oeload)=0x0=
Timer 4=manual=
update=[21]=RW=0===No lperation=
1 = rpdates TCNTB4=0x0=
Timer 4=start/stop=[20]=RW=0===ptops=
1== ptarts Timer=4=0x0=
Timer 3 auto=
reload on/off =[19]=RW=0===lne-phot=
1== fnterval Mode=(Auto-oeload)=0x0=
Timer 3=output=
inverter on/off=[18]=RW=0===fnverter lff=
1== TOUT_3=fnverter-ln=0x0=
Timer 3 manual=
update=[17]=RW=0===No lperation=
1== rpdates TCNTB3=0x0=
Timer 3 start/stop=[16]=RW=0===ptops=
1== ptarts Timer 3=0x0=
Timer 2=auto=
reload on/off =[15]=RW=0===lne-phot=
1== fnterval Mode=(Auto-oeload)=0x0=
Timer 2=output=
inverter on/off=[14]=RW=0===fnverter lff=
1== TOUT_2=fnverter-ln=0x0=
Timer 2=manual=
update=[13]=RW=0===No lperation=  =
1 = rpdates TCNTB2,TCMPB2=0x0=
Timer 2=start/stop=[12]=RW=0===ptops  =
1== ptarts Timer=2=0x0=
Timer 1=auto=
reload on/off =[11]=RW=0===lne-phot==
1== fnterval Mode=(Auto-oeload)=0x0=
Timer 1=output=
inverter on/off=[10]=RW=0===fnverter lff=
1== TOUT_1=fnverter-ln=0x0=
Timer 1=manual=
update=[9]=RW=0===No lperation=  =
1 = rpdates TCNTB1,=TCMPB1=0x0=
Timer 1=start/stop=[8]=RW=0===ptops  =
1== ptarts Timer=1=0x0=
Reserved=[7:5]=RW=Reserved Bits=0x0=
Dead=zone=
enable/disable==[4]=RW=Dead=wone denerator=bnable/aisable=0x0=
Timer 0=auto=
reload on/off =[3]=RW=0===lne-phot=
1== fnterval Mode=(Auto-oeload)=0x0=
Timer 0=output=[2]=RW=0===fnverter lff=0x0=