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Samsung Exynos 5 User Manual

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Exynos 5250_UM 7 Interrupt Combiner 
 7-23  
7.5.1.15 ISTR3 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0038, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31:28] –=Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
MDMA0_ABORT=[27]=o=–=
RSVD=[2S:10]=–=–=
MDMA1_ABORT=[9]=o=–=
RSVD=[8:0]=–=–=
=
7.5.1.16 IMSR3 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x003C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Masked interrupt=pending status=
If the corresponding interrupt enable bit is=0,=
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
MDMA0_ABORT=[27]=o=–=
RSVD=[2S:10]=–=–=
MDMA1_ABORT=[9]=o=–=
RSVD=[8:0]=–=–=
=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-24  
7.5.1.17 IESR4 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0040, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
CPU_nRAMERRIRQ [31] RW Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the 
interrupt request is served. 
Write 
0 = Does not change the current setting 
1 = Sets the interrupt enable bit to 1 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
CPU_nAXIERRIRQ [30] RW 0 
RSVD [29] –=–=
INT_COMB_ISP_GIC=[28]=RW=0=
INT_COMB_IOP_GIC=[27]=RW=0=
CCI_nERRORIRn=[26]=RW=0=
INT_COMB_ARMISP_GIC=[25]=RW=0=
INT_COMB_ARMIOP_GIC=[24]=RW=0=
DISP1[3]=[23]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
DISP1[2]=[22]=RW=0=
DISP1[1]=[21]=RW=0=
DISP1[0]=[20]=RW=0=
RSVD=[19]=–=–=
RSVD=[18]=–=–=
RSVD=[17]=–=–=
RSVD=x16]=–=–=
RSVD=[15:12]=–=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
SSCM_PLUSE_IRQ=
_C2CIF[1]=[11]=RW=0=
SSCM_PULSE_IRQ=
_C2CIF[0]=[10]=RW=0=
SSCM_IRQ_C2CIF[1]=[9]=RW=0=
SSCM_IRQ_C2CIF[0]=[8]=RW=0=
RSVD=[7]=–=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
RSVD=[6]=–=–=
RSVD=[5]=–=–=
RSVD=[4]=–=–=
PEREV_M1_CDREX=[3]=RW=0=
PEREV_M0_CDREX=[2]=RW=0=
PEREV_A1_CDREX=[1]=RW=0=
PEREV_A0_CDREX=[0]=RW=0=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-25  
7.5.1.18 IECR4 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0044, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
CPU_nRAMERRIRQ [31] RW Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0 
Read 
The current interrupt enable bit 
0 = Masks 
1 = Enables 
0 
CPU_nAXIERRIRQ [30] RW 0 
RSVD [29] –=–=
INT_COMB_ISP_GIC=[28]=RW=0=
INT_COMB_IOP_GIC=[27]=RW=0=
CCI_nERRORIRn=[26]=RW=0=
INT_COMB_ARMISP_GIC=[25]=RW=0=
INT_COMB_ARMIOP_GIC=[24]=RW=0=
DISP1[3]=[23]=RW=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
0=
DISP1[2]=[22]=RW=0=
DISP1[1]=[21]=RW=0=
DISP1[0]=[20]=RW=0=
oSVa=[19]=–=–=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
RSVD=[15:12]=–=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
SSCM_PLUSE_IRQ=
_C2CIF[1]=[11]=RW=0=
SSCM_PULSE_IRQ=
_C2CIF[0]=[10]=RW=0=
SSCM_IRQ_C2CIF[1]=[9]=RW=0=
SSCM_IRQ_C2CIF[0]=[8]=RW=0=
RSVD=[7]=–=Clear the corresponding interrupt enable bit to=
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit=
0 = Masks=
1===Enables=
–=
RSVD=[6]=–=–=
RSVD=[5]=–=–=
RSVD=[4]=–=–=
PEREV_M1_CDREX=[3]=RW=0=
PEREV_M0_CDREX=[2]=RW=0=
PEREV_A1_CDREX=[1]=RW=0=
PEREV_A0_CDREX=[0]=RW=0=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-26  
7.5.1.19 ISTR4 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0048, Reset Value = Undefined  
Name Bit Type Description Reset Value 
CPU_nRAMERRIRQ [31] R 
Interrupt pending status 
The corresponding interrupt enable bit does not 
affect this pending status.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
CPU_nAXIERRIRn=[30]=o=–=
RSVD=[29]=–=–=
INT_COMB_ISP_GIC=[28]=o=–=
INT_COMB_IOP_GIC=[27]=o=–=
CCI_nERRORIRn=[26]=o=–=
INT_COMB_ARMISP_GIC=[25]=o=–=
INT_COMB_ARMIOP_GIC=[24]=o=–=
DISP1[3]=[23]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
DISP1[2]=[22]=o=–=
DISP1[1]=[21]=o=–=
DISP1[0]=[20]=o=–=
oSVa=[19]=–=–=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
RSVD=[15:12]=–=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SSCM_PLUSE_IRQ=
_C2CIF[1]=[11]=o=–=
SSCM_PULSE_IRQ=
_C2CIF[0]=[10]=o=–=
SSCM_IRQ_C2CIF[1]=[9]=o=–=
SSCM_IRQ_C2CIF[0]=[8]=o=–=
RSVD=[7]=–=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status. =
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[6]=–=–=
RSVD=[5]=–=–=
RSVD=[4]=–=–=
PEREV_M1_CDREX=[3]=o=–=
PEREV_M0_CDREX=[2]=o=–=
PEREV_A1_CDREX=[1]=o=–=
PEREV_A0_CDREX=[0]=o=–=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-27  
7.5.1.20 IMSR4 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x004C, Reset Value = Undefined 
Name Bit Type Description Reset Value 
CPU_nRAMERRIRQ [31] R 
Masked interrupt pending status 
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.  
0 = The interrupt is not pending 
1 = The interrupt is pending 
–=
CPU_nAXIERRIRn=[30]=o=–=
RSVD=[29]=–=–=
INT_COMB_ISP_GIC=[28]=o=–=
INT_COMB_IOP_GIC=[27]=o=–=
CCI_nERRORIRn=[26]=o=–=
INT_COMB_ARMISP_GIC=[25]=o=–=
INT_COMB_ARMIOP_GIC=[24]=o=–=
DISP1[3]=[23]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
DISP1[2]=[22]=o=–=
DISP1[1]=[21]=o=–=
DISP1[0]=[20]=o=–=
oSVa=[19]=–=–=
oSVa=[18]=–=–=
oSVa=[17]=–=–=
oSVa=x16]=–=–=
RSVD=[15:12]=–=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
SSCM_PLUSE_IRQ=
_C2CIF[1]=[11]=o=–=
SSCM_PULSE_IRQ=
_C2CIF[0]=[10]=o=–=
SSCM_IRQ_C2CIF[1]=[9]=o=–=
SSCM_IRQ_C2CIF[0]=[8]=o=–=
RSVD=[7]=–=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.==
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[6]=–=–=
RSVD=[5]=–=–=
RSVD=[4]=–=–=
PEREV_M1_CDREX=[3]=o=–=
PEREV_M0_CDREX=[2]=o=–=
PEREV_A1_CDREX=[1]=o=–=
PEREV_A0_CDREX=[0]=o=–=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-28  
7.5.1.21 IESR5 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0050, Reset Value = 0x0000_0101 
Name Bit Type Description Reset Value 
RSVD [31] –=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
–=
RSVD=[30]=–=–=
RSVD=[29]=–=–=
MCT_G1=[28]=RW=0=
MCT_G0=[27]=RW=0=
RSVD=[26]=–=–=
RSVD=[25]=–=–=
EINT[0]=[24]=RW=0=
CPU_nCNTVIRQ[1]=[23]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
oead=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
CPU_nCTIIRQ[1]=[22]=RW=0=
CPU_nCNTPSIRQ[1]=[21]=RW=0=
CPU_nPMUIRQ[1]=[20]=RW=0=
CPU_nCNTPNSIRQ[1]=[19]=RW=0=
CPU_PARITYFAILSCU[1]=[18]=RW=0=
CPU_nCNTHPIRQ[1]=[17]=RW=0=
CPU_PARITYFAIL[1]=x16]=RW=0=
RSVD=x15:9]=–=Reserved=0x0=
CPU_nIRQ[1]=[8]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
oead=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
1=
RSVD=[7:1]=–=Reserved=0x0=
CPU_nIRQ[0]=[0]=RW=
Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
oead=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
1=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-29  
7.5.1.22 IECR5 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0054, Reset Value = 0x0000_0101 
Name Bit Type Description Reset Value 
RSVD [31] RW Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked. 
Write 
0 = Does not change the current setting 
1 = Clears the interrupt enable bit to 0 
Read 
The current interrupt enable bit. 
0 = Masks 
1 = Enables 
0 
RSVD [30] –=–=
RSVD=[29]=–=–=
MCT_G1=[28]=RW=0=
MCT_G0=[27]=RW=0=
RSVD=[26]=–=–=
RSVD=[25]=–=–=
EINT[0]=[24]=RW=0=
CPU_nCNTVIRQ[1]=[23]=RW=Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
CPU_nCTIIRQ[1]=[22]=RW=0=
CPU_nCNTPSIRQ[1]=[21]=RW=0=
CPU_nPMUIRQ[1]=[20]=RW=0=
CPU_nCNTPNSIRQ[1]=[19]=RW=0=
CPU_PARITYFAILSCU[1]=[18]=RW=0=
CPU_nCNTHPIRQ[1]=[17]=RW=0=
CPU_PARITYFAIL[1]=x16]=RW=0=
RSVD=x15:9]=–=Reserved=0x0=
CPU_nIRQ[1]=[8]=RW=
Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt is masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
1=
RSVD=[7:1]=–=Reserved=0x0=
CPU_nIRQ[0]=[0]=RW=
Clear the corresponding interrupt enable bit to 
0. If the interrupt enable bit is cleared, the 
interrupt will be masked.=
Write=
0===Does not change the current setting=
1===Clears the interrupt enable bit to 0=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
1=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-30  
7.5.1.23 ISTR5 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0058, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31] –=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[30]=–=–=
RSVD=[29]=–=–=
MCT_G1=[28]=o=–=
MCT_G0=[27]=o=–=
RSVD=[26]=–=–=
RSVD=[25]=–=–=
EINT[0]=[24]=o=–=
CPU_nCNTVIRQ[1]=[23]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
CPU_nCTIIRQ[1]=[22]=o=–=
CPU_nCNTPSIRQ[1]=[21]=o=–=
CPU_nPMUIRQ[1]=[20]=o=–=
CPU_nCNTPNSIRQ[1]=[19]=o=–=
CPU_PARITYFAILSCU[1]=[18]=o=–=
CPU_nCNTHPIRQ[1]=[17]=o=–=
CPU_PARITYFAIL[1]=x16]=o=–=
RSVD=x15:9]=–=Reserved=–=
CPU_nIRQ[1]=[8]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[7:1]=–=Reserved=–=
CPU_nIRQ[0]=[0]=o=
Interrupt pending status=
The corresponding interrupt enable bit does not 
affect this pending status.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-31  
7.5.1.24 IMSR5 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x005C, Reset Value = Undefined  
Name Bit Type Description Reset Value 
RSVD [31] –=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is=0,=
the IMSR bit is=read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[30]=–=–=
RSVD=[29]=–=–=
MCT_G1=[28]=o=–=
MCT_G0=[27]=o=–=
RSVD=[26]=–=–=
RSVD=[25]=–=–=
EINT[0]=[24]=o=–=
CPU_nCNTVIRQ[1]=[23]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
CPU_nCTIIRQ[1]=[22]=o=–=
CPU_nCNTPSIRQ[1]=[21]=o=–=
CPU_nPMUIRQ[1]=[20]=o=–=
CPU_nCNTPNSIRQ[1]=[19]=o=–=
CPU_PARITYFAILSCU[1]=[18]=o=–=
CPU_nCNTHPIRQ[1]=[17]=o=–=
CPU_PARITYFAIL[1]=x16]=o=–=
RSVD=x15:9]=–=Reserved=–=
CPU_nIRQ[1]=[8]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR=bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
RSVD=[7:1]=–=Reserved=–=
CPU_nIRQ[0]=[0]=o=
Masked interrupt=pending status=
If the corresponding interrupt enable bit is 0, 
the IMSR bit is read out as 0.=
0===The interrupt is not pending=
1===The interrupt is pending=
–=
=
=
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Exynos 5250_UM 7 Interrupt Combiner 
 7-32  
7.5.1.25 IESR6 
 Base Address: 0x1044_0000 for main CPU and 0x1045_0000 for IOP 
 Address = Base Address + 0x0060, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:26] –=Reserved=0x0=
EINTx7]=[25]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx6]=[24]=RW=0=
RSVD=x23:18]=–=Reserved=0x0=
EINTx5]=x17]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
EINTx4]=x16]=RW=0=
RSVD=x15:12]=–=Reserved=0x0=
MCT_G3=[11]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0 = Masks=
1===Enables=
0=
MCT_G2=[10]=RW=0=
EINTx3]=x9]=RW=0=
EINTx2]=x8]=RW=0=
RSVD=x7]=–=Reserved=0x0=
pYSMMU_G2D[1]=xS]=RW=Sets the corresponding interrupt enable bit to 
1. If the interrupt enable bit is set to 1, the=
interrupt request is served.=
Write=
0===Does not change the current setting=
1===Sets the interrupt enable bit to 1=
Read=
The current interrupt enable bit.=
0=
pYSMMU_G2D[0]=x5]=RW=0=
RSVD=x4:3]=–=0=
pYSMMU_FIMC_LITE1[1]=x2]=RW=0=
pYSMMU_FIMC_LITE1[0]=x1]=RW=0=
EINTx1]=x0]=RW=0=
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