Samsung Exynos 5 User Manual

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-135  
5.9.1.114 CLK_DIV_TOP0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0510, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_300_DISP1_
RATIl=x30:28]=RW=
DIV_ACLK_300_DISP1=clock divider Ratio=
ACLK_300_DISP1=
= 
MOUT_ACLK_300_DISP1/(ACLK_300_DISP1_RA
TIO + 1)=
0x0=
RSVD=x27]=–=Reserved=0x0=
ACLK_400_G3D_o
ATIO=x26:24]=RW=
DIV_ACLK_400_G3D=clock divider Ratio=
ACLK_400_G3D=
= 
MOUT_ACLK_400_G3D/(ACLK_400_G3D_RATIO=
+ 1)=
0x0=
RSVD=x23]=–=Reserved=0x0=
ACLK_333_RATIO=x22:20]=RW=
DIV_ACLK_333=clock divider Ratio=
ACLK_333=
= MOUT_ACLK_333/(ACLK_333_RATIO + 1)=
0x0=
RSVD=x19]=–=Reserved=0x0=
ACLK_266_RATIO=x18:16]=RW=
DIV_ACLK_266=clock divider Ratio=
ACLK_266=
= MOUT_MPLL_USER/(ACLK_266_RATIO + 1)=
0x0=
RSVD=x15]=–=Reserved=0x0=
ACLK_200_RATIO=[14:12]=RW=
DIV_ACLK_200=clock divider Ratio=
ACLK_200=
= MOUT_ACLK_200/(ACLK_200_RATIO + 1)=
0x0=
RSVD=[11]=–=Reserved=0x0=
ACLK_16S_RATIO=[10:8]=RW=
DIV_ACLK_1SS=clock divider Ratio=
ACLK16S=
= MOUT_ACLK_166/(ACLK_1SS_RATIO + 1)=
0x0=
RSVD=x7:3]=–=Reserved=0x0=
ACLK_66_RATIO=[2:0]=RW=
DIV_ACLK_66=clock divider Ratio=
ACLK_66=
= DOUT_ACLK_66_PRE/(ACLK_66_RATIO + 1)=
0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-136  
5.9.1.115 CLK_DIV_TOP1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0514, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31] –=Reserved=0x0=
ACLK_MIPI_HSf=
_TXBASb_RATIO=x30:28]=RW=
DIV_ACLK_MIPI_HSI_TXBASE=clock divider Ratio=
ACLK_MIPI_HSI_TXBASE=
= MOUT_ACLK_MIPI_HSI_TXBASE/=
(ACLK_MIPI_HSI_TXBASE_RATIO + 1)=
0x0=
RSVD=x27]=–=Reserved=0x0=
ACLK_66_PRb=
_RATIO=x26:24]=RW=
DIV_ACLK_66_PRb=clock divider Ratio=
ACLK_66_PRb=
= MOUT_MPLL_USEo/=
(ACLK_66_PRb_RATIO + 1)=
0x0=
RSVD=x23]=–=Reserved=0x0=
ACLK_400_ISP=
_RATIO=x22:20]=RW=
DIV_ACLK_400_ISP=clock divider Ratio=
ACLK_400_ISP=
= MOUT_ACLK_400_ISP/=
(ACLK_400_ISP_RATIO + 1)=
0x0=
RSVD=x19]=–=Reserved=0x0=
ACLK_400_IOP=
_RATIO=x18:16]=RW=
DIV_ACLK_400_IOP=clock divider Ratio=
ACLK_400_IOP=
= MOUT_ACLK_400_IOP/=
(ACLK_400_IOP_RATIO + 1)=
0x0=
RSVD=x15]=–=Reserved=0x0=
ACLK_300_GSCi=
_RATIO=[14:12]=RW=
DIV_ACLK_300_GSCL clock divider oatio=
ACLK_300_GSCi=
= MOUT_ACLK_300_GSCL/=
(ACLK_300_GSCL_RATIO + 1)=
0x0=
RSVD=x11:0]=–=Reserved=0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-137  
5.9.1.116 CLK_DIV_GSCL 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0520, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
GSCL_WRAP 
_B_RATIO [31:28] RW 
DIV_GSCL_WRAP_B clock divider Ratio 
SCLK_GSCL_WRAP_B 
= MOUT_GSCL_W RAP_B/ 
(GSCL_WRAP_B_RATIO + 1) 
0x0 
GSCL_WRAP 
_A_RATIO [27:24] RW 
DIV_GSCL_WRAP_A clock divider Ratio 
SCLK_GSCL_WRAP_A 
= MOUT_GSCL_W RAP_A/ 
(GSCL_WRAP_A_RATIO + 1) 
0x0 
RSVD [23:20] –=Reserved=0x0=
CAM0_RATIO=[19:16]=RW=
DIV_CAM0 clock divider Ratio=
SCLK_CAM0=
= MOUT_CAM0/(CAM0_RATIO + 1)=
0x0=
CAM_BAYER=
_RATIO=[15:12]=RW=
DIV_CAM_BAYER=clock divider Ratio=
SCLK_CAM_BAYER=
= MOUT_CAM_BAYER/=
(CAM_BAYER_RATIO + 1)=
0x0=
RSVD=x11:0]=–=Reserved=0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-138  
5.9.1.117 CLK_DIV_DISP1_0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x052C, Reset Value = 0x0070_0000 
Name Bit Type Description Reset Value 
HDMI_PIXEL 
_RATIO [31:28] RW 
DIV_HDMI_PIXEL clock divider Ratio 
SCLK_PIXEL 
= SCLK_VPLL/(HDMI_PIXEL_RATIO + 1) 
0x0 
DP1_EXT_MST 
_VID_RATIO [27:24] RW 
DIV_DP1_EXT_MST_VID clock divider Ratio 
SCLK_DP1_EXT_MST_VID 
= MOUT_DP1_EXT_MST_VID/ 
(DP1_EXT_MST_VID_RATIO + 1) 
0x0 
MIPI1_PRE_RATIO [23:20] RW 
DIV_MIPI1_PRE clock divider Ratio 
SCLK_MIPI1 
= DOUT_MIPI1/(MIPI1_PRE_RATIO + 1) 
0x7 
MIPI1_RATIO [19:16] RW 
DIV_MIPI1 clock divider Ratio 
SCLK_MIPIDPHY1 
= MOUT_MIPI1/(MIPI1_RATIO + 1) 
0x0 
RSVD [15:4] –=Reserved=0x0=
FIMD1_RATIO=[3:0]=RW=
DIV_FIMD1=clock divider Ratio=
SCLK_FIMa1=
= MOUT_FIMa1/(FIMD1_RATIO + 1)=
0x0=
=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-139  
5.9.1.118 CLK_DIV_GEN 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x053C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:8] –=Reserved=0x0=
JPEG_RATIO=x7:4]=RW=
DIV_JPEG=clock divider Ratio=
SCLK_JPEG=
==SCLK_CPLi/(JPEG_RATIO + 1)=
0x0=
RSVD=[3:0]=–=Reserved=0x0=
=
5.9.1.119 CLK_DIV_MAU 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0544, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:12] –=Reserved=0x0=
PCM0_RATIO=[11:4]=RW=
DIV_PCM0 clock divider Ratio=
SCLK_PCM0=
= SCLK_AUDIO0/(PCM0_RATIO + 1)=
0x0=
AUDIO0_RATIO=[3:0]=RW=
DIV_AUDIO0 clock divider Ratio=
SCLK_AUDIO0=
= MOUT_AUDIO0/(AUDIO0_RATIO + 1)=
0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-140  
5.9.1.120 CLK_DIV_FSYS0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0548, Reset Value = 0x00B0_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
USBDRD30_RATf
l=[27:24]=RW=
DIV_USBDRD30=clock divider Ratio=
SCLK_USBDRD30=
= MOUT_USBDRD30/(USBDRD30_RATIO + 1)=
0xB=
SATA_RATIO=[23:20]=RW=
DIV_SATA clock divider=oatio=
SCLK_SATA=
= MOUT_SATA/(SATA_RATIO + 1)=
0xB=
RSVD=[19:0]=–=Reserved=0x0=
=
5.9.1.121 CLK_DIV_FSYS1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x054C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MMC1_PRE 
_RATIO [31:24] RW 
DIV_MMC1_PRE clock divider Ratio 
SCLK_MMC1 
= DOUT_MMC1/(MMC1_PRE_RATIO + 1) 
0x0 
RSVD [23:20] –=Reserved=0x0=
MMC1_RATIO=[19:16]=RW=
DIV_MMC1 clock divider Ratio=
DOUT_MMC1=
= MOUT_MMC1/(MMC1_RATIO + 1)=
0x0=
MMC0_PRE=
_RATIO=[15:8]=RW=
DIV_MMC0_PRE clock divider Ratio=
SCLK_MMC0=
= DOUT_MMC0/(MMC0_PRE_RATIO + 1)=
0x0=
RSVD=[7:4]=–=Reserved=0x0=
MMC0_RATIO=[3:0]=RW=
DIV_MMC0 clock divider Ratio=
DOUT_MMC0=
= MOUT_MMC0/(MMC0_RATIO + 1)=
0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-141  
5.9.1.122 CLK_DIV_FSYS2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0550, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
MMC3_PRE 
_RATIO [31:24] RW 
DIV_MMC3_PRE clock divider Ratio 
SCLK_MMC3 
= DOUT_MMC3/(MMC3_PRE_RATIO + 1) 
0x0 
RSVD [23:20] –=Reserved=0x0=
MMC3_RATIO=[19:16]=RW=
DIV_MMC3 clock divider Ratio=
DOUT_MMC3=
= MOUT_MMC3/(MMC3_RATIO + 1)=
0x0=
MMC2_PRE=
_RATIO=[15:8]=RW=
DIV_MMC2_PRE=clock divider Ratio=
SCLK_MMC2=
= DOUT_MMC2/MMC2_PRE_RATIO + 1)=
0x0=
RSVD=[7:4]=–=Reserved=0x0=
MMC2_RATIO=[3:0]=RW=
DIV_MMC2 clock divider Ratio=
DOUT_MMC2=
= MOUT_MMC2/(MMC2_RATIO + 1)=
0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-142  
5.9.1.123 CLK_DIV_PERIC0 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0558, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
UART3_RATIl=[15:12]=RW=
DIV_UART3 clock divider Ratio=
SCLK_UART3=
= MOUT_UART3/(UART3_RATIO + 1)=
0x0=
UART2_RATIl=[11:8]=RW=
DIV_UART2 clock divider Ratio=
SCLK_UART2=
= MOUT_UART2/(UART2_RATIO + 1)=
0x0=
UART1_RATIl=[7:4]=RW=
DIV_UART1 clock divider Ratio=
SCLK_UART1=
= MOUT_UART1/(UART1_RATIO + 1)=
0x0=
UART0_RATIl=[3:0]=RW=
DIV_UART0 clock divider Ratio=
SCLK_UART0=
= MOUT_UART0/(UART0_RATIO + 1)=
0x0=
=
5.9.1.124 CLK_DIV_PERIC1 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x055C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
SPI1_PRE_RATIO [31:24] RW 
DIV_SPI1_PRE clock divider Ratio 
SCLK_SPI1 
= DOUT_SPI1/(SPI1_PRE_RATIO + 1) 
0x0 
RSVD [23:20] –=Reserved=0x0=
SPI1_RATIO=[19:16]=RW=
DIV_SPI1 clock divider Ratio=
DOUT_SPI1=
= MOUT_SPI1/(SPI1_RATIO + 1)=
0x0=
SPI0_PRE_RATIO=[15:8]=RW=
DIV_SPI0_PRE clock divider Ratio=
SCLK_SPI0=
= DOUT_SPI0/(SPI0_PRE_RATIO + 1)=
0x0=
RSVD=[7:4]=–=Reserved=0x0=
SPI0_RATIO=[3:0]=RW=
DIV_SPI0 clock divider Ratio=
DOUT_SPI0=
= MOUT_SPI0/(SPI0_RATIO + 1)=
0x0=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-143  
5.9.1.125 CLK_DIV_PERIC2 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0560, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:16] –=Reserved=0x0=
SPI2_PRE_RATIO=[15:8]=RW=
DIV_SPI2_PRE clock divider Ratio=
SCLK_SPI2=
= DOUT_SPI2/(SPI2_PRE_RATIO + 1)=
0x0=
RSVD=[7:4]=–=Reserved=0x0=
SPI2_RATIO=[3:0]=RW=
DIV_SPI2 clock divider Ratio=
DOUT_SPI2=
= MOUT_SPI2/(SPI2_RATIO + 1)=
0x0=
=
5.9.1.126 CLK_DIV_PERIC4 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0568, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:28] –=Reserved=0x0=
PCM2_RATIO=[27:20]=RW=
DIV_PCM2 clock divider=Ratio=
SCLK_PCM2=
= SCLK_AUDIO2/(PCM2_RATIO + 1)=
0x0=
AUDIO2_RATIO=[19:16]=RW=
DIV_AUDIO2 clock divider Ratio=
SCLK_AUDIO2=
= MOUT_AUDIO2/(AUDIO2_RATIO + 1)=
0x0=
RSVD=[15:12]=–=Reserved=0x0=
PCM1_RATIO=[11:4]=RW=
DIV_PCM1 clock divider Ratio=
SCLK_PCM1=
= SCLK_AUDIO1/(PCM1_RATIO + 1)=
0x0=
AUDIO1_RATIO=[3:0]=RW=
DIV_AUDIO1 clock divider Ratio=
SCLK_AUDIO1=
= MOUT_AUDIO1/(AUDIO1_RATIO + 1)=
0x0=
=
= 
						

							Samsung Confidential  
Exynos 5250_UM 5 Clock Controller 
 5-144  
5.9.1.127 CLK_DIV_PERIC5 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x056C, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
RSVD [31:14] –=Reserved=0x0=
I2S2_RATIO=[13:8]=RW=
DIV_I2S2 clock divider Ratio=
SCLK_I2S2=
= SCLK_AUDIO2/(I2S2_RATIO + 1)=
0x0=
RSVD=[7:6]=–=Reserved=0x0=
I2S1_RATIO=[5:0]=RW=
DIV_I2S1 clock divider Ratio=
SCLK_I2S1=
= SCLK_AUDIO1/(I2S1_RATIO + 1)=
0x0=
=
5.9.1.128 SCLK_DIV_ISP 
 Base Address: 0x1002_0000 
 Address = Base Address + 0x0580, Reset Value = 0x0000_0000 
Name Bit Type Description Reset Value 
PW M_ISP_RATIO [31:28] RW 
DIV_IPWM_ISP clock divider Ratio 
SCLK_PW M_ISP 
= MOUT_PWM_ISP/(PWM_ISP_RATIO + 1) 
0x0 
UART_ISP_RATIO [27:24] RW 
DIV_IUART_ISP clock divider Ratio 
SCLK_UART_ISP 
= MOUT_UART_ISP/(UART_ISP_RATIO + 1) 
0x0 
SPI1_ISP_PRE 
_RATIO [23:16] RW 
DIV_SPI1_ISP_PRE clock divider Ratio 
SCLK_SPI1_ISP 
= DOUT_SPI1_ISP/(SPI1_ISP_PRE_RATIO + 1) 
0x0 
SPI1_ISP_RATIO [15:12] RW 
DIV_SPI1_ISP clock divider Ratio 
DOUT_SPI1_ISP 
= MOUT_SPI1_ISP/(SPI1_ISP_RATIO + 1) 
0x0 
SPI0_ISP_PRE 
_RATIO [11:4] RW 
DIV_SPI0_ISP_PRE clock divider Ratio 
SCLK_SPI0_ISP 
= DOUT_SPI0_ISP/(SPI0_ISP_PRE_RATIO + 1) 
0x0 
SPI0_ISP_RATIO [3:0] RW 
DIV_SPI0_ISP clock divider Ratio 
DOUT_SPI0_ISP 
= MOUT_SPI0_ISP/(SPI0_ISP_RATIO + 1) 
0x0