Mitel SX 200 DIGITAL Pabx Superset 3 Telephone Description Manual

							SECTION MITL9109-094-125-NA .
vi 
						

							Circuit Card Descriptions
1. INTRODUCTION
General1 .OlThis Section describes the digital cards in the SX-200@ DIGITAL
PABX. Figure 
1-I shows the front faces of some of these digital
cards.
Reason for Issue
1.02This Section is issued to provide a general description of the
digital circuit cards in the SX-200 DIGITAL PABX.
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							SECTION MITL9109-094-125-NA
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							Circuit Card Descriptions
2. MAIN CONTROL CARD
Description2.01The Main Control card performs all call processing for the
entire system, and peripheral control operations for Bays 1 and
2. It maintains overall control through communication with the Bay
Control card or Peripheral Control Card in each bay.
Facilities
2.02
l
l
0
0
l
l
0
lFacilities on the Main Control Card are:
HDLC link for high speed message communication and bulk
data transfers to peripheral processors or Bay Control cards
and Digital line cards
Two RS-232 communication ports (one printer port, one main-
tenance port)
Floppy Disk Control including data separation and 
write pre-compensation
DMA controller for dynamic RAM refresh, data transfer to floppy
disk and HDLC communication system
Real Time Clock for time of day and interrupt generation, with
3-day non-volatile backup
System PCM Clock Generation
Memory: Dynamic RAM (on RAM Module) with parity detection,
3-day non-volatile CMOS RAM, EPROM
Digital signal processor to generate and detect progress and
ringing tones and to provide conferencing
RAM Module for program storage and process work areas
DX Module (digital time/space crosspoint switch) for circuit and
message switching
Decryption Module to enable use of protected software
Fault detection hardware to monitor PCM clock and processor
sanity (watchdog)
System Reset switch (front panel).
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							SECTION MITL9109-094-125-NAOperation
2.03The Main Control Card (MCC) must not be inserted or removed
with the power on. Damage to 
onboard circuits may result.
2.04 The correct Decryption Module must be installed, or the disk
software will not run.
2.05At power-up the Main Control Card is held reset for about 1
second after the power supply voltages reach their normal
levels. After reset, the processor first runs the software contained in
its EPROM. This consists of tests for the RAM memory, the CPU and
the DMA controller. A routine to load the system software into RAM
from disk is run only after all preliminary tests have been passed.
2.06The Main Control Card may also be reset via the pushbutton
switch behind the front panel of the card near the top. Reset
invokes Power Fail Transfer, which remains in effect until the system
software has been loaded from disk.
2.07Parts 3, 4 and 5 describe the modules that plug into the MCC.
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							Circuit Card Descriptions.
DECRVPTIONMODULE
7736EORIFigure 2-1 Main Control Card and Decryption Module
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							SECTION MITL9109-094-125-NAPage 6 
						

							Circuit Card Descriptions
3. DECRYPTION MODULEBrief Description
3.01The Decryption Module plugs into the lower front corner of the
Main Control Card. The Decryption Module must be present
during power-up and system operation. Figure 2-1 shows the location
of the Decryption Module on the Main Control Card. There are 3
Decryption Modules for Generic 1003, as follows:
aFK3 - Basic System
l
FK4 
- ACD
0FK5 - ACD + Reports
Operation3.02The Decryption Module is written to and read from constantly
by the system software. If there is a mismatch between the
module and the software, the software will not run.
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							Circuit Card Descriptions
4. RAM MODULEBrief Description
4.01The RAM Module carries the dynamic memory required for
program storage and call processing work areas. It plugs into a
96-pin DIN connector on the lower part of the Main Control Card.
Mechanical support is provided by standoffs. The board measures 25.9
mm x 14.5 mm high (10.6 in. x 5.7 in.).
4.02Parity is checked on all read and refresh cycles by circuitry on
the Main Control Card. 
If. the parity logic detects an error, it
logs it in CMOS RAM and invokes a system reset via software.
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