Fujitsu Series 3 Manual

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 Example trimming data acquisition using input capture 
Figure 4-3  shows the time chart of high-speed CR oscillation and the trimming process. 
Figure 4-3 Time chart of high-speed CR oscillation and the trimming process 
CLKHC
CLKHC_div PCLK
TRD
Free run
Input CaptureTIMER2
TIMER1 TIMER3 TIMER4
XtrmminXtrmmax
 
Run the free run timer by setting the main oscillation clock (CLKMC) as the master clock (measurement 
reference clock). Clear the free run timer once before measurement (to avoid overflow). Activate a trigger 
on the rising of the high-speed CR frequency division clock (CLKHC_div) when setting Xtrmmin or 
Xtrmmax, read the input capture timer value at that time, and perform the following calculations. 
Ymin = (TIMER2 - TIMER1)  x  PCLKDIV
 
Ymax = (TIMER4 - TIMER3)  x  PCLKDIV
 
   TIMER1 to TIMER2: Input capture timer value at Ymin   
   TIMER3 to TIMER4: Input capture timer value at Ymax 
   PCLK: Cycle when main oscillation is selected for the master clock 
   DIV: Frequency division ratio (CSR setting value) 
   CLKHC_div : Division clock for the high-speed CR oscillation clock (CLKHC) 
 
Example: When PCLK = 40MHz = 25ns, frequency division ratio = 1/8, and TIMER2 - TIMER1 = 100, 
Ymin = (100 x 25 sec)  x  10-98 3.2MHz
≒
 
 
The i n

put capture which can be used for trimming is ICU ch.3 of the multi-function timer Unit0. PCLK in 
Figure 4-3  is an APB1 clock. For the PCLK at that time, main oscillation must be selected for the master 
cl ock. 
 
 
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 Frequency trimming procedure example 
The following shows a trimming procedure example of high-speed CR oscillation. 
Figure 4-4 Trimming Procedure Example of High-speed CR Oscillation 
Start 
Set the master clock as the main oscillation 
clock by the SCM_CTL register 
 
 
Unlock the MCR_FTRM register 
Write 0x1ACC_E554 to the MCR_RLR 
Set the division ratio of high-speed CR 
oscillation to be input into input capture by the  
M
CRPSR register
Set the input into input capture as the CR 
division clock by the Extended Function Pin 
Setup Register (EPFR01).
Calculate Xtrm 
(see an Xtrm calculation procedure example)
Set the calculated Xtrm    as the MCR_FTRM 
Lock the MCR_FTRM register 
Write 0x0000_0000 to the MCR_RLR 
(Note: Write a value other than 0x1ACC_E554) 
End 
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 Xtrm calculation procedure example 
The following shows an Xtrm calculation procedure example. Perfor m frequency trimming in the two 
stages of coarse adjustment and fine adjustment. 
Figure 4-5 Xtrm Calculation Procedure Example 
 
Start 
 
Set an Xtrmmin value as the MCR_FTRM 
(value of the initial val ue of the TRD bit - 20%)
Free run timer operation 
Free run timer clear 
Set a trigger for input capture on the rising of the high-speed CR oscillation division clock 
Read TIMER1 and TIMER2 values 
Set an Xtrmmax value as the MCR_FTRM 
(value of the initial va lue of the TRD bit + 20%)
Free run timer operation 
Free run timer clear 
Set a trigger for input capture on the rising of the high-speed CR oscillation division clock 
Read TIMER3 and TIMER4 values 
Calculate Ymin and Ymax, based on 
measured TIMER1 to TIMER4 values: 
Ymin = DIV/{(TIMER2-TIMER1) ×PCLK} 
Ymax = DIV/{(TIMER4-TIMER3)× PCLK} 
Calculate Xtrm (TRD set value at Ytgt): 
K = (Ymax – Ymin)/(Xtrmmax-Xtrmmin)  Xtrm = {(Ytgt– Ymin)/K} +Xtrmmin 
End 
Calculate Xtrm of the coarse adjustment  (TRD[9:5]) bit 
Set an Xtrmmin value as the MCR_FTRM 
Calculate Xtrm of the fine adjustment (TRD[4:0]) bit 
(Xtrmmin = Xtrm[ 9:5],5b00000) 
Xtrm
[9:5] is a value calculated from coarse 
Free run timer operation  Free run timer clear 
Set a trigger for input capture on the rising of the high-speed CR oscillation division clock 
Read TIMER1 and TIMER2 values 
Set an Xtrmmax value as the MCR_FTRM 
(Xtrmmax = Xtrm[9:5],5b11111) 
Xtrm[9:5] is a value calculated from coarse 
Free run timer operation  Free run timer clear 
Set a trigger for input capture on the rising of the high-speed CR oscillation division clock 
Read TIMER3 and TIMER4 values 
Calculate Ymin and Ymax, based on 
measured TIMER1 to TIMER4 values: 
Ymin = DIV/{(TIMER2-TIMER1) ×PCLK} 
Ymax = DIV/{(TIMER4-TIMER3)× PCLK} 
Calculate Xtrm (TRD set value at Ytgt): 
K = (Ymax – Ymin)/(Xtrmmax-Xtrmmin)  Xtrm = {(Ytgt– Ymin)/K} +Xtrmmin 
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 Procedure example of using CR trimmi ng area storage data inside flash 
memory 
The following shows a procedure example of readin g trimming data stored in the CR trimming area 
inside flash memory and setting it as the frequency trimming register. 
Figure 4-6 Procedure Example of Using CR Trimming Area Storage Data 
Start 
 
 
Unlock the MCR_FTRM register 
Write 0x1ACC_E554 to the MCR_RLR 
Read the CR trimming area inside flash  memory 
Set the read value as the MCR_FTRM 
Lock the MCR_FTRM register 
Write 0x0000_0000 to the MCR_RLR 
(Note: Write a value other than 0x1ACC_E554) 
End 
  For th

e address of the CR trimming area, see Flash Programming Manual. 
   
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5.  High-Speed CR Trimming Function Register List 
The following lists and explains registers used for frequency trimming function of the 
high-speed CR oscillator. 
Ta b l e  5 - 1 lists the registers. 
Table 5-1 Register list 
Abbreviation Register name See 
MCR_PSR  High-speed CR oscillation    Frequency Division Setup Register  5.1 
MCR_FTRM High-speed CR oscillation    Frequency Trimming Register  5.2 
MCR_RLR High-speed CR oscillator    Register Write-Protect Register  5.3 
 
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5.1.  High-speed CR oscillation Frequency Division Setup Register (MCR_PSR) 
The MCR_PSR sets the frequency division ratio of high-speed CR oscillation. 
A divided clock can be input into input capture. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved  CSR 
Initial value - 2b01 
Attribute -  R/W 
 Register functions 
[bit 7:2] : Reserved bits 
0b000000 is read from these bits. 
Set these bits to 0b000000 when writing. 
[bit 1:0] CSR: High-speed CR oscillati on frequency division ratio setting bit 
Bit 1 Bit 0 Description 
0 0 1/4 
0 1 1/8 [Initial value] 
1 0 1/16 
1 1 1/32 
 
 
This  reg

ister is not initialized by software reset. 
  
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5.2.  High-speed CR oscillation Frequency Trimming Register (MCR_FTRM) 
The MCR_FTRM sets the frequency trimming value. 
This section explains register configuration and register functions. 
 Register configuration 
bit  31                16
Field Reserved 
Initial value  - 
Attribute - 
         
bit 15     109 8 7 6 5 4 3 2 1 0 
Field Reserved TRD[9:0] 
Initial value  -  10b0110000000 
Attribute -  R/W 
 Register functions 
[bit 31:10] : Reserved bits 
0 is always read from these bits. 
Writing is ignored. 
[bit 9:0] TRD: Frequency trimming setup bit 
Bit 9:5  Description 
When write This bit makes coarse adjustment to the high-speed CR oscillator frequency. 
For values to be set, see trimming data 
acquisition in the operation explanation of 
the frequency trimming function. 
This bit fluctuates in frequency steps of  approximately 6% each time ±1 setting is 
made. 
When read  A specified value is read. 
As an initial value, 5b01100 is read. 
 
Bit 4:0 
Description 
When write This bit makes fine adjustment to the high-speed CR oscillator frequency. 
For values to be set, see trimming data 
acquisition in the operation explanation of 
the frequency trimming function. 
This bit fluctuates in frequency steps of  approximately 0.4% each time ±1 setting 
is made. 
When read  A specified value is read. 
As an initial value, 5b00000 is read. 
 
 
  This  reg

ister is not initialized by software reset. 
   For values to  

be set to the TRD bit, see trimming  data acquisition in the operation explanation of the 
frequency trimming function. 
 
 
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5.3.  High-Speed CR Oscillator Register Write-Protect Register (MCR_RLR) 
The MCR_RLR controls the write-protect state of the frequency trimming register 
(MCR_FTRM). 
 Register configuration 
bit  31         16 
Field TRMLCK[31:16] 
Initial value  16h0000 
Attribute R/W 
         
bit 15       0 
Field TRMLCK[15:0] 
Initial value  16h0001 
Attribute R/W 
 Register functions 
[bit 31:0] TRMLCK: Register write-protect bits 
Bit 31:0  Description 
When read When 0x00000000 is read, the MCR_FTRM register is currently unlocked.
When 0x00000001 is read, the MCR_FTRM register is currently locked. 
Writing other than 
0x1ACCE554  Locks the MCR_FTRM register 
Writing 
0x1ACCE554  Unlocks the MCR_FTRM register 
 
 
This  reg

ister is not initialized by software reset. 
  
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6. High-Speed CR Trimming Function Usage Precautions 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: High-Speed CR Trimming 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  16 
6.  High-Speed CR Trimming Function Usage Precautions 
This section explains the precautions for using high-speed CR trimming function. 
   About low-speed CR oscillator 
This trimming function is only enabled for the high-speed CR oscillator. 
It cannot apply to the low-speed CR oscillator.   
   About data stored in the CR trimming area 
The CR trimming area stores th e factory preset frequency trimming data. For the preset data, see 
Data Sheet. 
   How to use input capture 
For information about how to use input capture, see Chapters Multi-Function Timer and I/O Port. 
   About FCS (Anomalous Frequency Detection) 
For FCS function (anomalous frequency detection), see Chapter Clock supervisor. Do not perform CR 
trimming after the FCS function is enabled. 
 
CHAPTER  2-2: High-Speed  CR Trimming 
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