Fujitsu Series 3 Manual

							 
5. Registers 
 
[Bit 8] STR0: 8-bit UP counter operation Enable bit This bit enables the 8-bit UP counter operation. 
Bit Function 
Read  0 is always read. 
Writing by 0  No effect 
Writing by 1  Starts the PPG UP counter operation. 
 
[Bits 7:0] RES: Reserved bits  0b00000000 is read from these bits. 
Set these bits to 0b00000000 when writing. 
 
 
  If TRGn O=1

 is set for matching by compare register value and if TRGnO=0 is set simultaneously, the 
start tr i

gger clear operation by TRGnO=0 setting preceded. 
   If TRGnO=0 is set by register writing before the TRGnO=1 is set for ma tching by compare register value, 
it does not have an affect on other operations. 
   The STR bit writing is prohibited when  the 8-bit UPcounter is operating. The STR bit must be set to 1 
when the MONI bit is 0. 
   If the STR bit is set to 1 when the 8-bit UP counter is operating, this writing is ignored. 
   The CS bit writing is prohibited after the 8-bit UP counter has operated. 
 
 
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5. Registers 
 
5.2.  PPG Start Trigger Control Register 1 (TTCR1) 
The TTCR1 Register controls a start of PPG8/PPG10/PPG12/PPG14 Register. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field TRG7O TRG5O TRG3O TRG1O CS11 CS10 MONI1  STR1 
Attribute  R/W R/W R/W  R/W R/W R/W  R R/W 
Initial value  1 b1 1 b1 1 b1  1 b1  1b0 1b0  1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field Reserved 
Attribute - 
Initial value  - 
 
  Register functions 
[Bits 15:12] TRG7O, TRG5O, TRG3O,  TRG1O: PPG trigger stop bits 
These bits control the PPG start trigger signal. 
Bits 15:12  Function 
Read 1 is always read. 
Writing by 0  Disables the PPG start trigger signal. (LOW output) 
Writing by 1 No effect 
 
[Bit 11:10] CS11, CS10: Count clock select bits  of UP counter comparing built-in compare register. 
These bits set an operation clock of UP counter. 
Bit 11  Bit 10  Function 
0 0 PCLK/2 [Initial value]   
0 1  PCLK/8 
1 0 PCLK/32 
1 1 PCLK/64 
 
[Bit 9] MONI1: 8-bit UP counter operation state monitor bit  This bit indicates the PPGs 8-bit UP counter operation state. 
Bit Function 
Reading as 0  The PPG UP counter is stopped. [Initial value] 
Reading as 1 The PPG UP counter is operating. 
During writing No effect 
 
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5. Registers 
 
[Bit 8] STR1: 8-bit Counter Operation Enable bit This bit enables the 8-bit UP counter operation. 
Bit Function 
Read  0 is always read. 
Writing by 0  No effect 
Writing by 1  Starts the PPG Counter operation. 
 
[Bits 7:0] RES: Reserved bits  0b00000000 is read from these bits. 
Set these bits to 0b00000000 when writing. 
 
 
 
  If TRGn O=1

 is set for matching by compare register value and if TRGnO=0 is set simultaneously, the 
start tr i

gger clear operation by TRGnO=0 setting preceded. 
   If TRGnO=0 is set by register writing before the TRGnO=1 is set for ma tching by compare register value, 
it does not have an affect on other operations. 
   The STR bit writing is prohibited when  the 8-bit UPcounter is operating. The STR bit must be set to 1 
when the MONI bit is 0. 
   If the STR bit is set to 1 when the 8-bit UP counter is operating, this writing is ignored. 
   The CS bit writing is prohibited after the 8-bit UP counter has operated. 
 
 
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5. Registers 
 
5.3.  PPG Compare Register n (COMPn, where n=0 to 7) 
The COMPn Register sets a Compare Register value of the Timing Generator. 
 Register configuration 
Bit  15/7 14/6 13/5  12/4 11/3 10/2  9/1 8/0 
Field COMPn 
Attribute R/W 
Initial value  8b00000000 
Note:  Bits 7 to 0 are set for an odd number address, bu t bits 15 to 8 are set for an even number address. 
 Register functions 
[Bits 15:8, or bits 7:0] COMP7 to CO MP0: Compare Register channels 7 to 0 
Sets a PPG Compare Register value. 
Bits 15:8, or  bits 7:0  Function 
Read Reads the Compare 
Register value. 
Initial value is 0b00000000. 
Write  Writes a Compare Register value. 
 
 
  This is an  

8-bit Compare Register, and it is  assigned to
  each of PPG start trigger signals. 
   When the register value matches the 8-bit counter  value, a PPG start trigger signal of the channel 
corresponding to the matching register value is switched from LOW to HIGH state and output. 
   If this register value is 0b00000000, it is not co mpared with the 8-bit counter value. The PPG start 
trigger signal is never output HIGH but is kept LOW. 
   This register writing is prohibited wh en the 8-bit Counter is operating. 
 
 
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5. Registers 
 
5.4.  PPG Start Register (TRG) 
The TRG Register allows a start of the PPG. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field  PEN15 PEN14 PEN13  PEN12 PEN11 PEN10  PEN09 PEN08 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field  PEN07 PEN06 PEN05  PEN04 PEN03 PEN02 PEN01 PEN00 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
 
  Register functions 
[Bits 15:0] PEN15 to PEN00: PPG Operation Enable bits 
Starts PPG operation and sets its operation mode. 
Bits 15:0  Function 
0 Disables PPG operation. (The LOW output is held.) [Initial value] 
1 Enables PPG operation. 
 
 
In 16

-bit PPG mode, a combination of TRG Register PENn bits of each channel must be started or stopped 
simulta neousl

y. 
 
 
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5. Registers 
 
5.5.  Output Reverse Register (REVC) 
The REVC Register sets an output polarity of PPG output value. 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field  REV15REV14 REV13 REV12REV11 REV10 REV09 REV08
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
           
Bit  7 6 5  4 3 2 1 0 
Field  REV07REV06 REV05 REV04REV03 REV02 REV01 REV00
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1b0 1b0 1b0  1b0 1b0 1b0 1b0 1b0 
 
  Register functions 
[Bits 15:0] REV15 to REV00: PPG Output Reverse Enable bits 
Sets a polarity of PPG output value. 
Bits 15:0  Function 
0 Normal output (LOW output when PPG is not operating) [Initial value] 
1 Invert the output. (HIGH output when PPG is stopped) 
 
 
In 16

-bit operation mode, the PPG values of even-numbered channels (PPG0, PPG2, PPG4, PPG6, PPG8, 
PPG10, PPG12, and  PPG14

) are only output. If the REVC Registers of odd-numbered channels are written, 
it has no effect. 
 
 
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5. Registers 
 
5.6.  PPG Operation Mode Control Register (PPGC) 
PPGC Register sets an interrupt, an operation mode, and the prescaler data. 
 PPGC Register configuration list 
  15   8  7    0 Initial 
value  Access  Corresponding 
PPG 
 PPGC0  PPGC1 0x0000R/W PPG0, PPG1 
 PPGC2  PPGC3 0x0000R/W PPG2, PPG3 
 PPGC4  PPGC5 0x0000R/W PPG4, PPG5 
 PPGC6  PPGC7 0x0000R/W PPG6, PPG7 
 PPGC8  PPGC9 0x0000R/W PPG8, PPG9 
 PPGC10  PPGC11 0x0000R/W PPG10, PPG11
 PPGC12  PPGC13 0x0000R/W PPG12, PPG13
 PPGC14  PPGC15 0x0000R/W PPG14, PPG15
 
 Register configuration details 
Bit  15/7 14/6 13/5  12/4 11/3 10/2  9/1 8/0 
Field  PIE PUF INTM  PCS1 PCS0 MD1  MD0 TTRG 
Note:  Bits 7 to 0 are set for an odd number address, bu t bits 15 to 8 are set for an even number address. 
 Register functions 
[Bit 15 or 7] PIE: PPG Interrupt Enable bit 
Enables a PPG interrupt. 
Bit 15 or 7  Function 
0 Disables an interrupt. [Initial value] 
1 Enables an interrupt. 
 
[Bit 14 or 6] PUF: PPG Counter Underflow bit  Controls the underflow bits of PPG Counter. 
Bit 14 or 6  Function 
0 No underflow of PPG Counter was detected. [Initial value] 
1 An underflow of PPG Counter was detected. 
 
[Bit 13 or 5] INTM: Interrupt Mode Select bit  Sets an interrupt mode. 
Bit 13 or 5  Function 
0 Sets the PUF bit to 1 when a PPLH or  PPLL underflow occurs. [Initial value] 
1 Sets the PUF bit to 1 only when a PPLH underflow occurs. 
 
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5. Registers 
 
[Bit 12 or 11, or bit 4 or 3] CS1, CS0: PPG DOWN Counter Operation Clock Select bits 
Sets an operation clock of PPGs DOWN Counter. 
Bit 12 or 4  Bit 11 or 3  Function 
0 0 PCLK [Initial  value] 
0 1  PCLK/4 
1 0  PCLK/16 
1 1 PCLK/64 
 
[Bit 10 or 9, or bit 9 or 1] MD1, MD0: PPG Operation Mode Set bits  PPG output value can be set to be reversed. 
Bit 10 or 9  Bit 9 or 1  Function 
0 0 Sets 8-bit operation mode. [Initial value] 
0 1 Sets 8+8-bit operation mode. 
1 0 Sets 16-bit operation mode. 
1 1 Sets 16+16-bit operation mode. 
 
[Bit 8 or 0] TTRG: PPG start trigger select bit  Selects the PPG start trigger. 
Bit 8 or 0  Function 
0 Uses a TRG Register value or a multifunction timer value. [Initial value] 
1 Uses a Timing Generator Circuit. 
 
 
  If PP GC.P

IF=1 and PPGC.PUF=1, an interrupt occurs. 
   If an u nde

rflow occurs, the PPGC.PUF bits of Cha nnel 0 and Channel 1 are set in the same timing. 
   The PPGC.PUF bits are cleared when they are se t to 0. The bit setting to 1 is ignored. 
   When a Read-Modify-Write instruction is executed, th e PPGC.PUF bit is always held to 1 regardless 
of the bit value.   
   In 16-bit PPG mode, the values are the same between Channel 0 and Channel 1, and between Channel 2 
and Channel 3. 
Therefore, the count value is within a range of 0x0000 to 0xFFFF. 
   The PPGC.CS1, PPGC.CS0 and PPGC.TTRG bits are set only for Channel 0 and Channel 2 of PPGC 
Register. 
 
 
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5. Registers 
 
5.7.  PPG Reload Registers (PRLH, PRLL) 
The PRLH and PRLL Registers set the LOW and HIGH width of PPG. 
 PPGC Register configuration list 
  15   8  7    0 Initial 
value  Access  Corresponding 
PPG 
 PRLH0  PRLL0 0xxxxxR/W  PPG0 
 PRLH1  PRLL1 0xxxxxR/W  PPG1 
 PRLH2  PRLL2 0xxxxxR/W  PPG2 
 PRLH3  PRLL3 0xxxxxR/W  PPG3 
 PRLH4  PRLL4 0xxxxxR/W  PPG4 
 PRLH5  PRLL5 0xxxxxR/W  PPG5 
 PRLH6  PRLL6 0xxxxxR/W  PPG6 
 PRLH7  PRLL7 0xxxxxR/W  PPG7 
 PRLH8  PRLL8 0xxxxxR/W  PPG8 
 PRLH9  PRLL9 0xxxxxR/W  PPG9 
 PRLH10  PRLL10 0xxxxxR/W  PPG10 
 PRLH11  PRLL11 0xxxxxR/W  PPG11 
 PRLH12  PRLL12 0xxxxxR/W  PPG12 
 PRLH13  PRLL13 0xxxxxR/W  PPG13 
 PRLH14  PRLL14 0xxxxxR/W  PPG14 
 PRLH15  PRLL15 0xxxxxR/W  PPG15 
 
 Register configuration 
Bit  15 14 13  12 11 10  9 8 
Field PRLH 
Attribute R/W 
Initial value  8bXXXXXXXX 
           
Bit  7 6 5  4 3 2 1 0 
Field PRLL 
Attribute R/W 
Initial value  8bXXXXXXXX 
 
  Register functions 
[Bits 15:8] PRLH: PPG Reload Register Level-HIGH Set bits 
Sets a HIGH value of PPG. 
Bit Function 
During writing Any value can be written. 
During reading The register value is read. The initial value is undefined. 
 
[Bits 7:0] PRLL: PPG Reload Register Level-LOW Set bits  Sets a LOW value of PPG. 
Bit Function 
During writing Any value can be written. 
During reading The register value is read. The initial value is undefined. 
 
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5. Registers 
 
 This register operation is determined based on PPG operation mode. 
The following
  defines each operation mode. 
  8-bit operation mode combination 
  15                                  8 7                                   0
 PRLH0  PRLL0 
  Sets the HIGH width of PPG0.  Sets the LOW width of PPG0. 
 PRLH1  PRLL1 
 Sets the HIGH width of PPG1.  Sets the LOW width of PPG1. 
 PRLH2  PRLL2 
 Sets the HIGH width of PPG2.  Sets the LOW width of PPG2. 
 PRLH3  PRLL3 
 Sets the HIGH width of PPG3.  Sets the LOW width of PPG3. 
  

 
 
 
   Sets the PPGn channel. (n=0 to 15) 
The 8-bit PRLH bits of PPGn set the HIGH width  of PPGn. The 8-bit length PRLL bits set the LOW 
width of PPGn. 
  8+8-bit operation mode combination 
 15                                  87                                   0
 PRLH0 PRLL0 
 Sets the HIGH width of PPG0. Sets the LOW width of PPG0. 
 PRLH1  PRLL1 
 Sets the HIGH width of PPG0-pri.  Sets the LOW width of PPG0-pri. 
 PRLH2  PRLL2 
 Sets the HIGH width of PPG2.  Sets the LOW width of PPG2. 
 PRLH3  PRLL3 
 Sets the HIGH width of PPG2-pri.  Sets the LOW width of PPG2-pri. 
  
 
 
 
  PPGn and PPGn+1 channel settings (where, n=0, 2, 4, 6, 8, 10, 12, or 14) 
The 8-bit PRLH bits of PPGn set the HIGH width of PPGn. The 8-bit length PRLL bits set the LOW 
width of PPGn. The 8-bit length PRLH bits of PPGn+1 set the HIGH width of PPGn prescaler. The 8-bit 
length PRLL bits of PPGn+1 set the LOW width of PPGn prescaler. 
  16-bit operation mode combination 
  15                                  8 7                                   0
 PRLH0  PRLL0 
  Sets the HIGH width of PPG0. 
 PRLH1  PRLL1 
 Sets the LOW width of PPG0. 
 PRLH2  PRLL2 
 Sets the HIGH width of PPG2. 
 PRLH3  PRLL3 
 Sets the LOW width of PPG2. 
  
 
 
 
  PPGn and PPGn+1 channel settings (where, n=0, 2, 4, 6, 8, 10, 12, or 14) 
The 16-bit length that combined PRLH with PRLL  bits of PPGn set the HIGH width of PPGn. The 
16-bit length that combined PRLH with PRLL  bits of PPGn+1 set the LOW width of PPGn. 
FUJITSU SEMICO NDUCTOR LIMITED 
CHAPTER  16-2: PPG 
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MB9Axxx/MB9Bxxx  Series