Fujitsu Series 3 Manual

							 
4. Registers 
 
4. Registers 
This section explains the configuration and functions of the registers used for the Quad 
Position & Revolution Counter (QPRC). 
 List of Quad Position & Revolution Counter registers 
 
Abbreviation Register  name See 
QPCR Quad Position & Revolution Counter Position Count Register  4.1 
QRCR QPRC Revolution Count Register  4.2 
QPCCR QPRC Position Counter Compare Register  4.3 
QPRCR QPRC Position and Revolution Counter Compare Register  4.4 
QCR QPRC Control Register  4.5 
QECR QPRC Extension Control Register  4.6 
QICRL Low-Order Bytes of QPRC Interrupt Control Register  4.7 
QICRH High-Order Bytes of QP RC Interrupt Control Register  4.8 
QMPR QPRC Maximum Position Register  4.9 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
665 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
4.1.  Quad Position & Revolution Counter Position Count Register (QPCR) 
The Quad Position & Revolution Counter Position Count Register (QPCR) indicates the 
position counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 
0 
Field QPCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPCR:    Reading this register reads out the current value of  the position counter. While the position counter stops 
counting (QCR:PSTP=1), the count value can be written to this register. 
This register is set to 0x0000 in the following one of conditions. 
   Reset 
   A ZIN active edge is detected in the following conditions. 
  The ZIN function is set to the counter clear function (QCR:CGSC=0) in RC_Mode1 
(QCR:RCM[1:0]=01). 
   After the position counter has been incremented or decremented by the mask set value when the 
count inversion of the position counter is not detected where the ZIN function is set to the counter 
clear function (QCR:CGSC=0) and the reset ma sk function of the position counter is valid 
(QCR:PCRM[1:0]=01 or 10 or 11) in RC_Mode0 (QCR:RCM[1:0]=00) or RC_Mode3 
(QCR:RCM[1:0]=11) 
   The ZIN function is set to the counter clear function (QCR:CGSC=0) and the reset mask function 
of the position counter is invalid (QCR:PCRM[1:0]=00) in RC_Mode0(QCR:RCM[1:0]=00) or 
RC_Mode3(QCR:RCM[1:0]=11). 
   A position counter overflow is detected in the following conditions. 
  RC_Mode2(QCR:RCM[1:0]=10) 
   After the position counter has been incremented or decremented by the mask set value when the 
count inversion of the position counter is not detected where the ZIN function is set to the counter 
clear function (QCR:CGSC=0) and the reset ma sk function of the position counter is valid 
(QCR:PCRM[1:0]=01 or 10 or 11) in RC_Mode0 (QCR:RCM[1:0]=00) or RC_Mode3 
(QCR:RCM[1:0]=11) 
   The ZIN function is set to the counter clear function (QCR:CGSC=0) and the reset mask function 
of the position counter is invalid (QCR:PCRM[1:0]=00) in RC_Mode0(QCR:RCM[1:0]=00) or 
RC_Mode3(QCR:RCM[1:0]=11). 
   0x0000 is written to this QPCR while the positi on counter is under suspension (QCR:PSTP=1). 
 
The value of the QPRC Maximum Position Register (QMP R) is set to this register in the following 
condition. 
   A position counter underflow is detected. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
666 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
   Do not access the Quad Position &  Revolution Counter Position Count R
 egister (QPCR) with a byte 
access instruction. 
   After the count value was written to the Quad Pos ition & Revolution Counter Position Count Register 
(QPCR) while the position counter was unde r suspension (QCR:PSTP=1) in RC_Mode0 
(QCR:RCM[1:0]=00), RC_Mode1 (QCR:RCM[1:0]=01), or RC_Mode3(QCR:RCM[1:0]=11), if a 
ZIN active edge is detected with the count function (QCR:CGSC=0), the Quad Position & Revolution 
Counter Position Count Register (QPCR) will be set to 0x0000. 
To write the count value to the Quad Position &  Revolution Counter Position Count Register (QPCR), 
make the ZIN detection edge invalid (QCR:CGE[ 1:0 ]=00) before writing it to the QPCR. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
667 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
4.2.  QPRC Revolution Count Register (QRCR) 
The QPRC Revolution Count Register (QRCR) indicates the revolution counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 
0 
Field QRCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QRCR:    Reading this register reads out th e current value of the revolution counter. While the revolution counter 
stops counting (QCR:RCM[1:0]=00), the count value can be written to this register. 
This register is set to 0x0000 in the following one of conditions. 
   Reset 
   0x0000 is written to this register while the revolution counter is under suspension 
(QCR.RCM[1:0]=00). 
 
 
   Do not access  the QPRC Revolution Count 
Register
  (QRCR) with a byte access instruction. 
   As the direction of the position counter is not detected in PC_Mode0 (QCR:PCM[1:0]=00), the last 
position counter direction bit (QICR:DI RPC) becomes indefinite. Therefore, if the mode is changed from 
PC_Mode0 (QCR:PCM[1:0]=00) to another mode, when a ZIN active edge is detected before an 
AIN/BIN active edge is detected,  the following operations apply. 
   The position counter is reset if the mode is RC_Mode0 (QCR:RCM[1:0]=00), RC_Mode1 
(QCR:RCM[1:0]=01), or RC_Mode3 (QCR:RCM[1:0]=11) 
   The revolution counter is not counted up or down 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
668 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
4.3.  QPRC Position Counter Compare Register (QPCCR) 
The QPRC Position Counter Compare Register (QPCCR) is used to compare with the count 
value of the position counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field QPCCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPCCR:    If the value of this register matches that of the po sition counter, the QPRC position counter comparison 
match flag (QICR:QPCMF) is set to 1. This Compare Register can be used on ly to compare with the 
count value of the position counter. 
 
 
Do not access the QPRC Positi on C

ounter Compare Register (QPCCR) with a by te access instruction. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
669 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
4.4.  QPRC Position and Revolution Counter Compare Register (QPRCR) 
The QPRC Position and Revolution Counter Compare Register (QPRCR) is used to compare 
with the selected count value of the position or revolution counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field QPRCR[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit 15:0] QPRCR:    Select whether to compare with the count value of the position or revolution counter using the RSEL bit of 
the QPRC Control Register (QCR). If the value of this register matches that of the position or revolution 
counter, the QPRC position and revolution counter comp arison match flag (QICR:QPRCMF) is set to 1. 
 
  Do not access the QPRC Positi on a

nd Revolution Counter Compare Register (QPRCR) with a byte access 
in stru

ction. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
670 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
4.5.  QPRC Control Register (QCR) 
The QPRC Control Register (QCR) is used to specify the operation mode of the position 
counter or 16-bit revolution counter. It is also used to start or stop each counter. 
 Low-Order Bytes of QPRC Control Register (QCRL) 
 
bit 7 6 5 4 3 2 1 0 
Field SWAP RSEL CGSC PSTP RCM1 RCM0 PCM1 PCM0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] SWAP: Swap bit  This bit is used to swap the connections of th e AIN input and BIN input to the position counter. 
When this bit is set to 0, the AIN pin is used for the AIN input of the position counter, and the BIN pin is 
used for the BIN input of the position counter. When this bit is set to 1, the AIN pin is used for the BIN 
input of the position counter, and the BIN pin is  used for the AIN input of the position counter. 
Bit Description 
0 No swap 
1 Swaps AIN and BIN inputs. 
 
 
Change  t

he swap bit (SWAP) when the position counter is disabled (PCM[1:0]=00). 
 [bit 6] RSEL: Register function selection bit  This bit is used to  select 

whether to compare the value of the QPRC Position and Revolution Counter 
Compare Register (QPRCR) with that of  the position or revolution counter. 
Bit Description 
0 Compares the value of the QPRC Position and Revolution Counter Compare 
Register (QPRCR) with that of the position counter. 
1 Compares the value of the QPRC Position and Revolution Counter Compare 
Register (QPRCR) with that of the revolution counter. 
 
 
When t h

e value of the position counter matches th at of the QPRC Position Counter Com
 pare Register 
(QPCCR) and also the value of the revolution counter matches that of the QPRC Position and Revolution 
Counter Compare Register (QPRCR), the PC match and RC match interrupt request flag bit (QICR: 
QPCNRCMF) is set to 1 regardless of the setting of this bit. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
671 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
[bit 5] CGSC: Count clear or gate selection bit This bit is used to select the function of the ZIN external pin. 
When the counter clear function is  enabled (QGSC=0), the ZIN pin clears the position counter if the 
revolution count mode is set to RC_Mode0 (RCM[1:0]=00), RC_Mode1 (RCM[1:0]=01), or 
RC_Mode3 (RCM[1:0]=11). The CGE1 and CGE0 bits  of the QCR register clear the position counter by 
selecting a valid edge of the ZIN pin and detecting the selected edge. 
When the gate function is enabled (QGSC=1), the ZIN pin controls the count operation of the position 
counter. The CGE1 and CGE0 bits of the QCR register count the position counter at the valid level of the 
ZIN pin. 
Bit Description 
0 Counter clear function 
1 Gate function 
 
[bit 4] PSTP: Position counter stop bit  This bit is used to stop the position counter. 
Bit Description 
0 Enables count operation. 
1 Stops count operation. 
 
[bit 3:2] RCM1, RCM0: Revolution counter mode bits  These bits are used to select the count mode of the  revolution counter and the reset mode of the position 
counter. For the effect on the position counter, see  Operation of revolution counter. 
bit3 bit2  Description 
0 0 Disables the revolution counter (RC_Mode0). 
0 1  The revolution counter is counted up or down only with a ZIN active edge 
(RC_Mode1). 
1 
0 The revolution counter is counted up or down only when overflow or underflow 
is detected in the position counter that matches QMPR (RC_Mode2). 
1  1 The revolution counter is counted up or down in two cases: a position counter 
overflow or underflow is detected and a ZIN active edge is detected 
(RC_Mode3). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
672 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
[bit 1:0] PCM1, PCM0: Position counter mode bits These bits are used to select the count mode of the position counter. 
bit1 bit0  Description 
0 0 Disables the position counter (PC_Mode0) to stop it. 
0 1  Up-down count mode (PC_Mode1) 
Increments the value with an AIN active edge and decrements it with a BIN 
active edge. 
1 
0 Phase difference count mode (PC_Mode2) 
Counts up if AIN is leading BIN and down if BIN is leading AIN. 
1  1 Directional count mode (PC_Mode3) 
Counts up or down with the BIN active edge and AIN level. 
 
 
As the di rection

 of the position counter is not detected in PC_Mode0 (PCM[1:0]=00), the last position 
counter di re

ction bit (QICR:DIRPC) becomes indefinite. Therefore, if the mode is changed from 
PC_Mode0 (PCM[1:0]=00) to another mode, when a ZIN active edge is detected before an AIN/BIN 
active edge is detected, the following operations apply. 
  The position counter is reset if the mode is RC_Mode0 (RCM[1:0]=00), RC_Mode1 
(RCM[1:0]=01), or RC_Mode3 (RCM[1:0]=11) 
   The revolution counter is not counted up or down 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
673 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers 
 
 High-Order Bytes of QPRC Control Register (QCRH) 
 
bit 15 14 13 12 11 10 9 8 
Field CGE1 CGE0 BES1 BES0 AES1 AES0 PCRM1 PCRM0
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 15:14] CGE1, CGE0: Detection edge selection bits  These bits are used to select the  detection edge when the ZIN external pin is used for the counter clear 
function (CGSC=0). They are also used to select the detection level when the ZIN external pin is used for 
the gate function (CGSC=1). 
bit15 bit14  ZIN used for counter clear function
(CGSC=0)  ZIN used for gate function 
(CGSC=0) 
0  0 Disables edge detection.  Disables level detection. 
0 1 Detects a falling edge.  Detects level L. 
1 0 Detects a rising edge.  Detects level H. 
1 1 Detects a rising or falling edge.  Disables level detection. 
 
[bit 13:12] BES1, BES0: BIN detection edge selection bits  These bits are used to select the det ection edge of the BIN external pin. 
bit13 bit12  Description 
0 0 Disables edge detection. 
0 1 Detects a falling edge. 
1  0 Detects a rising edge. 
1  1 Detects rising and falling edges. 
 
[bit 11:10] AES1, AES0: AIN detection edge selection bits  These bits are used to select the det ection edge of the AIN external pin. 
bit11 bit10  Description 
0 0 Disables edge detection. 
0 1 Detects a falling edge. 
1  0 Detects a rising edge. 
1  1 Detects rising and falling edges. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  17: Quad  Position  & Revolution  Counter 
MN706-00002-1v0-E 
674 
MB9Axxx/MB9Bxxx  Series