Fujitsu Series 3 Manual

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5.9.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 - 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits 
They are FIFO Test bits. 
They must always be set to 0. 
Bit 15:14  Description 
0 Disables the FIFO test. 
1  Enables the FIFO test. 
 
 
If this  b

it is set to 1, the FIFO test is executed. 
 
[bit 13] Reserved bit 
This bit value is undefined during reading.   
This bit has no effect during writing. 
 
[bit 12] FLSTE: Re-transmit data lost detection enable bit 
This bit enables the FCR0:FLST bit detection. 
If set to 0, the FCR0:FLST bit detection is disabled.   
If set to 1, the FCR0:FLST bit detection is enabled. 
Bit Description 
0  Disables the Data Lost detection. 
1  Enables the Data Lost detection. 
 
 
If you wish  t

o set this bit to 1, set the FSET bit to 1 first, and then set this bit to 1. 
 
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[bit 11] FRIIE: Receive FIFO idle detection enable bit 
This bit sets to detect the receive idle state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0, a detection of receive idle state is disabled.   
If set to 1, a detection of receive idle state is enabled. 
Bit Description 
0  Disables the receive FIFO idle detection. 
1  Enables the receive FIFO idle detection. 
 
 
In case of usin g Receive

 FIFO, set this bit to 1. 
 
[bit 10] FDRQ: Transmit FIFO data request bit 
This bit requests for the transmit FIFO data.   
If this bit is 1, the transmit data is being requested. If the Transmit Interrupt is enabled (FTIE=1) during 
this time, a transmit FIFO interrupt request is output. 
The FDRQ bit is set when: 

 The FBYTE (for transmission) is 0 (Transmit FIFO is empty). 

 Transmit FIFO is reset. 
 
The FDRQ bit is reset when: 

 This bit is set to 0. 

 Transmit FIFO is filled with data. 
 
Bit Description 
0  Does not request for the transmit FIFO data. 
1  Requests for the transmit FIFO data. 
 
 

 If the FBYTE (for transmission) is 0 , this bit cannot be set to 0. 

 If this bit is 0, the FSEL bit state cannot be changed. 

 If this bit is set to 1, it has no effect on the operation. 

 If a read-modify-write instruction is issued, 1 is read. 

 If a transmit interrupt has occurred and you have  written the required data in transmit FIFO, clear the 
interrupt request by setting the FIFO transmit data request bit (FCR1:FDRQ) to 0. 
 
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[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO buffer selection bit 
This bit selects the transmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO 1, and the receive FIFO is assigned FIFO2.   
If set to 1, transmit FIFO is assigned FIFO 2, and the receive FIFO is assigned FIFO1. 
Bit Description 
0 Set transmit FIFO as FIFO1, an d the receive FIFO as FIFO2. 
1 Set transmit FIFO as FIFO2, an d the receive FIFO as FIFO1. 
 
 

 This bit is not cleared by  FIFO reset (FCL2, FCL1=1). 

 To change this bit state, first disable the FIFO operation (FCR0:FE2, FE1=0). 
 
 
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5.10.  FIFO Control Register 0 (FCR0) 
The FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      -  R R/W  R/W R/W R/W  R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] Reserved bit 
When read, 0 is always read.   
When writing, always set to 0. 
 
[bit 6] FLST: FIFO re-transmit data lost flag bit 
This bit shows that the re-transmit data of transmit FIFO has been lost. 
The FLST bit is set when: 

 If the FLSTE bit of FIFO Control Register 1 (FCR1) is  1, the write pointer of transmit FIFO matches 
the read pointer which has been saved by the FSE T bit, and data is written in the FIFO buffer. 
 
The FLST bit is reset when: 

 FIFO is reset (FCL bit is set to 1). 

 The FSET bit is set to 1. 
 
If this bit is set to 1, the data which has been save d by the FSET bit and identified by the read pointer is 
overwritten. The data re-transmission cannot be set by the FLD bit even if an error has occurred. If this bit 
is set to 1 and if you wish to re-transmit data, first  reset FIFO. Then, write data in the FIFO buffer again. 
Bit Description 
0 No Data Lost has occurred. 
1  Data Lost has occurred. 
 
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[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred.   
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 

 If this bit is 1, data is being reloaded in the read  pointer. Therefore, data writing except for FIFO reset 
is disabled. 

 When FIFO is enabled or when data is being transmitted, this bit cannot be set to 1. 

 Set the SMR:TIE bit to 0 first, and set this bit to  1. Then, enable transmit FIFO and set the SMR:TIE 
bit to 1. 
 
[bit 4] FSET: FIFO pointer save bit 
This bit saves the read poin ter value of transmit FIFO.   
If the read pointer value is saved before being transm itted and if the FLST bit is 0, the data can be 
re-transmitted even if a communication error or others have occurred. 
If set to 1, the current read pointer value is saved.   
If set to 0, it has no effect. 
Bit Description 
0 Not  saved 
1 Saved 
 
 
This b it can b

e set to 1 only when the transmit byte count (FBYTE) is 0. 
 
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[bit 3] FCL2: FIFO2 reset bit 
This bit resets the FIFO2 value.   
If this bit is set to 1, the FIFO2 buffer is initialized.   
Only the FCR0:FLST bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 0 is always read. 
1  FIFO2 is reset. 
 
 

 Disable the FIFO2 operation first, and then reset the FIFO2 buffer. 

 Set the transmit FIFO interrupt enable bit to 0 before the execution. 

 The FBYTE2 register has the significant data count of 0. 
 
[bit 2] FCL1: FIFO1 reset bit 
This bit resets the FIFO1 value.   
If this bit is set to 1, the FIFO1 buffer is initialized.   
Only the FCR0:FLST bit is initialized, but th e other bits of FCR1/0 registers are kept. 
Description Bit 
During writing During reading 
0 No  effect. 0 is always read. 
1  FIFO1 is reset. 
 
 

 Disable the FIFO1 operation first, and then reset FIFO1. 

 Set the transmit FIFO interrupt enable bit to 0 before the execution. 

 The FBYTE1 register has the significant data count of 0. 
 
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[bit 1] FE2: FIFO2 operation enable bit 
This bit enables or disables the FIFO2 operation. 

 To use the FIFO2 operation, set this bit to 1. 

 If receive FIFO is selected by the FCR1:FSEL bit and if  a receive error has occurred, this bit is cleared to 
0. This bit cannot be set to 1 until the receive error is cleared. 

 To use FIFO2 as transmit FIFO, this bit must be  set to 1 or 0 when the transmit data is empty 
(SSR:TDRE=1). 

 To use FIFO2 as receive FIFO, this bit must be  set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and receive FIFO contains  no valid data (FBYTE2=0) while the I2C interface operation 
is disabled (ISMK:EN=0), the operation flag (IBCR:ACT)  is 0, or the interrupt flag (IBCR:INT) is 1. 

 To use FIFO2 as receive FIFO, this bit must be  set to 1 when the receive buffer is empty 
(SSR:RDRF=0) while the I2C interface operation is disabled  (ISMK:EN=0), the operation flag 
(IBCR:ACT) is 0, or the inte rrupt flag (IBCR:INT) is 1. 

 The FIFO2 state is held even if the FIFO2 operation is disabled. 
 
Bit Description 
0  Disables the FIFO2 operation. 
1  Enables the FIFO2 operation. 
 
 

 The enable or disable state must be switched only  when the IBSR:BB bit is 0 or when the IBCR:INT 
bit is 1. 

 If receive FIFO is selected and the reserved address is  detected, and if you wish to select the slave mode 
transmission, set this bit to 0 and set IBCR:ACKE  bit to 0 with an interrupt of reserved address 
detection. 

 If receive FIFO is selected and if the SSR:RDRF bit of  SSR is 1 when this bit is changed from 1 to 
0, receive FIFO is not disabl ed until the bit is set to 0. 

 If transmit FIFO is selected, FIFO2 contains data, and yo u wish to change this bit from 0 to 1, set the 
SMR:TIE bit to 0 first. Then, set this bit to 1, and set the SMR:TIE bit to 1. 
 
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[bit 0] FE1: FIFO1 operation enable bit 
This bit enables or disables the FIFO1 operation. 

 To use the FIFO1 operation, set this bit to 1. 

 If receive FIFO is selected by the FCR1:FSEL bit and if  a receive error has occurred, this bit is cleared to 
0. This bit cannot be set to 1 until the receive error is cleared. 

 To use FIFO1 as transmit FIFO, this bit must be  set to 1 or 0 when the transmit data is empty 
(SSR:TDRE=1). 

 To use FIFO1 as receive FIFO, this bit must be  set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and receive FIFO contains  no valid data (FBYTE2=0) while the I2C interface operation 
is disabled (ISMK:EN=0), the operation flag (IBCR:ACT)  is 0, or the interrupt flag (IBCR:INT) is 1. 

 To use FIFO1 as receive FIFO, this bit must be  set to 1 when the receive buffer is empty 
(SSR:RDRF=0) while the I2C interface operation is disabled  (ISMK:EN=0), the operation flag 
(IBCR:ACT) is 0, or the inte rrupt flag (IBCR:INT) is 1. 

 The FIFO1 state is held even if the FIFO1 operation is disabled. 
 
Bit Description 
0  Disables the FIFO1 operation. 
1  Enables the FIFO1 operation. 
 
 

 The enable or disable state must be switched only  when the IBSR:BB bit is 0 or when the IBCR:INT 
bit is 1. 

 If receive FIFO is selected and the reserved address is  detected, and if you wish to select the slave mode 
transmission, set this bit to 0 and set IBCR:ACKE  bit to 0 with an interrupt of reserved address 
detection. 

 If receive FIFO is selected and the SSR:RDRF bit is 1  when this bit is changed from 1 to 0, receive 
FIFO is not disabled until the bit is set to 0. 

 If transmit FIFO is selected, FIFO1 contains data, and if  you wish to change this bit from 0 to 1 state, 
set the SMR:TIE bit to 0 first. Then, set this  bit to 1, and set the SMR:TIE bit to 1. 
 
 
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5.11.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when certain number of data sets are 
received in the receive FIFO. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the effective data coun t in the FIFO buffer. The following table shows the 
relation between the FCR1:FSEL bit state to FBYTE. 
Table 5-3 Display of data count 
FSEL FIFO selection Data count display 
0  FIFO2:Receive FIFO, FI FO1: Transmit FIFO FIFO2:FBYTE2, FIFO1:FBYTE1 
1  FIFO2:Transmit FIFO, FIFO1:Receive  FIFO FIFO2:FBYTE2, FIFO1:FBYTE1 
 

 The initial value of data transfer count is 0x08 for the FBYTE register. 

 Set a data count to flag a receive interrupt for the FBYTE register of receive FIFO. If  this transfer data 
count matches the FBYTE register display, the interrupt flag (SSR:RDRF) is set to 1. 

 If both of the following conditions are satisfied and if the receive idle state continues for more than 8 
baud rate clocks, the interrupt flag (SSR:RDRF) is set to 1. 

 The receive FIFO idle detection  enable bit (FCR:FRIIE) is 1. 

 The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0 and counting for 8 clocks is 
restarted. If receive FIFO is disabled , this counter is reset to zero (0). If data remains in the receive FIFO 
and if receive FIFO is enabled,  the data counting is restarted. 

 To receive data in the master mode operation (maste r mode reception), set the SMR:TIE bit to 0, set 
the receive data count for the FBYTE register of tr ansmit FIFO, and set the FCR1:FDRQ bit to 0. The 
SCL clocks are output for the specified data count,  and then IBCR:INT bit is set to 1. The SMR:TIE bit 
must be set to 1 only after the FCR1:FDRQ bit is set to 1. 
 
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5. I2C Interface Registers 
 
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Chapter: I2C Interface (I2C Communications Control Interface) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  89 
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writingSets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets alread y written in the FIFO buffer but not transmitted yet 
During reception: The number of  data sets received in FIFO 
Write (Transfer data count)  During transmission: Set 0x00. 
During reception: Set the data count  to generate a receive interrupt. 
 
 The FBYTE value of transmit FIFO must be 8h00  except when data is received in the master mode 
operation. 

 During the master mode data reception, the transmit da ta count must be set only when transmit FIFO is 
empty and the SMR:TIE bit is 0. 

 When data is being received in th e master mode operation, the I2C interface operation can be disabled 
(ISMK:EN=0) only after transmit/receive FIFO has been disabled. 

 The FBYTE bit of receive FIFO must be set to 1 or larger. 

 Change this register under one of the following conditions: 

 When the I2C interface operation is  disabled (ISMK:EN=0) 

 When IBCR:INT=1 in case of SSR:DMA =0 and master mode reception 

 When SSR:TBI=1 in case of SSR:D MA=1 and master mode reception 

 A read-modify-write instruction cannot be used for this register. 

 Any setting exceeding the FIFO  capacity is inhibited. 

 To receive data in the master mode operation (maste r mode reception), do not write dummy data to the 
Transmit Data Register (TDR) when setting the SMR:TI E bit to 0 and setting the receive data count for 
the FBYTE register of transmit FIFO. 

 When all the following requirements  are met, the receive data full flag bit (SSR:RDRF) is not set to 1 
even though the effective data of  FBYTE setting number exist in the r eceive FIFO. If the FBYTE register 
is set to 2 or greater, this operation will not occur. 

 FBYTE is set to 1. 

 The effective data count is 1, same as  the number specified in FBYTE register. 

 When the multi function serial interface macro r eceives the data, and writes received data in the 
reception FIFO, the data of the receptio n FIFO are read at the same time.   
However, after that, the receive data full flag bit (S SR:RDRF) will be set to 1 at any of the following 
conditions. 

 The next data is received. 

 The receive idele state of 8 bits  or longer is detected when the receive FIFO idele is enabled 
(FCR:FRIIE=1)  
 
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