Fujitsu Series 3 Manual

							 
4. CAN Registers 
 
4.3.1. IFx Command Request Register (IFxCREQ) 
The IFx Command Request Register is used to select a message number of the message 
RAM and transfer data between the message RAM and Message Buffer Register. In basic 
test mode, IF1 is used to control sending and IF2 to control receiving. 
 Register configuration 
- IFx Command Request Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field BUSY Reserved ReservedReservedReservedReserved Reserved Reserved
Attribute R/W  R0,W0 R0,W0  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Command Request Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Message  Number 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 1 
 
  Register functions 
A message transfer starts between the message RAM and Message Buffer Register (Mask, Arbitration, 
Message Control, and Data Registers) immediately af ter a message number has been written to the IFx 
Command Request Register. This write operation sets  the BUSY bit to 1 and continues transfer 
processing while the BUSY bit is 1.  When transfer processing is ended, the BUSY bit is reset to 0. 
If the CPU accesses the Message Interface Register while the BUSY bit is 1,  the CPU waits until the 
BUSY bit is set to 0 (for 3 to 6 clock cycles  after data has been written to the Command Request 
Register). 
The method for using the BUSY bit is different in basic test mode. The IF1 Command Request Register, 
which is used as a send message, starts message sending when the BUSY bit is set to 1. When message 
transfer has finished successfully, the BUSY bit is  reset to 0. Resetting the BUSY bit to 0 enables 
canceling message transfer at any time. 
The IF2 Command Request Register, which is used for receiving message, stores the received message in 
the IF2 Message Interface Register wh en the BUSY bit is set to 1. 
[bit 15] BUSY: Busy flag bit    Other than basic test mode 
Bit Function 
0  Indicates that data transfer is not 
performed between the Message Interface 
Register and message RAM.    [Initial value] 
1  Indicates that data transfer is bei
ng performed between the Message Interface 
Register and message RAM. 
 
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  Basic test mode 
   IF1 Command Request Register 
Bit Function 
0  Disables message sending. 
1 Enables message sending. 
 
  IF2 Command Request Register 
Bit Function 
0 Disables message receiving. 
1 Enables message receiving. 
 
[bit 14:8] Reserved bits  Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7:0] Message Number: Message number (32 message buffers) 
Bit 7:0  Function 
0x00, 0x40, 0x60, 0x80,   
0xA0, 0xC0, 0xE0  Setting disabled. 
If specified, it is interpreted as 0x20, causing 0x20 to be read. 
0x01 - 0x20 
Specifies a message number to perform processing. 
0x21-0x3F, 
0x41-0x5F, 
0x61-0x7F, 
0x81-0x9F, 
0xA1-0xBF, 
0xC1-0xDF,  0xE1-0xFF  Setting disabled. If specified, it is interpreted as one of 0x01 to 0x1F, 
causing the interpreted value to be read. 
 
 
The B

USY bit can be read and written.  Therefore, writing any d
 ata to this bit does not affect operations, 
excluding in basic test mode (see  3.7 Test mode  for basic test mode). 
 
 
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4. CAN Registers 
 
4.3.2. IFx Command Mask Register (IFxCMSK) 
The IFx Command Mask Register is used to control the transfer direction between the 
Message Interface Register and message RAM and specify which data is to be updated. This 
register is invalid in basic test mode. 
 Register configuration 
- IFx Command Mask Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field ReservedReserved ReservedReservedReservedReserved Reserved Reserved
Attribute  R0,W0 R0,W0 R0,W0  R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Command Mask Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field WR/RD Mask Arb Control CIP TxRqst/
NewDat  Data A 
Data  B 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
  Register functions 
[bit 15:8] Reserved bits 
Reserved bits are read as 0, an d must be set to 0 when writing. 
[bit 7] WR/RD: Writing or reading control bit 
Bit Function 
0  Indicates that data is read from the 
message RAM. Reading from the message 
RAM is performed by writing data to the IFx Command Request Register. What 
data is to be read from the message RAM depends on the setting of the Mask, 
Arb, Control, CIP, TxRqst/NewDat, Data A, or Data B bit. 
[Initial value] 
1  Indicates that data is written to the 
message RAM. Writing to the message RAM 
is performed by writing data to the IFx Command Request Register.What data is 
to be written to the message RAM depends on the setting of the Mask, Arb, 
Control, CIP, TxRqst/NewDat,  Data A, or Data B bit. 
 
 
After resetting,  d

ata of the message RAM is undefined. The message RAM cannot be read while its data is 
undefined. 
 
Bit 6 to 0 in the IFx Command Mask Register are set to different values depending on the transfer direction 
specified with the WR
  or RD bit. 
 
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 When the transfer directi on is writing (WR/RD=1) 
[bit 6] Mask: Mask data update bit 
Bit Function 
0 Indicates that mask data (ID mask + MDir + MXtd) of a message object*1 is not 
updated. [Initial value] 
1 Indicates that mask data (ID mask + 
MDir + MXtd) of a message object*1 is 
updated. 
*1: See  4.4 Message objects . 
 
[bit 5]  Arb: Arbitration data update bit 
Bit Function 
0  Indicates that arbitration data (ID + Dir + Xtd + MsgVal) of a message object*1 is 
not updated.    [Initial value] 
1 Indicates that arbitration data (ID + Dir + Xtd + MsgVal) of a message object*1 is 
updated. 
*1: See 
4.4 Message objects . 
 
[bit 4] Control : Control data update bit 
Bit Function 
0 Indicates that control data (IFx Message Control Register) of a message object*1 
is not updated.    [Initial value] 
1 Indicates that control data (IFx Message Control Register) of a message object*1 
is updated. 
*1: See 
4.4 Message objects . 
 
[bit 3] CIP:  Interrupt clear bit 
If t
his bit is set to 0 or 1, it does not affect CAN controller operations. 
[bit 2] TxRqst/NewDat: Message transmission request bit 
Bit Function 
0  Indicates that the TxRqst bits of the me
ssage object*1 and CAN Transmit Request 
Register are not changed.    [Initial value] 
1  Indicates that the TxRqst bits of the me
ssage object*1 and CAN Transmit Request 
Register are set to 1 (transmission requested). 
*1: See  4.4 Message objects . 
 
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[bit 1] Data A: Data 0-3 update bit 
Bit Function 
0 Indicates that data 0-3 of a me
ssage object*1 is not updated. 
[Initial value] 
1  Indicates that data 0-3 of a message object*1 is updated. 
*1: See 4.4 Message objects . 
 
[bit 0] Dat a B: Data 4-
7 update bit 
Bit Function 
0  Indicates that data 4-7 of a me
ssage object*1 is not updated. 
[Initial value] 
1  Indicates that data 4-7 of a message object*1 is updated. 
*1: See 4.4 Message objects . 
 
 
  When  t

he TxRqst or NewDat bit of the IFx Command Mask Register is set to 1, the setting of the 
TxRqst bit in the  IFx

 Message Control Register becomes invalid. 
   This register is invalid in basic test mode. 
 
 
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 When the transfer directi on is reading (WR/RD=0) 
[bit 6] Mask: Mask data update bit 
Bit Function 
0 Indicates that data (ID mask + MDir + 
MXtd) is not transferred from a message 
object*1 to IFx Master Register 1 or 2.    [Initial value] 
1  Indicates that data (ID mask + MDir 
+ MXtd) is transferred from a message 
object*1 to IFx Master Register 1 or 2. 
*1: See  4.4 Message objects . 
 
[bit 5]  Arb: Arbitration data update bit 
Bit Function 
0  Indicates that data (ID + Dir + Xtd + Ms
gVal) is not transferred from a message 
object*1 to IFx Arbitration Register 1 or 2.    [Initial value] 
1  Indicates that data (ID + Dir + Xtd + 
MsgVal) is transferred from a message 
object*1 to IFx Arbitration Register 1 or 2. 
*1: See  4.4 Message objects . 
 
[bit 4] Control : Control data update bit 
Bit Function 
0 Indicates that data is not transferred fr
om a message object*1 to the IFx Message 
Control Register.    [Initial value] 
1  Indicates that data is transferred from
 a message object*1 to the IFx Message 
Control Register. 
*1: See  4.4 Message objects . 
 
[bit 3] CIP:  Interrupt clear bit 
Bit Function 
0 Indicates that the IntPnd bits of the me
ssage object*1 and CAN Interrupt Pending 
Register are held. [Initial value] 
1  Indicates that the IntPnd bits of the me
ssage object*1 and CAN Interrupt Pending 
Register are cleared to 0. 
*1: See  4.4 Message objects . 
 
[bit 2]  TxRqst/NewDat: Data update bit 
Bit Function 
0  Indicates that the NewDat bits of the message object*1 and CAN New Data 
Register are held.    [Initial value] 
1 Indicates that the NewDat bits of the message object*1 and CAN New Data 
Register are cleared to 0. 
*1: See 
4.4 Message objects . 
 
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[bit 1] Data A: Data 0-3 update bit 
Bit Function 
0 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is 
held.  [Initial value] 
1  Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is 
updated. 
*1: See  4.4 Message objects . 
 
[bit 0] Dat a B: Data 4-
7 update bit 
Bit Function 
0  Indicates that data of the message object
*1 and CAN Data Register B1 or B2 is 
held.  [Initial value] 
1  Indicates that data of the message object
*1 and CAN Data Register B1 or B2 is 
updated. 
*1: See  4.4 Message objects . 
 
 
  The IntP n

d and NewDat bits can be reset to 0 by reading a message object. However, the value before 
reset by read ing

 is set to the IntPnd and Ne wDat bits of the IFx Message Control Register. 
   This register is invalid in basic test mode. 
 
 
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4.3.3. IFx Mask Registers 1, 2 (IFxMSK1 ,IFxMSK2) 
The IFx Mask Registers 1 and 2 are used to write or read message object mask data of the 
message RAM. The specified mask data is invalid in basic test mode. 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx Mask Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field MXtd MDir ReservedMsk28-24 
Attribute  R/W R/W  R1,W1 R/W R/W R/W  R/W R/W 
Initial value 1 1 1  1 1 1 1 1 
 
- IFx Mask Register 2 (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Msk23-16 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1 1 1  1 1 1 1 1 
 
- IFx Mask Register 1 (High-order byte)  bit  15 14 13  12 11 10  9 8 
Field Msk15-8 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1 1 1  1 1 1 1 1 
 
- IFx Mask Register 1 (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field Msk7-0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 1 1 1  1 1 1 1 1 
  For the explanation of each b it in this register, see 4.4 Message objects . 
Read  1 in the reserved
 

bit (bit 13 of IFx Mask Register 2), and set 1 in write mode. 
 
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4.3.4. IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2) 
The IFx Arbitration Registers 1 and 2 are used to write or read message object arbitration data 
of the message RAM. This register is invalid in basic test mode. 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx Arbitration Register 2 (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field MsgValXtd Dir ID28-24 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Arbitration Register 2 (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field ID23-16 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Arbitration Register 1 (High-order byte)  bit  15 14 13  12 11 10  9 8 
Field ID15-8 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Arbitration Register 1 (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field ID7-0 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
  For the explanation of each b it in this register, see 4.4 Message objects . 
 
  If the Ms

gVal bit of a message object is cleared to 0  during t
 ransmission, the TxOk bit of the CAN Status 
Register is set to 1 when transmission has been completed. However, the TxRqst bits of the message 
object and CAN Transmit Request Register are not clea red to 0. Use the Message Interface Register to 
clear the TxRqst bit to 0. 
 
 
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4.3.5. IFx Message Control Register (IFxMCTR) 
The IFx Message Control Register is used to write or read message object control data of the 
message RAM. This register is invalid in basic test mode. The NewDat and MsgLst bits of the 
IF2 Message Control Register are used to perform normal operations. The DLC bits indicate 
the DLC of the received message. The other control bits are invalid (0). 
For the function of each bit, see 4.4 Message objects . 
 Register configuration 
- IFx Message Control Register (High-order byte) 
bit 15 14 13 12 11 10 9 8 
Field NewDatMsgLst IntPnd UMask TxIE RxIE RmtEn TxRqst 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
- IFx Message Control Register (Low-order byte)  bit  7 6 5  4 3 2 1 0 
Field EoB  Reserved Reserved Reserved DLC3-0 
Attribute R/W R0,W0 R0,W0  R0,W0  R/W R/W  R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
  For the explanation of each b it in this register, see 4.4 Message objects . 
 
  The v

alues of the TxRqst, NewDat, and IntPnd bits ar e set as shown below 
 depending on the setting of the 
WR or RD bit in the IFx Command Mask Register. 
   When the transfer directio n is writing (IFx Command  Mask Register: WR/RD=1) 
   The TxRqst bit of this register is valid only when the TxRqst or NewDat bit of the IFx Command 
Mask Register is set to 0. 
 
   When the transfer direction is reading (IFx Command Mask Register: WR/RD=0) 
  If the IntPnd bits of the message object and CAN Interrupt Pending Register are reset by setting the 
CIP bit of the IFx Command Mask Register to 1 and writing data to the IFx Command Request 
Register, the value of the IntPnd bit that is speci fied before reset is stored in this register. 
   If the NewDat bits of the message object and CAN New Data Register are reset by setting the 
TxRqst or NewDat bit of the IFx Command Mask  Register to 1 and writing data to the IFx 
Command Request Register, the value of the NewDat bit that is specified before reset is stored in 
this register. 
 
 
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