Fujitsu Series 3 Manual

							 
2. Configuration of USB Function 
 
2.  Configuration of USB Function 
Figure 2-1 shows the block diagram of the USB function 
 USB function block diagram 
Figure 2-1 USB function block diagram 
 
Endpoint 0
IN buffer On-chip bus
UDP
UDM
UDC
CPU 
interface
UDCC register UDCS register
Time stamp
UDC 
interface
USB clock (48MHz)
From USB clock 
generation unit
I/O
Interrupts
Interrupts
Stop signal 
from a device
SUSP
Endpoint 0
OUT buffer
Endpoint 1
Buffer
Endpoint 2Buffer
Endpoint 3
Buffer
Endpoint 4Buffer
Endpoint 5
Buffer
  
 
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CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
3.  Operations of USB Function 
The USB function supports the USB (Universal Serial Bus) communication protocol.Its 
hardware supports the basic protocol operation (handshake). Therefore, USB communication 
can be implemented by processing only transfer data. 
 
3.1 USB function operation  
3.2  Detection of connection and disconnection  
3.3  Operation of each register in response to a command  
3.4  Suspend function  
3.5  Wake-up function  
3.6  DMA transfer function  
3.7  NULL transfer function 
3.8  STALL response/release of endpoint 0  
3.9  Stall response/release of endpoints 1 to 5 
 
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3. Operations of USB Function 
 
3.1.  USB function operation 
To use the USB function, take the following steps for setup. 
1. Configure the USB clock generation unit while th e USB Enable Register (USBEN) disables USB 
operation (USBEN = 0). 
2.  Enable the USB clock output. 
3.  Enable USB operation (USBEN = 1). 
 
The USB function transfers packets bi-directionally to/from a host controller that supports the USB protocol. 
Connection with the host and devices, and configur ation are emulated. Communications are implemented 
subsequently in different transfer types using device drivers. 
The following explains the operation of USB communication between the host and devices by taking an 
enumeration for example. 
Movements of registers and USB packets are shown here to provide details of the entire process. 
  Emulation processing 
Emulation is the first process for USB to work, establishes connection between the host and devices. The 
host investigates what types of devices are connected  on the USB bus by using USB control transfer (a USB 
transfer type). (Defined  in the USB specification) This process uses EP0 (Endpoint 0) from the six 
Endpoints (as defined in the USB specification). 
To use EP1 to EP5, reception and processing on the USB bus are required in the following order: 
1.  Resetting the USB bus 
2.  Setting the address by SET_Address 
3.  Setting configuration by SET_Config 
 
 
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CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
Figure 3-1 Example USB cable pin connection 
 
  
Operation summary Direction
Operation does not start until the host detects 
USB bus connection 
Host  Device
detection
 pull-up on the USB bus.
Descriptor information 
Returns descriptor data to the host.
Host   Device
acquisition
 
Device address setting 
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   USB bus connection detection 
The connection is reported from a device to the host. 
The host monitors two signal lines (D+ and D-) on the USB bus, and found the connection of a device if 
either of the signals turns to HIGH level. 
For a detailed procedure explaining how to use the device in self-powered mode, see  3.2 Detection of 
con nectio
n a

nd disconnection .To use the device as bus-powered , follo
 w the procedure given in 
Register Initial Setting and Operation Start Procedures. 
  Register initial setting and operation start procedures 
The following shows an example initial setting procedure of USB function registers. 
1. Set EP0 configuration (such as packet size) by the EP0C register. 
2.  Set EPEN, DIR, or TYPE of each Endpoi nt by the EP1C to 5C registers. 
3.  Clear the RST bit in the UDCC register. 
4.  Clear BFINI in the EP0IS, EP0OS, and EP1S to EP5S registers. 
5.  Clear the HCONX bit in the UDCC register. 
 
  USB bus reset 
The USB device core is initialized when the host executes a bus reset on the device, but register and buffer 
states are not initialized. 
Take the following steps to process the device. (The pr ocess is not required in the initial bus reset after USB 
connection.) 
1. Initialize the buffer by the BFINI bit in the EP0I  Status Register (EP0IS), the BFINI bit in the 
EP0O Status Register (EP0OS), and the BFINI b it in the EP1 to EP5 Status Registers (EP1S to 
EP5S). 
2.  Return firmware control to th e state before the emulation. 
 
Descriptor information 
(device) acquisition
Host   DeviceAn arbitrary address is assigned by the host.
Host  Device  Returns descriptor data to the host.
Descriptor information  (configuration) acquisitio n
 
Host  Device Returns descriptor data to the host.
Host  Device
Configuration settingA configuration number is assigned by the host.
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3. Operations of USB Function 
 
 Descriptor acquisition 
When the host requests a device, the device reports data to the host in reply to the request. 
The communication is broken up into the following three stages. 
Figure 3-2 Communication stages 
 
 Setup stage   ->   Data stage   ->   Status stage   
 
The setup stage checks whether the device has received the packets from the host successfully. The 
descriptor information to be returned in the next stage is prepared in the send buffer in this stage. The data 
stage checks whether the host has sent data successfully.  In the status stage, the host sends a packet without 
data to end the transfer. 
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3. Operations of USB Function 
 
3.2.  Detection of connection and disconnection 
The following explains about detecting connection and disconnection to/from the USB host. 
 Example of USB system connection 
By connecting an external interrupt pin to the VBUS pin of the USB connector, and installing a pull-down 
resistor onto the VBSU signal, disconnection from the USB host can be detected. Figure 3-3 shows an 
example connection of USB c o

nn ector with D+, D- and VBUS. 
Figure 3-3 Example USB system configuration 
 
Install level shif ters if necessary
External interruptHCONX(GPIO) 0: pull-up 
connected
1: pull-up 
disconnected
1.5K
USB device
VBUS
USB IO USB IO
27
27
USB host
B connector
This LSI
D+ -D
  
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
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3. Operations of USB Function 
 
 Connection detection 
Figure 3-4 Connection detecting operation 
 
Connected to the host
VBUS ENx
ERx
[LBx, LAx]
HCONX
[0, 1] [0, 0]
Connection enabled
VBUS stables Source level changed
External interrupt enabled
  
 
A device finds and processes the connection with the host in the following sequence: 
1. The HCONX bit in the UDCC register must be set to 1. (When controlling a pull-up resistor on a 
general-purpose port, set the port to the pull-up resistor disconnection.) 
2.  Set the source level of external interrupts connected  with VBUS to HIGH level detection to enable 
interrupts. 
3.  Find the USB host connection by the detection of HIGH  level of the external interrupt pin, and waits 
for the period the VB US becomes stable. 
4.  Disable external interrupts once. Change the external interrupt cause level to LOW to clear the 
interrupt cause, and enable external interrupts again. 
5.  Configure the initial settings (In itialize all components including  the USB function registers.)See 
Register Initial Setting and Operation St art Procedures in this section. 
6.  Connect the pull-up resistor to D+ by clearing the HCONX bit in the UDCC register. *1 *2 
  *1 :  When control the pull-up resistor on a general-purpose port, clear the HCONX bit in the UDCC  register, and set the pull-up resistor control general-purpose port to the pull-up resistor connection. 
*2 :  Clear the HCONX bit even if the pull-up resistor is not controlled. 
 
  If an ex tern

al filter is installed on the external interrupt pin, the above VBUS stabilization period does not 
need to be  set b

y the program. 
 
 
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3. Operations of USB Function 
 
 Disconnection detection 
Figure 3-5 Connection detecting operation 
 
Disconnected 
from the host
VBUS
ENx
ERx
[LBx, LAx]
HCONX SUSP
USTP Returned from stop mode
[0, 0]
Source level changed
VBUS stabilization 
period or
Oscillation 
stabilization wait time
Disconnection  setting
[0, 1]
  
 
A device finds and processes the disconnection from the host in the following sequence: 
1. Find the disconnection of the USB host by detecting LOW level of the external interrupt pin 
connected to VBUS. 
2.  When returned from stop mode or timer mode 
  After the oscillation stabilization wait time, clear  in the order of SUSP in the UDCS register and 
USTP in the UDCC register. 
In other than stop mode and timer mode wait for the period the VBUS becomes stable. 
3.  Disable external interrupts once.Change the external interrupt cause level to HIGH to clear the 
interrupt cause, and enable external interrupts again. 
4.  Disconnect the pull-up resistor from D+ by se tting the HCONX bit in the UDCC register. *1*2 
  *1 :  When controlling the pull-up resistor on a general-purpose port, set the HCONX bit in the UDCC  register, and set the pull-up resistor control general-purpose port to the pull-up resistor connection. 
*2 :  Set the HCONX bit even if the pull-up resistor is not controlled. 
 
  If an ex tern

al filter is installed on the external interrupt pin, the above VBUS stabilization period does not 
need to be set b
 y the program. 
 
 
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3. Operations of USB Function 
 
3.3.  Operation of each register in response to a command 
The following explains the method (architecture) to process USB packets. Responding to 
CPU interrupts, the firmware sequence is processed for each handshake. This is equivalent to 
the processing of each packet on the stage basis. 
 Operation of each register in response to a read command 
The following explains the case of GetDescripter, SynchFrame, and class vendor commands. 
Figure 3-6 Operation of Each Register in Response to a Read Command 
 
  
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  Setup sequence 
Upon the receipt of the setup stag e, DRQO changes to 1.Immediately when DRQO has changed to 1, 
enter the CPU interrupt and check the  SETP flag. If the flag is 1, read required bits of the command in 
the receive buffer. (Not necessarily read all the eight bytes.) Subsequently, decode the command, 
configure required settings, clear the SETP flag  and the DRQO interrupt cause, and return. 
   Data stage sequence 
If the command decoding concludes that the data st age is in the IN direction, enable DRQIE,* and 
transfer outgoing data to the send buffer by the CPU  interrupt. When the transfer has finished, clear the 
DRQI interrupt cause, and return. 
*:  The DRQI interrupt cause is initially set to 1, and is only used to enable interrupts. 
DRQI is set when the data packet to the IN di rection has finished. The CPU interrupt is entered 
immediately when DRQI has been set, and outgoing data  is transferred to the send buffer in preparation 
for the next data packet. When the transfer has finished, interrupt cause DRQI, and return. 
Host   
Device SET 
UP
SETP 
DRQI 
Device   Host ACK
Setup stage Status stage Data stage
DRQO 
(1) Setup stage 
sequence
 
(2 ) Data stage 
sequence(3 ) Command end sequence
 
DRQIIE 
DRQOIE Cleared by 
software .Cleared by 
software .
ACKDATA0
Command read 
OUTIN
DATA0 
writeDATA1 write
IN
DATA 0
DATA 1
DATA1 ACK
ACK 
DATA1 
read
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3. Operations of USB Function 
 
  Command end sequence 
DRQO is set when the status stage  to OUT direction has finished. Immediately when DRQO is set, enter 
the CPU interrupt and check that the number of receive d data units is 0.In preparation for the next setup 
stage, interrupt cause DRQO, and return. 
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