Fujitsu Series 3 Manual

							 
3. Operations of Multifunction Timer 
 
Table 3-4 Example of Operation 1 – Register Settings 4 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
EG0[1:0] DC ch.0 operation state: 
EG1[1:0]  DC ch.1 operation state: 
ICE0 DC  ch.0 interrupt: 
ICE1 DC ch.1 interrupt: 
ICP0 1 ch.0 edge detection: Edge detected 
ICSA10 BR 
ICP1 0 ch.1 edge detect ion: Edge not detected 
ICCP0 HW  ICCP0 0x57FECapture ch.0 capture value 
EG0[1:0]  NM ch.0 operation state: 
EG1[1:0]  NM ch.1 operation state: 
ICE0 NM  ch.0 interrupt: 
ICE1 NM ch.1 interrupt: 
ICP0 0 ch.0 edge detection: Clear 
6 ICU 
ICSA10 BW  ICP1 1(RMW)ch.1 edge detection: Do nothing 
CST0 0 ch.0 operation state: Disabled 
CST1  0 ch.1 operation state: Disabled 
BDIS0  NM ch.0 OCCP buffer function:   
BDIS1  NM ch.1 OCCP buffer function:   
IOE0 NM  ch.0 interrupt:  
IOE1 NM ch.1 interrupt:  
IOP0 1 ch.0 match detection: Do nothing 
OCSA10 BW 
IOP1  1 ch.1 match detection: Do nothing 
OTD0  0 RT0 output level: Low 
OTD1  0 RT1 output level: Low 
Reserved NM  - 
CMOD NM ch.0/ch.1 operation mode: 
BTS0 NM  ch.0 buffer transfer: 
BTS1 NM ch.1 buffer transfer: 
OCU 
OCSB10BW  Reserved NM - 
EG0[1:0] 00 ch.0 operation state: Operation disabled 
EG1[1:0]  00 ch.1 operation state: Operation disabled 
ICE0 NM  ch.0 interrupt: 
ICE1 NM ch.1 interrupt: 
ICP0 1 ch.0 edge detection: Do nothing 
ICU ICSA10  BW 
ICP1  1 ch.1 edge detection: Do nothing 
CLK[3:0] NM Clock division pre-scaler setting: 
SCLR  1 Soft clear: Initialize FRT 
MODE  NM Count mode setting:   
STOP  1 FRT count operation: Stop counting 
BFE  NM TCCP buffer function: 
ICRE  NM Peak value detection interrupt: 
ICLR  1 Peak value detection: Do nothing 
Reserved NM  - 
IRQZE NM Zero value detection interrupt: 
IRQZF  1 Zero value detection: Do nothing 
TCSA0 HW 
ECKE NM Selection of clock used: 
7 
FRT  TCDT0 HW TCDT 0x0000Initialize FRT count value 
  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
515 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
3.2.  Example of Operation of Multifunction Timer - 2 
Example of Operation of Multifunction Timer - 2 explains the cases where each function 
block is operated in the following modes: FRT  :  Up/Down-count mode, with interrupt 
OCU  :  Up/Down-count mode (Active High), without interrupt 
WFG  :  RT-dead timer mode (Active High) 
  ADCMP/ATSA :  Instruct ADCunit0 to start scan conversion under the match condition for 
Up-counting 
 Time Chart 
 
Figure 3-2 Time Chart of Main Registers and I/O Signals of Each Block 
 
Ch.0
count
OCCP1 Buf.
RT0 output   0x5FFF
0x5FFF
0x0000
0x1800 0x2800 0x3800 0x4800 0x5800
0x0800
TCCP0 reg.
RTO0 output
RTO1 output
CPU operation timing
123 4 5
FRT
OCU
WFG ACCP0 reg.
ADC start trigger
ADCMP
/ATSA   0x2800 ( Only Up Count )0x4800 0x4000 0x3800 0x3000
0x4800 0x4000 0x3800 0x3000
OCCP1 reg.
RT1 output   No Use
ADC operation Zero interrupt
Dead time 67 9
8 4 5 6 7 4 56
7
8 8
  
 
Figure 3-2  shows the time chart of main registers and I/O  signals fo
 r each block. From top to bottom, the 
figure indicates CPU operation, FRT operation, OCU operation, WFG operation and ADCMP operation. 
The following section describes the operation of each functi on block and what is controlled from CPU at 
the timing 1 to 9. It also shows specific examples of CPU register settings at each of the timings. For details 
of register settings, see  4 Registers of Multifunction Timer. It should be noted that in addition to the 
abo ve, LSI 
I/

O port block, interrupt control block and ADC must be set separately. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
516 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
 Operation of FRT, OCU 
Timing 1 
  Set Up-count operation to FRT-ch.0 (TCSA0 register write). 
   Set an operating cycle to FRT-ch.0  (TCCP0 register write). In this example, 0x5FFF is set. When the 
FRT pre-scaler is set to 1/4 and PCLK to  40MHz, the count cycle of FRT is 4.915 s. 
   Connect and set FRT-ch.0 to OCU-ch.1 (OCFS10 register write). 
   Set OCU-ch.1 to Up/Down-count m ode (Active High) operation. Also specify the initial output level 
of the output signal (RT1) (OCSA10, OCSB10 and OCSC register write). 
   Set the timing of changing the output signal (RT1 ) for OCU-ch.1 (OCCP1 register write). In this 
example, 0x4800 is set. The value is written to  the buffer register, and then transferred to the 
OCCP1 register. 
Timing 2    Instruct FRT-ch.0 to start count operation (TCSA0 register write). 
   In Up/Down-count mode, FRT-ch.0 starts counting from 0x0000 and continues the Up-count 
operation until the TCCP value is reached (=0x5FFF),  as shown in the figure. After that, switch over 
the count direction and perform the Down-count operation until the TCCP value (=0x5FFF) is 
reached. Then, con tinue counting. 
Timing 3    Instruct OCU-ch.0/ch.1 to enable the operation (OCSA10 register write). 
Timing 4    When OCU-ch.1 detects that the value of the FRT counter has reached 0x4800 and matched the 
setting value of OCCP1 during the Up-count operation, it changes the output signal (RT1) from the 
Low to High level. 
Timing 5    When OCU-ch.1 detects that the value of the FRT counter has reached 0x4800 and matched the 
setting value of OCCP1 during the Down-count operation, it changes the output signal (RT1) from 
the High to Low level. 
Timing 6    CPU sets the timing of changing the output signal (RT1) for OCU-ch.1 in the next FRT cycle (OCCP1 
register write). As OCCP buffer function is valid an d Zero value detection transfer mode is selected, 
the written value is first stored in the buffer regist er. Then, when the value of the FRT counter reaches 
the Zero value (Timing 7), the written value is tran sferred to the OCCP1 register and reflected upon 
OCU output. For this reason, ev en if writing takes place before Timing 5, as indicated by  in the 
figure, it does not affect the timing of changing the output signal (RT1). 
Timing 7    When the count value reaches 0x0000, FRT-ch.0 generates Zero value detection interrupt to CPU 
(Zero value detection interrupt is not generated at Timing 3). 
   CPU determines that an interrupt has been generated from FRT-ch.0, because 1 is set to the Zero 
value detection flag of FRT-ch.0 (TCSA0 register read). 
   CPU clears the Zero value detection flag and retu rns from the interrupt (TCSA0 register write). 
After that, repeat Operations 4 to 7 so that PWM waveform with the peak value of the FRT counter 
symmetrical about the RT1 output can be achieved. 
  WFG’s Operation 
Timing 1 
  Initialize WFG-ch.10 to RT-dead timer mode  (Active High) (WFSA10 register write). 
   Set the dead dead time to WFG-ch10 (WFTM register  write). In this example, 0x0010 is set. When 
the WFG pre-scaler is set to 1/2 and PCLK to 40MHz, the dead time to be inserted is 0.8 s. 
   In this mode of WFG, signals at the same level as RT1 and the opposite level are output to the output 
signals of WFG (RTO0 and RTO1) respectively. 
Timing 4, 5    When the RT1 signal changes from the Low to High level (or from the High to Low level), a specified 
dead time (transistor response time at the destination of the output) is inserted into the RTO0 and 
RTO1 signals, as shown in the figure, and the output level is changed. 
   Non-overlap signal containing a dead time shown in the figure can be output to RTO0 and RTO1 by 
using the WFG function. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
517 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
 Operation of ADCMP/ATSA 
Timing 1 
  Set ADCMP-ch.0 to instruct ADC-unit0 to start  AD conversion with the match condition for FRT’s 
Up-count operation (ACSA and ACSB register write). 
   Initialize ATSA to select ADC-unit0’s conversion st art signal from ADCMP as the scan conversion 
start signal (ATSA register write). 
   Set the timing of starting AD conversion (ACCP0 regi ster write). In this example, 0x2800 is set. 
Timing 3    Instruct ADCMP-ch.0 to enable its operation (ACSA register write). 
Timing 8    When ADCMP-ch.0 and ATSA detect that the value of the FRT counter has reached 0x2800 during 
the Up-count operation, they output ADC-unit0’s scan conversion start signal. 
  Completion of Processing 
Timing 9 
The processing at Timing 9 indicates the procedure for completing the output of the PWM signal. 
  Disable the operation of OCU-  ch.1 (OCSA10 register write). 
   Set the level of the output signals (RT0, RT1) for OCU-ch.1 (OCSB10 register write). 
   Disable the operation of ADCMP -ch.0 (ACSA register write). 
   When the output of OCU stops, WFG does not perform its operation. 
   Instruct FRT-ch.0 to stop the count operation (TCSA0 register write). 
   Set 0x0000 to FRT’s count value (TCDT0 register write). 
 
The above example explained the operation with 1 channel of OCU, 1 channel of WFG and 1 channel of 
ADCMP. If OCU-3ch, WFG-3ch and ADCMP-3ch are connected to the same FRT to perform interlocking 
control, three-phase motor control can be achieved. 
  Details of Register Settings 
The procedure for register settings in Example of Operation – 2 is as follows. 
The meanings of the symbols in the table are the same as those in Example of Operation – 1.   
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
518 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
Table 3-5 Example of Operation 2 - Register Settings 1 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CLK[3:0]0010 Clock division pre-scaler setting: 1/4 
SCLR  0 Soft clear: Do nothing 
MODE  1 Count mode setting: Up/Down-count mode 
STOP  1 FRT count operation: Stop counting 
BFE  1 TCCP buffer function: Enable 
ICRE  0 Peak value detection interrupt: Disable 
ICLR  0 Peak value detection: Clear 
Reserved 000  - 
IRQZE 1 Zero value detection interrupt: Enable 
IRQZF  0 Zero value detection: Clear 
TCSA0 HW 
ECKE 0 Selection of clock to be used: Internal clock FRT 
TCCP0 HW TCCP 0x5FFFSet FRT cycle 
FSO0[3:0] Other FRT connected to ch.0: OCFS10 BW 
FSO1[3:0] 0000 FRT connected to ch.1: FRT ch.0 
CST0  Other ch.0 operation state: 
CST1  0 ch.1 operation state: Operation disabled 
BDIS0  Other ch.0 OCCP buffer function: 
BDIS1  0 ch.1 OCCP buffer function: Enable 
IOE0 Other  ch.0 interrupt: 
IOE1 0 ch.1 interrupt: Disable 
IOP0 Other ch.0 match detection: 
OCSA10 BW 
IOP1  0 ch.1 match detection: Clear 
OTD0  Other RT0 output level: 
OTD1  0 RT1 output level: Low 
Reserved 00  - 
CMOD 0 ch.0/ch.1 operation mode: Up/Down (Active High) 
BTS0 Other  ch.0 buffer transfer: 
BTS1 0 ch.1 buffer transfer: Zero value detection transfer 
OCSB10 BW 
Reserved 0  - 
MOD0 Other ch.0 operation mode: 
MOD1  1 ch.1 operation mode: Up/Down (Active High) 
MOD2  Other ch.2 operation mode: 
MOD3  Other ch.3 operation mode: 
MOD4  Other ch.4 operation mode: 
MOD5  Other ch.5 operation mode: 
OCSC BW 
Reserved 00 - 
1 
OCU 
OCCP1 HW OCCP 0x4800Specify ch.1 change timing 
  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
519 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
Table 3-6 Example of Operation 2 - Register Settings 2 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
DCK[2:0]001 Clock division pre-scaler setting: 1/2 
TMD[2:0] 100 Operation mode: Select RT-dead timer mode 
GTEN[1:0] 00 Gate signal generation: don’t care 
PSEL[1:0] 00 Connecting PPG: don’t care 
PGEN[1:0] 00 PPG reflection: don’t care 
DMOD  0 Output polarity: Active High 
WFSA10 HW 
Reserved 000  - WFG 
WFTM10HW WFTM 0x0010Set dead time value 
CE0[1:0]  00 ch.0 operation state: Operation disabled 
CE1[1:0]  Other ch.1 operation state: 
CE2[1:0]  Other ch.2 operation state: 
Reserved 00  - 
SEL0[1:0]01 Selection of ch.0 start timing: At Up-count only 
SEL1[1:0] Other Selection of ch.1 start timing: 
SEL2[1:0] Other Selection of ch.2 start timing: 
ACSA HW 
Reserved 00 - 
BDIS0 1 ch.0 buffer function: Disable 
BDIS1  Other ch.1 buffer function: 
BDIS2  Other ch.2 buffer function: 
Reserved 0  - 
BTS0 0 ch.0 buffer transfer: don’t care 
BTS1 Other  ch.1 buffer transfer: 
BTS2 Other ch.2 buffer transfer: 
ACSB BW 
Reserved 0  
ADCMP 
ACCP0 HW ACCP 0x2800Specify start timing for ADC0 
AD0S[1:0] 00 ADC0 scan conversion start: ADCMPch.0 
AD1S[1:0] Other ADC1 scan conversion function: 
AD2S[1:0] Other ADC2 scan conversion function: 
Reserved 00  - 
AD0P[1:0]00 ADC0 priority conversion start: ADCMPch.0 
AD1P[1:0] Other ADC1 priority conversion start: 
AD2P[1:0] Other ADC2 priority conversion start: 
1 
AT S A  AT S A   H W  
Reserved 00  - 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
520 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
Table 3-7 Example of Operation 2 – Register Settings 3 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CLK[3:0]NM Clock division pre-scaler setting: 
SCLR NM  Soft clear: 
MODE NM Count mode setting: 
STOP  0 FRT count operation: Start counting 
BFE  NM TCCP buffer function: 
ICRE  NM Peak value detection interrupt: 
ICLR  1(RMW)Peak value detection: Do nothing 
Reserved NM  - 
IRQZE NM Zero value detection interrupt: 
IRQZF  1(RMW)Zero value detection: Do nothing 
2 FRT 
TCSA0 HW 
ECKE NM Selection of clock  to be used

: Internal clock 
CST0 NM ch.0 operation state: 
CST1  1 ch.1 operation state: Operation enabled 
BDIS0  NM ch.0 OCCP buffer function: 
BDIS1  NM ch.1 OCCP buffer function: 
IOE0 NM  ch.0 interrupt: 
IOE1 NM ch.1 interrupt: 
IOP0 1 ch.0 match detection: Do nothing 
OCU OCSA10 BW 
IOP1  1 ch.1 match detection: Do nothing 
CE0[1:0] 01  ch.0 operation state: Operation enabled 
Connecting FRT: FRT ch.0 
CE1[1:0] 
NM ch.1 operation state: 
CE2[1:0]  NM ch.2 operation state: 
Reserved NM  - 
SEL0[1:0]NM Selection of ch.0 start timing: 
SEL1[1:0] NM Selection of ch.1 start timing: 
SEL2[1:0] NM Selection of ch.2 start timing: 
3 
ADCMP ACSA HW  Reserved NM - 
6 OCU  OCCP1  HW OCCP1  0x4000Specify ch.1 change timing 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
521 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
Table 3-8 Example of Operation 2 – Register Settings 4 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CLK[3:0]DC Clock division pre-scaler setting: 
SCLR DC  Soft clear: 
MODE DC Count mode setting: 
STOP  DC FRT count operation: 
BFE  DC TCCP buffer function: 
ICRE  DC Peak value detection interrupt: 
ICLR  DC Peak value detection: 
Reserved DC  - 
IRQZE DC Zero value detection interrupt: 
IRQZF  1 Zero value detection: Zero value detected 
TCSA0 HR 
ECKE DC Selection of clock used: 
CLK[3:0]NM Clock division pre-scaler setting: 
SCLR NM  Soft clear: 
MODE NM Count mode setting: 
STOP  NM FRT count operation: 
BFE  NM TCCP buffer function: 
ICRE  NM Peak value detection interrupt: 
ICLR  1(RMW)Peak value detection: Do nothing 
Reserved NM  - 
IRQZE NM Zero value detection interrupt: 
IRQZF  0 Zero value detection: Flag cleared 
7 FRT 
TCSA0 HW  ECKE NM Selection of clock used: 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
522 
MB9Axxx/MB9Bxxx  Series  
						

							 
3. Operations of Multifunction Timer 
 
Table 3-9 Example of Operation 2 – Register Settings 5 
Setting Timing  Name of 
Target Block  Name of 
Register Operation 
Bit Field Value Description of Setting 
CST0 NM ch.0 operation state: 
CST1  0 ch.1 operation state: Disable 
BDIS0  NM ch.0 OCCP buffer function:   
BDIS1  NM ch.1 OCCP buffer function:   
IOE0 NM  ch.0 interrupt: 
IOE1 NM ch.1 interrupt: 
IOP0 1 ch.0 match detection: Do nothing 
OCSA10 BW 
IOP1  1 ch.1 match detection: Do nothing 
OTD0  NM RT0 output level: 
OTD1  0 RT1 output level: Low 
Reserved NM  - 
CMOD NM ch.0/ch.1 operation mode: 
BTS0 NM  ch.0 buffer transfer: 
BTS1 NM ch.1 buffer transfer: 
OCU 
OCSB10BW  Reserved NM - 
CE0[1:0] 00 ch.0 operation state: Operation disabled 
CE1[1:0]  NM ch.1 operation state: 
CE2[1:0]  NM ch.2 operation state: 
Reserved NM  - 
SEL0[1:0]NM Selection of ch.0 start timing: 
SEL1[1:0] NM Selection of ch.1 start timing: 
SEL2[1:0] NM Selection of ch.2 start timing: 
ADCMP ACSA  HW 
Reserved NM  - 
CLK[3:0]NM Clock division pre-scaler setting: 
SCLR  1 Soft clear: Initialize FRT 
MODE  NM Count mode setting:   
STOP  1 FRT count operation: Stop counting 
BFE  NM TCCP buffer function: 
ICRE  NM Peak value detection interrupt: 
ICLR  1 Peak value detection: Do nothing 
Reserved NM  - 
IRQZE NM Zero value detection interrupt: 
IRQZF  1 Zero value detection: Do nothing 
TCSA0 HW 
ECKE NM Selection of clock used: 
9 
FRT  TCDT0 HW TCDT 0x0000Initialize FRT count value 
  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
523 
MB9Axxx/MB9Bxxx  Series  
						

							 
4. Registers of Multifunction Timer 
 
4.  Registers of Multifunction Timer 
This chapter describes the registers of the multifunction timer. 
 
4.1 Individual Notation and Common Notation of Channel Numbers in Descriptions of Functions  
4.2  List of Registers of Multifunction Timer  
4.3  Details of Register Functions  
4.4  Details of OCU Output Waveform  
4.5  Details of WFG Output Waveform 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  15: Multifunction  Timer 
MN706-00002-1v0-E 
524 
MB9Axxx/MB9Bxxx  Series