Fujitsu Series 3 Manual

							 
3. Explanation of Operations 
 
3.2.2. Priority conversion operation 
This section explains the priority conversion operation. 
This mode is used to give priority to a specific conversion process. Even when scan conversion is in 
progress, if priority conversion is started, the scan  conversion is interrupted immediately and the priority 
conversion is performed. When the priority conversion  is completed, the scan operation restarts from the 
channel where it was interrupted. If conversion with hi gher priority (priority level 1) is started while the 
conversion with lower priority (priority level 2) is pe rformed, the priority level 2 conversion is interrupted 
immediately and the priority level 1 conversion is pe rformed. When the priority level 1 conversion is 
completed, the priority level 2 conversion is restarted. 
Two levels of priority are given to  priority conversion. Priority level 1 is the highest and level 2 is the 
second. Trigger start by an external pin is assigned as the start factor at  priority level 1 and software/timer 
start is assigned as that at priority level 2. 
The input channels are selected in the Priority  Conversion Input Selection (PCIS) register. 
   The procedure for selecting channels at priority level 1 differs depending on the ESCE bit in the 
Priority Conversion Control (PCCR) register. 
When ESCE = 0:  The P1A [2:0] bits in the PCIS re gister are used. Only one of the eight channels, 
ch.0 to 7, can be selected. 
When ESCE = 1:  The setting of the P1A [2:0] bits in the PCIS register is ignored. Only one of  the eight channels, ch.0 to 7, can be selected with input from the external pin 
(ECS [2:0]). 
Example: ECS [2:0]  =  0b000 -> ch.0 
  =  0b010 -> ch.2 
 = 0b111 -> ch.7 
   The P2A [4:0] bits in the PCIS regi ster are used for selecting the channel at priority level 2. Only one 
of the multiple input channels can be selected. 
 
The start factor of A/D conversion differs depending on the priority level. 
  Priority level 1 (highest priority) conversion can be  started by a falling edge of external trigger input. 
To enable external trigger start, set th e PEEN bit to 1 in the PCCR register. 
   Priority level 2 conversion can be started by software or a timer. 
To start conversion by software, set the PSTR bit in  the PCCR register to 1. To start conversion by 
a timer, set the PHEN bit in the PCCR register to 1  to enable timer start. Conversion starts when 
the timers rising edge is detected . When conversion starts, the PCS bit  in the ADSR register is set to 
1. When the conversion is completed, the PCS bit is reset to 0. 
In priority conversion mode, the conversion cannot be  restarted. In addition, start factors at the same 
priority level are ignored. 
(A timer start factor is ignored during software-started operation.) 
If a priority level 1 start factor (external trigger) oc curs during conversion started by a priority level 2 
start factor (software or timer), the PCNS bit in th e A/D Status Register (ADSR) is set to 1 and the 
priority level 2 conversion is interrupted immediately.  When the priority level 1 conversion is completed, 
PCNS is reset to 0 and the interrupted priority level 2 conversion is restarted. If a priority level 2 start 
factor occurs during priority level 1 conversion, the pr iority level 2 start factor is reserved (retained) and 
PCNS is set to 1. When the priority level 1 conversion is completed, PCNS is reset to 0 and the 
priority level 2 conversion is started. 
Priority conversion can only be performed in one-shot mode for a single channel. 
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3. Explanation of Operations 
 
3.2.3. Priority levels and state transitions 
This section explains priority levels and state transitions. 
 Priority levels 
Table 3-1 Priority levels for the A/D converter 
Priority level  Conversion type  Start factor 
1 Priority level 1 conversion 
  Input from external trigger pin (at falling edge) 
2  Priority level 2 conversion  
  Software (when the PSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
3 Scan conversion  
  Software (when the SSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
 
  When a startup by priority conversion occurs during scan conversion 
The scan conversion operation is interrupted and priority conversion operation is performed. When the 
priority conversion operation is completed, the sc an conversion is restarted from the channel where it 
was interrupted. 
   When a startup at priority level 1 occurs  during conversion at priority level 2 
The priority level 2 conversion is interrupted and th e operation by the startup at priority level 1 is 
performed. When the priority level 1 operation is completed, the priority level 2 conversion is restarted 
automatically. 
   When a startup at priority level 2 occurs  during conversion at priority level 1 
The start factor at priority level 2 is retained. When  the priority level 1 conversion is completed, the 
priority level 2 conversion is started automatically. 
   When a startup of scan conversion occurs during priority level 1 conversion 
The start factor of the scan conversion is retained.  When the priority level 1 conversion is completed, 
the scan conversion operation is started automatically. 
   When a startup of scan conversion occurs during priority level 2 conversion 
The start factor of the scan conversion is retained.  When the priority level 2 conversion is completed, 
the scan conversion operation is started automatically. 
   While priority conversion is performed, start factor at  the same priority level are masked (the operation is 
not restarted). 
 
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3. Explanation of Operations 
 
 State transitions 
Figure 3-5 12-bit A/D converter state transitions 
000
Standby for A/D conversion
010
Priority conversion is in progress.
110
Priority level 1 conversion is in  progress.
Priority level 2 conversion is  pending.
011Priority conversion is in progress.
Scan conversion is  pending.
001
Scan conversion is in progress.
111
Priority level 1 conversion is in progress.
Priority level 2 conversion is pending .
Scan conversion is pending .
Scan conversion 
request
Scan conversion completed
Priority conversion  completed Priority conversion 
request Scan conversion 
request
Priority level 1  conversion completed Priority level 1 
conversion 
completed
Priority 
conversion  request Priority conversion 
request
Priority conversion  completed
Priority 
conversion 
request
Scan conversion  request
 
 
The operation states can be read from the SCS,  PCS, and PCNS bits of the ADSR register. 
Table 3-2 Correspondence between bits and operation states 
PCNS PCS SCS Explanation of states 
0 0  0 Standby for A/D conversion. 
0  0  1 Scan A/D conversion is in progress. 
0 1  0 Priority A/D conversion (priority level 1 or 2) is in progress. 
0 1  1 Priority A/D conversion (priority level 1 or
 2) is in progress. Scan conversion is 
pending. 
1 1  0 Priority A/D conversion (priority level 1)
 is in progress. Priority conversion 
(priority level 2) is pending. 
1 1  1 Priority A/D conversion (priority level 1) is in progress. Scan conversion and 
priority conversion (priority level 2) are pending. 
 
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CHAPTER  18-3: 12-bit  A/D Converter 
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3. Explanation of Operations 
 
3.3. FIFO operations 
The A/D converter has 16 FIFO stages for scan conversion and 4 FIFO stages for priority 
conversion. When conversion data is written in the specified count of FIFO stages, an 
interrupt is generated to the CPU. 
 
3.3.1 FIFO operations in scan conversion 
3.3.2  Interrupts in scan conversion 
3.3.3  FIFO operations in priority conversion 
3.3.4  Interrupts in priority conversion 
3.3.5  Validity of FIFO data 
3.3.6  Bit placement selection for FIFO data registers 
 
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CHAPTER  18-3: 12-bit  A/D Converter 
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3. Explanation of Operations 
 
3.3.1. FIFO operations in scan conversion 
This section explains FIFO operations in scan conversion. 
Sixteen FIFO stages are incorporated for writing scan conversion data. After reset, they are in empty state 
and the SEMP bit in the Scan Conversion Control Register is set to 1. When A/D conversion of one 
channel is completed, the conversion result, start factor , and conversion channel are written in the first FIFO 
stage. This resets SEMP to 0. The conversion resu lt, start factor, and conversion channel for the next 
channel are written sequentially in the second FIFO stage. 
When such data is written in all of the 16 stages, the SFUL bit is set to 1 to indicate that FIFO is in full 
state. If conversion is performed and  an attempt is made to write data in FIFO when FIFO is in full state, the 
SOVR bit is set to 1 and the data is di scarded (cannot overwrite the existing data). 
To clear the data in FIFO, set the SFCLR bit in the S can Conversion Control register to 1. FIFO goes to 
the empty state and the SEMP bit is set to 1. 
Data in FIFO can be read sequentially by reading the  Scan FIFO Data Register (SCFD). To perform a byte 
(8 bits) access to this register, read the most significa nt byte (bit 31:24) to shift FIFO (reading the other 
bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO). To  perform a half word (16 bits) access to this register, 
read the most significant half word (bit 31:16) to shif t FIFO (reading the other byte (bit 15:0) does not shift 
FIFO). Performing a word (32 bits) acces s to this register shifts FIFO. 
 
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CHAPTER  18-3: 12-bit  A/D Converter 
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MB9Axxx/MB9Bxxx  Series  
						

							 
3. Explanation of Operations 
 
3.3.2. Interrupts in scan conversion 
This section explains interrupts in scan conversion. 
Figure 3-6 FIFO interrupt settings and FIFO operations 
 
FIFO interrupt 
request FIFO stage 
count settingValid FIFO 
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
  
 
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO 
Stage Count Setup Register (SFNS) is written in FIFO,  the interrupt request bit (SCIF) in the A/D Control 
Register (ADCR) is set to 1. If the interrupt enable  bit (SCIE) is set to 1, an interrupt request is 
generated to the CPU. 
The following explains FIFO st age count interrupt methods for each scan conversion mode. 
1.  One-shot mode for a single channel 
To generate an interrupt after the completion of one conversion process for the specified channel, set 
SFS [3:0] = 0x0. When conversion data is written in  the first FIFO stage, SCIF is set to 1. 
 
If SFS [3 :0

] is set to 0x1 or more (two stages or more ), interrupts are no
 t generated until conversion data is 
written into FIFO by the  specified stage count. 
 
2. Continuous mode for a single channel 
To generat
 e an interrupt after the completion of one conversion process for the specified channel, set 
SFS [3:0] = 0x0. When conversion data is written in  the first FIFO stage, SCIF is set to 1. 
To generate an interrupt at the completion of a number of times of conversion of the specified 
channel, set SFS [3:0] to 0x1 or more (two stag es or more). For example, set SFS [3:0] = 0x3 to 
generate an interrupt after four repeats. 
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CHAPTER  18-3: 12-bit  A/D Converter 
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3. Explanation of Operations 
 
3. One-shot mode for multiple channels 
To generate an interrupt after the completion of conversion of the multiple specified channels, set the 
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO 
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels 
is completed, SCIF is set to 1. 
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a value 
less than the number of selected channels. 
4.  Continuous mode for multiple channels 
To generate an interrupt after the completion of the first scan of the multiple specified channels, set 
the FIFO stage count according to the number of channels. If eight channels are selected, set the 
FIFO stage count by setting SFS [3:0] = 0x7. When  the conversion of the last one of the selected 
channels is completed, SCIF is set to 1. 
To generate an interrupt after the completion of the second scan, set the FIFO stage count to twice 
the number of selected channels.  For example, when four channels are selected, set the FIFO stage 
count to 8 (SFS [3:0] = 0x7). An interrupt is  generated when the second scan is completed. 
Because the FIFO stage count can be set to any valu e, an interrupt can be generated at any desired 
timing. 
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CHAPTER  18-3: 12-bit  A/D Converter 
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MB9Axxx/MB9Bxxx  Series  
						

							 
3. Explanation of Operations 
 
3.3.3. FIFO operations in priority conversion 
This section explains FIFO operations in priority conversion. 
Four FIFO stages are incorporated for writing priority conversion data. After reset, they are in empty state 
and the PEMP bit in the Priority Conversion Contro l Register is set to 1. When one A/D conversion 
process is completed, the conversion  result, start factor, and conversion channels are written in the first 
FIFO stage. This resets SEMP to 0. The conversion result and conversion channels for the subsequent 
conversion processes are written in  the corresponding FIFO stages. 
When such data is written in all of the 4 stages, the PFUL  bit is set to 1 to indicate that FIFO is in full 
state. If conversion is performed and  an attempt is made to write data in FIFO when FIFO is in full state, the 
POVR bit is set to 1 and the data is di scarded (cannot overwrite the existing data). 
To clear the data in FIFO, set the PFCLR bit in the Pr iority Conversion Control Register to 1. FIFO goes 
to the empty state and the PEMP bit is set to 1. 
Data in FIFO can be read sequentially by reading the  Priority FIFO Data Register (PCFD). To perform byte 
(8 bits) access to this register, read the most significa nt byte (bit 31:24) to shift FIFO (reading the other 
bytes (bit23:16, bit15:8, bit7:0) does not shift FIFO). To  perform a half word (16 bits) access to this register, 
read the most significant half word (bit 31:16) to shif t FIFO (reading the other byte (bit 15:0) does not shift 
FIFO). Performing a word (32 bits) acces s to this register shifts FIFO. 
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CHAPTER  18-3: 12-bit  A/D Converter 
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MB9Axxx/MB9Bxxx  Series  
						

							 
3. Explanation of Operations 
 
3.3.4. Interrupts in priority conversion 
This section explains interrupts in priority conversion. 
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion 
FIFO Stage Count Setup Register (PFNS) is written in  FIFO, the interrupt request bit (PCIF) in the A/D 
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is 
generated to the CPU. 
The following explains FIFO stage count interrupt methods in priority conversion. 
To generate an interrupt after the completion of one conversion process for the specified channel, set 
PFS [1:0] = 0x0. When conversion data is written in  the first FIFO stage, PCIF is set to 1. 
 
If PFS[1 :

0] is set to 0x1 or more (two stages or more), interrupts are not generated until conversion data is 
written into  FIFO b

y the specified stage count. 
 
 
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CHAPTER  18-3: 12-bit  A/D Converter 
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3. Explanation of Operations 
 
3.3.5. Validity  of  FIFO  data 
This section explains restrictions on reading FIFO data registers. 
The bit 12 of the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion FIFO Data Register 
(PCFD) comes with the INVL (A/D conversion result disable) bit which indicates data validity. During 
reading FIFO data registers, the INVL bit is set to 0 if data is valid while the INVL bit is set to 1 if data 
is invalid. 
For word (32 bits) reading, data validity can be checked by the INVL bit. 
For half word (16 bits) reading which does not use in terrupts or empty bits (SEMP, PEMP), always start 
reading from the least significant 16 bits including the INVL bit. If the INVL bit is    1 at this time, 
reading the most significant 16 bits is prohibited. The most significant 16 bits must be read only when the 
INVL bit is 0. 
For byte (8 bits) reading which does not use interrupts or empty bits (SEMP, PEMP), always start reading 
from bit15:8 including the INVL bit. If the INVL bit is 1 at this time, reading bit 31:24, bit 23:16, or bit 
7:0 is prohibited. They must be read only when the INVL bit is 0. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
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MB9Axxx/MB9Bxxx  Series