Fujitsu Series 3 Manual

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 Description of Each State 
Disable state  
See the hardware transfer (EM=0)  procedure. 
Wait -1st -trigger  state  
See the hardware transfer (EM=0)  procedure. 
Transfer state  
In this state, the channel to be controlled has received the first transfer request from the Peripheral. A 
channel in this state performs transfer operation as specified.  In the case of EM=1 , it moves to 
Wa i t -1st -trigger  state, o nce all the transfer operation is completed . It also changes its state upon 
instruction from CPU.  
Pause  state  
See the hardware transfer (EM=0)  procedure. 
 Explanation of Control Procedure  
1. Disable state / Preparation for transfer  
See Step 1 in the hardware transfer (EM=0)  procedure.  
To  s e t  EM=1 , set all of the reload specifications for the transfer content (R C, RS, RD) in order to 
prevent data transfer in an unintended address area. Also, CI is not set, because it is meaningless to 
generate a successful transfer completion interrupt from DMAC. EI is set to generate an unsuccessful 
transfer completion interrupt  from DMAC. 
2.  Disable  state => Wait -1st -trigger state / Enabling transfer  
See Step 2 in the hardware transfer (EM=0)  procedure.  
3.  Wait -1st -trigger state / Start of transfer  
See Step 3 in the hardware transfer (EM=0)  procedure.  
4.  Transfer state  
See Step 4 in the hardware transfer (EM=0)  procedure.  
5.  Transfer state  => Wait -1st -trigger  state / Successful completion of transfer  
When transfers are successfully completed for the number of times calculated by (BC+1) x (TC+1), the 
channel in Transfer state  does not clear EB but does clear PB and ST and moves to  Wa i t-1st -trigger . It 
sets SS=101 to provide the notification of the successful completion.  As CI is not set, no successful 
transfer completion interrupt is generated. Since RC, RS and RD are set, the specifications o f the 
transfer content of BC, TC, DMACSA  and  DMACDA  are reloaded.  
6.  Transfer state  => Wait-1st -trigger  state / Transfer error end  
See Step 6 in the hardware transfer (EM=0)  procedure.  
In the case of EM=1 , EB is not cleared even if the transfer ends due to an  error. It clears PB and ST, 
moves to  Wa i t-1st -trigger  state and waits for the next transfer request. Therefore, it is recommended not 
to use DMA transfer with EM=1 in an address area where a transfer error may occur.  
7.  Transfer  state  =>Wait -1st -trigger  state  /End of  Peripheral  stop request 
See Step 7 in the hardware transfer (EM=0)  procedure.  
In the case of EM=1 , EB is not cleared even if a stop request is issued from the Peripheral. It clears PB 
and ST and moves to  Wa i t-1st -trigge r state. Since RC, RS and RD are set, the specifications of the 
transfer content of BC, TC, DMACSA  and  DMACDA  are reloaded. As EI is set, an unsuccessful 
transfer completion interrupt is generated.  
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8. Wait -1st -trigger  state / Post -transfer process  
In the case of EM=1 , EB is not cleared upon the completion of the transfer. (DE=1, EB=1, DH=0000, 
PB=0)  is set and it moves to  Wa i t-1st -trigger  state. When the next transfer request is generated from the 
Peripheral, therefore, the next transfer starts without an instruction from CPU.  
If it mo ves to Wa i t-1st -trigger  state due to a stop request from the Peripheral, an unsuccessful 
completion interrupt occurs and that state can be confirmed. Also, the transfer request signal is masked 
while the stop request signal is asserted. Even if the next tr ansfer request signal is asserted from the 
Peripheral, it will not be recognized and the channel to be controlled will remain in Wa i t -1st -trigger  state, 
waiting for an instruction from CPU.  
In the above case, SS is read from CPU to check the state of the t ransfer completion. The interrupt 
signal is deasserted by clearing SS from CPU. CPU clears EB and it returns to Disable state (this 
operation is the operation shown in Step 15 of the hardware transfer (EM=1)  procedure). The  transfer 
request signal and the  stop request signal from the Peripheral are deasserted, as shown in Step 7 of the 
hardware transfer (EM= 0) procedure  
9.  Transfer state  => Disable  state / Completion of transfer by  EM=0 
The operation can exit from the loop of  Wa i t-1st -trigger  state and  Transfer state by writing  EM=0 from 
CPU. At the timing when the transfer stops after the instruction, EB, ST and PB are cleared and the 
Transfer state changes to Disable state (DE=1, EB=0, DH=0000, PB=0)  to successfully complete the 
transfer. In this case, no suc cessful transfer completion interrupt is generated, as CI is not set.  
10.  Transfer  state, Pause  state => Disable  state / Forced termination of transfer  
See Step 8 in the hardware transfer (EM=0)  procedure.  
The operation can exit from the loop of  Wa i t-1st -trigg er state and  Transfer state by an operation disable 
instruction. When an instruction to disable individual -channel operation is issued, the relevant channel 
moves to Disable state (DE=1, EB=0, DH=0000, PB=0)  and stops the operation. When an instruction to 
enable all -channel operation is issued, it moves to Disable state (DE=0, EB=1, DH=0000, PB=0)  and 
stops the operation. In the case of an instruction to disable all- channel operation, EB is not cleared 
either; therefore, attention must be paid.  
When the ope ration exits from Transfer state, an unsuccessful transfer completion interrupt occurs 
because it is unsuccessful completion due to the forced stop. When it exits from  Wa i t-1st -trigger  state, 
the enabled transfer is cancelled (this operation is the operati on shown in Step 15 of the hardware 
transfer (EM=1)  procedure).  
11.  Disable state / Post -transfer processing  
See Step 9 in the hardware transfer (EM=0)  procedure.  
12.  Transfer state, Pause state / Transfer pause  
See Step 10 in the hardware transfer (EM=0)  procedur e. 
13.  Pause state  
See Step 11 in the hardware transfer (EM=0)  procedure.  
14.  Pause state / Cancellation of transfer pause  
See Step 12 in the hardware transfer (EM=0)  procedure.  
15.  Operation in Disable state and Wait -1st -trigger  state 
See Step 13 in the hardware tran sfer (EM=0)  procedure.  
In the case of EM=1 , the Transfer state changes directly to  Wa i t-1st -trigger  state. Therefore, the 
specifications of the transfer content cannot be rewritten during the repeated transfer operation 
( rewriting the registers DMACSA, DMACDA, DMACB[31:1]  and  DMACA[28:0] ). 
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Additional Matter 1  
See Additional Matter 1 in the hardware transfer (EM=0)  procedure.  
Additional Matter  2 
See Additional Matter 2 in the hardware transfer (EM=0)  procedure.  
In the case of EM=1 , Additional Matter 2 does not apply, because EB is not cleared during the transfer 
operation.  
Additional Matter  3 
See Additional Matter 3 in the hardware transfer (EM=0)  procedure.  
Additional Matter  4 
See Additional Matter 4 in the hardware transfer (EM=0)  procedure.  
The following explains what must be noted when setting interrupts from DMAC with EM=1 . As  the 
target channel does not change from  Wa i t-1st -trigger  state due to an unsuccessful completion interrupt 
by a stop request from the Peripheral, the interrupt signal is not deasserted until it is cleared from CPU. 
Similarly, as the target channel moves to Disable state due to an unsuccessful transfer completion 
interrupt by a stop request from software, the interrupt signal is not deasserted until it is cleared from 
CPU. Other succ essful transfer completion interrupts and unsuccessful transfer completion interrupts 
may be deasserted at a timing that is not intended by CPU, if the relevant channel moves to Transfer 
state. Therefore, attention must be paid.  
Additional Matter  5 
See Add itional Matter 5 in the hardware transfer (EM=0)  procedure.  
 
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5.  Registers of DMAC 
This chapter describes each register function of DMAC.  
 
5.1 List of Registers  
5.2  Entire  DMAC  Configuration Register (DMACR ) 
5.3  Configuration A  Register  (DMACA ) 
5.4  Configuration B Register  (DMACB ) 
5.5  Transfer Source Address  Register  (DMACSA ) 
5.6  Transfer Destination Address Register  (DMACDA ) 
5.7  Notes  on Register Setting  
 
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5.1.  List of Registers  
Table 5-1 shows a list of DMAC control registers. 
Table 5-1  List of DMAC Control Registers  
Abbreviation Ch. Controlled Register name See 
DMACR All Entire DMAC configuration register 5.2 
DMACA0 
ch.0 
Configuration A register 5.3 
DMACB0 Configuration B register 5.4 
DMACSA0 Transfer source address register 5.5 
DMACDA0 Transfer destination address register 5.6 
DMACA1 
ch.1 
Configuration A register 5.3 
DMACB1 Configuration B register 5.4 
DMACSA1 Transfer source address register 5.5 
DMACDA1 Transfer destination address register 5.6 
DMACA2 
ch.2 
Configuration A register 5.3 
DMACB2 Configuration B register 5.4 
DMACSA2 Transfer source address register 5.5 
DMACDA2 Transfer destination address register 5.6 
DMACA3 
ch.3 
Configuration A register 5.3 
DMACB3 Configuration B register 5.4 
DMACSA3 Transfer source address register 5.5 
DMACDA3 Transfer destination address register 5.6 
DMACA4 
ch.4 
Configuration A register 5.3 
DMACB4 Configuration B register 5.4 
DMACSA4 Transfer source address register 5.5 
DMACDA4 Transfer destination address register 5.6 
DMACA5 
ch.5 
Configuration A register 5.3 
DMACB5 Configuration B register 5.4 
DMACSA5 Transfer source address register 5.5 
DMACDA5 Transfer destination address register 5.6 
DMACA6 
ch.6 
Configuration A register 5.3 
DMACB6 Configuration B register 5.4 
DMACSA6 Transfer source address register 5.5 
DMACDA6 Transfer destination address register 5.6 
DMACA7 
ch.7 
Configuration A register 5.3 
DMACB7 Configuration B register 5.4 
DMACSA7 Transfer source address register 5.5 
DMACDA7 Transfer destination address register 5.6 
 
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5.2.  Entire DMAC  Configuration Register  (DMACR ) 
This section describes  entire DMAC configuration re gister (DMACR).  
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field DE DS - PR DH[3:0] - - - - - - - - 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field - - - - - - - - - - - - - - - - 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
[bit31] DE : DMA Enable  (all-channel operation enable bit)  
This bit controls the ena bling and disabling of transfer operations for all of the channels.  
When  "1" is set to this bit, the operations of all of the channels are enabled and each channel operates 
according to its settings.  
When  "0" is set to this bit, the operations of all of th e channels are disabled, and no transfer is performed 
until  "1" is set to the bit. Also, a channel in the middle of its transfer operation is forced to stop the transfer.  
This bit can be used to force all of the channels that are currently performing a tra nsfer to stop it and reset 
the configuration register.  
bit31 Function 
0 Disables the operations of all of the channels. (Initial value) 
1 Enables the operations of all of the channels. 
 
[bit30] DS : DMA Stop  
This bit indicates the transfer state of all of the channels.  
If either of the following conditions is established during transfer operation, the bit is set to "1"  by DMAC. 
⋅   When  "0" is written to the DMACR/DE  bit and then the transfers of all of the channels are completed.  
⋅   When  other than "  0000" is  written to the  DMACR/DH  bit and then the transfers of all of the channels 
pause.  
 
When  DMACR/DE=1  and  DMACR/DH=0000  are set and all of the channels become enabled to operate, 
this bit is set to "0"  by DMAC. 
Although the attribute of this bit is R/W, writing to it by CPU does not affect DMAC ’s operation. If, 
however, the DMACR register needs to be updated without affecting the state of this bit, first read from this 
bit and then rewrite the same value.  
bit30 Function 
0 Clears the disabling of all
-channel op eration or the setting of all -channel pause. (Initial value) 
1 The transfers of all of the channels have stopped due to the disabling of 
all- channel operation or the setting of all -channel pause.  
 
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[bit29] Reserved  
 
[bit28] PR : Priority Rotation  This bi t controls the order of transfer priority among channels.  
When this bit is set to "0" , the priority order is fixed for all of the channels.  
When this bit is set to "1" , the priority order is determined in a rotation method for all of the channels.  
bit28 Function 
0 Fixes the priority order.
 (ch.0>ch.1>ch.2>ch.3>ch.4>ch.5>ch.6>ch.7) (Initial value) 
1 Applies the rotation method to the priority order. 
 
For selection of the transfer priority order, see Section 3.5 . 
[bit27:24] DH : DMA Halt (All- channel pause bit) 
This bit controls the pause/cancellation of transfer operations for all of the channels.  
When this bit is set to a value other than " 0000", all of the channels that are currently performing a transfer 
are put on pause. Wh en it is set to "0000", the transfers are resumed.  
Even if a transfer request from an external/peripheral device is asserted, the channels in Pause state ignore 
the transfer request. In the cases of Block transfer and Burst transfer, the relevant channel d oes not start a 
transfer, even if the pause is cleared. In order to complete a transfer when a pause is set during the transfer, 
an additional transfer request is required after the pause is cancelled.  
This bit can be used to put a transfer on pause withou t resetting the configuration registers of all of the 
channels.  
bit27:24 Function 
0000 Cancels the pause of transfers for all of the channels. (Initial value) 
Other than 0000 Puts the transfers of all of the channels on pause. 
 
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5.3.  Configuration A Register  (DMACA ) 
This section describes  configuration A  register  (DMACA ). 
 
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 
Field EB PB ST IS[5:0] - - - BC[3:0] 
Attribute R/W R/W R/W R/W R/W R/W R/W R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 
Field TC[15:0] 
Attribute R/W 
Initial 
Va l u e 0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0 
 
[bit31] EB : Enable Bit (individual -channel operation enable bit)  
This bit controls the enabling and disabling of the transfer operation of a n individual channel. 
When this bit is set to "1" , the relevant channel is enabled to operate and waits for a trigger to start its 
transfer operation (the DMACR/DE  must be set to "1" ). 
If the EM bit (DMACB[0])  is not set to "1", DMAC clears this bit to "0"  upon the completion of the 
transfer.  
When this bit is set to "0" , the relevant channel is disabled to operate and does not perform transfer 
operation until it is set to "1" . Also, if it is in the middle of transfer operation, it is forced to stop the tran s fe r. 
This bit can be used to force the relevant channel that is currently in transfer operation to stop it and reset 
the configuration register.  
bit31 Function 
0 The operation of the relevant channel is disabled. (Initial value) 
1 The operation of the relevant channel is enabled. 
 
[bit30] PB : Pause Bit (individual -channel pause bit)  
This bit controls the pause/cancellation of the transfer operation of an individual channel.  
When this bit is set to "1"  and the relevant channel is currently in transfer o peration, it puts the transfer on 
pause. When this bit is set to "0" , it resumes the transfer. 
This bit is cleared to  "0", when the transfer operation of the  channel is completed. 
Even if a transfer request from an external/peripheral device is asserted, the channels in Pause state ignore 
the transfer request. In the cases of Block transfer and Burst transfer, the relevant channel does not start a 
transfer, even if the pause is cleared. In order to complete a transfer when a pause is set during the transfer , 
an additional transfer request is required after the pause is cancelled.    
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This bit can be used to put a transfer on pause without resetting the configuration register of the relevant 
channel.  
bit30 Function 
0 Cancels the pause of the transfer of the relevant channel. 
1 Puts the transfer of the relevant channel on pause. 
 
[bit29] ST : Software Trigger  
This bit is used to generate a software transfer request  for an individual channel. 
When this bit is set to "1" , a trigger is generated by the software transfer request and the relevant channel 
starts its transfer. After the completion of the transfer, DMAC clears this bit to "0". 
When this bit is set to "0"  during the transfer, the transfer stops.  
bit29 Function 
0 No software transfer request (Initial value) 
1 Software transfer request available 
 
[bit28:23] IS : Input Select  
These bits select the trigger for transfer requests.  
When the transfer trigger is set to software request (ST=1) , set the IS bit to "000000". 
When the transfer trigger is set to har dware request, specify which Peripheral ’s interrupt signal to be used to 
start transfer. Any Peripheral can be selected for all of the channels.  
The hardware transfer request signal to be connected to DMAC varies depending on the model. Check the 
transfer  request signal to be connected in " 2.2 I/O Signals of DMAC " before setting the selection.  
bit28:23 Function 
000000 Software (Initial value) 
100000 IDREQ[0] 
100001 IDREQ[1] 
100010 IDREQ[2] 
100011 IDREQ[3] 
100100 IDREQ[4] 
100101 IDREQ[5] 
100110 IDREQ[6] 
100111 IDREQ[7] 
101000 IDREQ[8] 
101001 IDREQ[9] 
101010 IDREQ[10] 
101011 IDREQ[11] 
101100 IDREQ[12] 
101101 IDREQ[13] 
101110 IDREQ[14] 
101111 IDREQ[15]  
110000 IDREQ[16] 
110001 IDREQ[17] 
110010 IDREQ[18] 
110011 IDREQ[19] 
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bit28:23 Function 
110100 IDREQ[20] 
110101 IDREQ[21] 
110110 IDREQ[22] 
110111 IDREQ[23] 
111000 IDREQ[24] 
111001 IDREQ[25] 
111010 IDREQ[26] 
111011 IDREQ[27] 
111100 IDREQ[28] 
111101 IDREQ[29] 
111110 IDREQ[30] 
111111 IDREQ[31] 
Setting other 
than above  Setting prohibited
 
 
[bit22:20] :  Reserved 
 
[bit19:16] BC : Block Count  
These bits specify the number of blocks for Block/Burst transfer.  
When the transfer mode is set to Demand transfer, set BC to " 0000". 
Set the value " BC = Number of blocks  - 1". The maximum allowed number of blocks is 16.  
The value of these bits can be read during a transfer. Normally, as one transfer source access or one transfer 
destination access is completed successfully, BC is decreased by 1.  
In the case of RC=1 , the value set when the transfer started is reloaded upon the completion of the transfer.  
In the case of RC=0 , the value is set to "0"  upon successful completion of the transfer, while the value 
remains the same value as set during the transfer suspension  upon unsuccessful completion of the transfer. 
bit19:16 Function 
xxxx Number of transfer blocks (Initial value : 4’b0000) 
 
[bit15:0] TC : Transfer Count  
These bits specify the number of transfers for Block/Burst/Demand transfer.  
Set the value " TC = Number of transfers - 1" . The maximum allowed number of transfers is 65536 . 
The value of these bits can be read during a transfer. Normally, as the transfer of one block is completed, 
TC is decreased by1.  
In the case of RC=1 , the value set when the transfer star ted is reloaded upon the completion of the transfer.  
In the case of RC=0 , the value is set to "0"  upon successful completion of the transfer, while the value 
remains the same value as set during the transfer suspension upon unsuccessful completion of the t r a n s fe r. 
bit15:0 Function 
16’hxxxx Number of transfers (Initial value : 16’h0000) 
 
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