Fujitsu Series 3 Manual

							 
 
 
 
Page Section Change Results 
377 CHAPTER 13-2 
Watch Counter  2. Configuration of the Watch Counter 

  Corrected the error in description. (Watch counter control register 
(WCRD)   (WCCR)) 
407 3.2.  I/O mode 
   Corrected  of   I/O mode 8 (Shared channel signal 
trigger and timer start/stop mode. 
(  The odd channel stops...    Base timer stops...) 
409 to 412  CHAPTER 14-1 
Base Timer I/O Select 
Function 
4.1., 4.2. I/O Select Register (BTSEL0123, BTSEL4567) 
   Corrected the bit number of the register. 
534  4.3.1 FRT Control Register A (TCSA) 
   Added the following to the description of item 2 in [bit6]. 
Do not write TCSA.SCLR=0 until it can be checked that the 
counter value is cleared. 
576  4.3.18. ADCMP Control Register A (ACSA) 
   Added the following to the description of [bit5:4]. 
If the buffer function of ACCP and ACCPDN registers is to be 
used, use FRT-ch.0 for FRT to be connected. 
580  4.3.19. ADCMP Control Register B (ACSB) 
   Added the following to the description of [bit2]. 
If the buffer function of ACCP and ACCPDN registers is to be 
used, use FRT-ch.0 for FRT to be connected. 
584  4.3.20. ADCMP Compare Value Store Register (ACCP) 
   Added . 
586  4.3.21. ADCMP Compare Value Store Register, Down-count 
Direction Only (ACCPDN) 
   Added . 
590, 591  CHAPTER 15 
Multifunction Timer 
4.4. Details of OCU Output Waveform 
  Corrected the whole description in   List of OCU Operation 
Modes. 
Whole 
chapter  CHAPTER 16-1 
PPG Configuration 
Corrected the chapter name. (PPG 
 PPG Configuration) 
Deleted the description of MB9BF500. 
636 CHAPTER 16-2  PPG  5.2. PPG Start Trigger Control Register 1 (TTCR1) 

  Corrected the summaries. 
(PPG01/PPG03/PPG05/PPG07   PPG8/PPG10/PPG12/PPG14) 
 
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Page Section Change Results 
658 3. Operations 
     RC_Mode1 (QCR:RCM[1:0]=01): 
Added . 
659      RC_Mode3 (QCR:RCM[1:0]=11): 
Added . 
661      Operation example of QPRC Maximum Position Register 
(QMPR) interrupt 
The following ... RC_Mode2 (QCR:RCM[1:0]).    
The following ... RC_Mode2 (QCR:RCM[1:0]=10). 
662      Position counter reset mask function 
  Deleted the description of the ZIN function is set to the counter 
clear function (QCR:CGSC=0) and when. 
664      Position counter reset mask function 
Added . 
667  4.1. Quad Position & Revolution Counter Position Count Register 
(QPCR) 
   Corrected . 
668  4.2. QPRC Revolution Count Register (QRCR) 
   Added . 
672, 673  4.5. QPRC Control Register (QCR) 
     Low-Order Bytes of QPRC Control Register (QCRL) 
  Added (RC_Mode0 to 3) to the description of [bit3:2]. 
  Added (PC_Mode0 to 3) to the description of [bit1:0]. 
  Added  . 
675 
    High-Order Bytes of QPRC Control Register (QCRH) 
  C orrected the description of [bit9:8]. 
  Corrected . 
676, 677  4.6. QPRC Extension Control Register (QECR) 
   Corrected the descri ption of [bit1]. 
   Deleted  of [bit1]. 
   Corrected the descri ption of [bit0].   
(2K   8K, 0x8000   0x7FFFF) 
680, 681  4.7. Low-Order Bytes of QPRC Interrupt Control Register (QICRL)
   Corrected  of [bit3] and [bit1]. 
683, 684  CHAPTER 17 
Quad Position & 
Revolution Counter 
4.8. High-Order Bytes of QPRC Interrupt Control Register (QICRH)
  Corrected  of [bit13]. 
   Added  to [bit10] and [bit9]. 
Whole 
chapter  Added the description of 12 bit A/D converter. 
690 CHAPTER 18-1 
A/D Converter 
3. Notes 
  Corrected the description of   Notes on 10-bit A/D converter. 
 
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Page Section Change Results 
696 3.1.1. Scan conversion operation 
   Corrected the title of Figure 3-1, Figure 3-2. (SCIS0=0x04   
0x08) 
706  3.2.4. Interrupts in priority conversion 
   Corrected . (PFS[3:0]   PFS[1:0]) 
710  3.4. Starting DMA 
   Corrected the whole description and the figure. 
713  4.2. Priority conversion setup procedure example 
   Corrected Figure 4-2. (SFCLR   PFCLR) 
714  CHAPTER 18-2 
10-bit A/D  Converter 
4.3. Setting the conversion time 
  Corrected the description of   Example of setting the sampling 
time. ((ADSS2 to 0)   (ADSS3 to 0)) 
Whole 
chapter  CHAPTER 18-3 
12-bit A/D  Converter  Added a new section. 
Whole 
chapter CHAPTER 18-4 
A/D Timer Trigger 
Selection  Added the description of 12 bit A/D converter. 
796 CHAPTER 19-1 
Multi-function Serial 
Interface  1. Overview of the Multi
-function Serial Interface 
   Added LIN(LIN bus interface) to   Interface Mode and 
Table 1-1. 
   Added   LIN Sync field Detection: LSYN. 
798  1. Overview of UART (Async Serial Interface) 
   128 bytes   128 × 9 bits 
817, 818  4.1. Baud rate settings 
   Corrected the computation expression in   Allowable baud rate 
range for data reception. 
   Corrected the value of Minimum allowable baud rate error in 
the table. 
830  7.2. Serial Mode Register (SMR) 
   Corrected the summaries. 
844  7.7. FIFO Control Register 1 (FCR1) 
   Added  to [bit11]. 
849  7.8. FIFO Control Register 0 (FCR0) 
   Corrected the description of [bit1] and [bit0]. 
851  CHAPTER 19-2 
UART 
7.9. FIFO Byte Register (FBYTE) 
  Added . 
854  1. Outline of CSIO (Clock Sync Serial Interface) 
   128 bytes   128 × 9 bits 
903  5.7. FIFO Control Register 1 (FCR1) 
   Added  to [bit11]. 
907, 908  5.8. FIFO Control Register 0 (FCR0) 
   Corrected the description of [bit1] and [bit0]. 
910  CHAPTER 19-3 
CSIO 
5.9. FIFO Byte Register (FBYTE) 
  Added . 
 
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Page Section Change Results 
912 1. Overview of LIN Interface (Ver. 2.1) (LIN Communication 
Control Interface Ver. 2.1) 
   128 bytes   128 × 9 bits 
923, 924  3.1. Baud rate settings 
   Corrected Figure  3-1. (11xFL  10xFL) 
   Corrected the computation expression in   Allowable baud rate 
range for data reception. 
   Corrected the value in the table. 
941, 942  6.1. Serial Control Register (SCR) 
   Added  of [bit15]. 
   Corrected the descri ption of [bit12].   
(SSR:LER, FRE, ORE   SSR:FRE, ORE) 
945, 946  6.2. Serial Mode Register (SMR) 
   Corrected the summaries. 
   Corrected the description of [bit2]. (Unused bit   Reserved bit) 
958  6.7. FIFO Control Register 1 (FCR1) 
   Added  to [bit11]. 
963  6.8. FIFO Control Register 0 (FCR0) 
   Corrected the description of [bit1] and [bit0]. 
965  CHAPTER 19-4 
LIN Interface 
6.9. FIFO Byte Register (FBYTE) 
  Added . 
968  1. Overview of I2C Interface (I2C Communications Control 
Interface) 
   128 bytes   128 × 9 bits 
1028 5.1.  I2C Bus Control Register (IBCR) 
   Added . 
1040  5.5. Receive Data Register/Transmit Data Register (RDR/TDR) 
   Corrected the description of   Receive Data Register (RDR). 
1046  5.9. FIFO Control Register 1 (FCR1) 
   Added  to [bit11]. 
1051, 1052  5.10. FIFO Control Register 0 (FCR0) 
   Corrected the description of [bit1] and [bit0]. 
1054  CHAPTER 19-5 
I
2C Interface 
5.11. FIFO Byte Register (FBYTE) 
  Corrected . 
1057  2. Configuration and Block Diagram 
   Corrected Figure 2-1. 
1064  CHAPTER 20-1 
USB Clock Generation 
5.3. 5.3. USB-PLL Control Register-2 (UPCR2) 
  Corrected the description of [bit2:0]. 
1137 CHAPTER 20-3 
USB Host  1. Overview of USB host 

  Corrected Table 1-1. (Added missed lines in the table) 
1190 CHAPTER 21-1 
CAN Prescaler  2.1. CAN Prescaler Register (CANPRE) 

  Corrected the initial value of   Register configuration.   
(bit3, 1, 0 : 0   1) 
 
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MAJOR CHANGES IN THIS EDITION 
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Page Section  Change Results 
1319 FLASH_IF 
  Corrected the initial value of FSTR(0x008). 
(-------- -------- -------- -----00X   -------- -------- -------- ------0X) 
   Added CRTRMM(0x100). 
1320 Clock/Reset 
  Corrected the initial value of RST_STR(0x00C). 
(-------0 00000-01   -------0 0000--01) 
1321 SW  WDT 
   Corrected the initial value of WdogLock(0xC00). 
(00000000 00000000 00000000 00000001    
00000000 00000000 00000000 00000000) 
1325 PPG 
  Corrected Base_Ad dress + Address. 
(0x038 - 0x03F   0x038 - 0x0FF,   
0x108 - 0x13F   0x108 - 0x1FF) 
1327 Corrected  the whole  description of Base Timer I/O Select Function.
1328 QPRC 
  Corrected the initial value of QICRH(0x0014). 
(--111111   --000000) 
1329 10bit  A/DC 
   Added 10bit to the register name. 
1330 12bit  A/DC 
   Added a new section. 
CR Trim 
   Corrected configuration and initial value of MCR_FTRM(0x004).
(01111111   ------01 10000000) 
1331 EXTI 
  Corrected the initial value of EIRR(0x0004).   
00000000 00000000   XXXXXXXX XXXXXXXX) 
1332, 1333  INT-Req. READ 
   IRQMON0  EXC02MON 
   IRQMON1 to 48   IRQ00MON to IRQ47MON 
1334, 1335  GPIO 
   Added PFR8(0x020), DDR8(0x220), PDIR8(0x320), 
PDOR8(0x420) and SPSR(0x580). 
1336 LVD 
  Added LVD_STR2(0x010). 
1337 CAN_Prescaler 
  Corrected Base_Address + Address. (0x04E   0x000) 
   Corrected the initial value of CANPRE(0x000).   
(----0000   ----1011) 
1340  APPENDIXES 
1. Register Map 
USB ch0 
  Corrected configur ation, access unit and initial value of 
UDCC(0x2120). (B   B,H,W    10100-00   -------- 10100-00) 
In the previous revision, the number at the upper-right of the page is CM91-10101-2. 
 
MN706-00002-1v0-E 
\05033\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
 FUJITSU SEMICONDUCTOR LIMITED 
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1. Bus Architecture 
 
CHAPTER: System Overview 
This chapter explains this series system overview.   
 1.
 Bus Architecture 
2. Memory Architecture 
3. Cortex-M3 Architecture 
4. Mode 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFSYSTEM-E01.3 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  1: System  Overview 
MN706-00002-1v0-E 
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MB9Axxx/MB9Bxxx  Series  
						

							 
1. Bus Architecture 
 
1. Bus Architecture 
This chapter explains this series bus architecture. 
For this series bus, AHB Bus Matrix circuit actualizes a multi-layer bus. Master and slave architectures are 
shown below:   
  Master 
  Cortex-M3 CPU(I-code Bus, D- code Bus, System Bus) 
   DMAC 
 
  Slave 
  Internal Flash Memory 
   Internal SRAM(Code SRAM, On-chip SRAM) 
   External Bus 
   USB ch0/1 
   AHB-AHB Bus Bridge 
   AHB-APB Bus Bridge (APB0, 1, 2) 
 
See  Figure 1-1  for the bus block diagram. 
 Features 
  RAM Architecture 
For this series SRAM layout, bus is divided into co de area and on-chip area. This allows for preventing 
conflicts to RAM by multiple bus masters such as CPU and DMAC and allows for improving the 
performance. 
Also, because the divided RAM address areas are serial, RAM area can be utilized to the maximum extent. 
  APB Extension Bus 
APB1 and APB2 Peripheral Buses are APB extension bus  that the following functions are originally added 
based on AMBA3.0. (APB0 is not included.) 
   Supporting Halfword (16 bits) and Byte(8 bits) Accesses 
For supported registers, halfword  access and byte access are enabled. 
See Register Map for the supported registers. 
   Adding Read-Modify-Write (RMW) Signal 
HMASTLOCK signal in bit-band operations is used to generate. 
RMW signal is a signal added to prevent that  an unrelated flag is cleared mistakenly in 
read-modify-write process of bit-band operations. 
The corresponding flag reads 1 in read during the read-modify-write process and is designed to ignore 
1 write. 
This prevents any unrelated flag from being mistaken ly cleared in the next write when the flag is set 
immediately after the read in the sequ ence from read to modify to write. 
For the corresponding flags and registers, it is described that regardless of bit values, 1 can be read in 
Read-Modify-Write. 
 
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1. Bus Architecture 
 
   Bit-band operation must not be performed to a register which RMW is prohibited. 
   When Rea

d-Modify-Write process is performed over the software without bit-band operation, RMW 
signal is not output. 
Therefore, in this case, the flag value can be read  in read operation although a register supports RMW 
process, and it is necessary not to be cleared an unrelated flag mistakenly in write operation. 
   For the details of bit-band operations, see the Cortex-M3 Technical Reference Manual. 
 
 Priority Level 
This series sets the bus right as DMAC>CPU.   
According to DMAC access settings such as a case wh ere DMAC is always accessed by a burst transfer, 
access to CPU may be controlled. Please pay extra attention to DMAC transfer settings. 
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CHAPTER  1: System  Overview 
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MB9Axxx/MB9Bxxx  Series  
						

							 
1. Bus Architecture 
 
1.1.  Bus Block Diagram 
Figure 1-1 illustrates this series bus block diagram.   
Figure 1-1 Bus Block Diagram 
Cortex-M3TM
Core FLASHIF FLASH 
ROM table 
ETM 
TPIU 
SWJ-DP Code SRAM
DMAC 
On chip SRAM
I-code bus
System bus
AHB to AHB
bridge 
USB ch0
CAN 
DMAC bus
AHB to APBbridge APB1 
Peripherals
EXT-Bus I/F 
 
AHB to 
APB bridge APB0 
Peripherals 
AHB to APB bridge 
D-code bus
AHB bus matrix 
APB0 
APB2 
APB1 
USB ch1
APB2 
Peripherals
 
 
There are  som

e areas which no DMAC transfer can  be perfor
 med. For details, see the DMAC Transfer 
column in  Ta b l e  2 - 1. 
 
 
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CHAPTER  1: System  Overview 
MN706-00002-1v0-E 
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MB9Axxx/MB9Bxxx  Series