Fujitsu Series 3 Manual

							 
6. LIN Interface (ver. 2.1) Registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: LIN Interface (Ver. 2.1) (LIN Co mmunication Control Interface Ver. 2.1) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  56 
FBYTE2, FBYTE1: FIFO2 data count display bit, FIFO1 data count display bit 
During writing Sets the transfer data count. 
During reading Reads the effective count of data. 
 
Read (Effective data count) 
During transmission: The number of data sets  already written in FIFO but not transmitted yet 
During reception: The number of  data sets received in FIFO 
Write (Transfer data count)  During transmission: Set 0x00. 
During reception: Set the data count  to generate a receive interrupt. 
 
   Set 8h00 in the FBYTE register of transmit FIFO. 
   Set data equal to or greater than 1  in the FBYTE register of receive FIFO. 
   This state can be changed only after the data transmission or reception has been disabled. 
   A read-modify-write instruction cannot be used for this register. 
   Any setting exceeding the FIFO  capacity is inhibited. 
   When all the following requirements  are met, the receive data full flag bit (SSR:RDRF) is not set to 1 
even though the effective data of  FBYTE setting number exist in the r eceive FIFO. If the FBYTE register 
is set to 2 or greater, this operation will not occur. 
  FBYTE is set to 1. 
   The effective data count is 1, same as  the number specified in FBYTE register. 
   When the multi function serial interface macro r eceives the data, and writes received data in the 
reception FIFO, the data of the receptio n FIFO are read at the same time.   
However, after that, the receive data full flag bit (S SR:RDRF) will be set to 1 at any of the following 
conditions. 
  The next data is received. 
   The receive idele state of 8 bits  or longer is detected when the receive FIFO idele is enabled 
(FCR:FRIIE=1) 
 
 
CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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 FUJITSU SEMICONDUCTOR LIMITED 
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MB9Axxx/MB9Bxxx  Series  
						

							 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: I2C Interface (I2C Communications 
Control Interface) 
This chapter describes the I2C function supported in operation mode 4 of the multifunctional 
serial interface. 
 
1.
 Overview of I2C Interface (I2C Communications Control Interface) 
2. I2C Interface interrupt 
3. Dedicated Baud Rate Generator 
4. I2C communication operation flowchart examples 
5. I2C Interface Registers  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FM15I-E05.2 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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1.  Overview of I2C Interface (I2C Communications Control 
Interface) 
The I2C interface (I2C communications control interface) supports the I2C bus and operates as 
a master/slave device on the I2C bus. It also has transmit/receive FIFO (up to 128 × 9 bits 
each) *1installed. 
  Functions of I2C interface (I2C communications control interface) 
 
   Function 
1 Data buffer 
  Full duplex double buffer (when FIFO is not used) 
   Transmit/receive FIFO (max  128 × 9 bits each) *1 (when FIFO is 
used) 
2 Serial  input Removes noise up to 2 clocks in the bus clock for serial clock/serial 
data input. 
3 Transfer mode 
Synchronous 
4 Baud rate 
  Complete with a dedicated baud rate generator (constructed with a 
15-bit reload counter) 
   The external clock can be adjust ed with the reload counter. 
5 Data length 8 bits 
6  Signaling system  NRZ (Non Return to Zero) 
7 Interrupt request  
  Receive interrupt 
   Transmit interrupt 
   Request of status interrupt/interrupt to ICU 
   Transmit FIFO interrupt (when transmit FIFO is empty) 
   For both transmission and reception, the extended intelligent I/O 
service (EIIOS) and the DMA su pport function are available. 
8 I2C 
  Master/slave transmission and reception functions 
   Arbitration function 
   Clock synchronization function 
   Transmission direction detection function 
   Function to generate and detect iteration start condition 
   Bus error detection function 
   General call addressing function 
   7-bit addressing as master/slave 
   Generation of interrupt enabled during transmission or a bus error 
   The 10-bit addressing function can be programmatically enabled. 
9 FIFO  
  Transmit/receive FIFO installed (maximum capacity: 128 × 9 bits 
for transmit FIFO, 128 × 9 bits for receive FIFO) 
*1  
   Transmit FIFO or receive FIFO can be selected. 
   Transmit data can be resent. 
   Receive FIFO interrupt timing  can be changed via software. 
   FIFO resetting is supported independently. 
*1 : The FIFO capacity size varies from model type to model type. 
 
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2. I2C Interface interrupt 
I2C interface interrupt request is generated due to the following factors. 
- After transmission/reception of the first byte and after data transmission/reception is  completed 
- Stop condition 
-  Iteration start condition 
-  FIFO transmit dat

a request 
-  FIFO receive data completed 
  I2C Interface Interrupt 
Ta b l e  2 - 1  shows the interrupt control bits and interrupt causes for the I2C interface. 
Table 2-1 Interrupt control bits and interrupt causes for the I2C interface 
Interrupt  
type  Interrupt 
request flag bit  Flag 
register  Interrupt cause  Interrupt cause 
enable bit  Operation to clear interrupt request flag
The first byte has been 
transmitted/received*1 
(except for master operation when 
SSR:DMA=1) 
Data has been transmitted/received*1
(When SSR:DMA=0) 
Detection of a bus error 
Detection of arbitration lost 
Detection of reserved address 
Reception of NACK  Setting the interrupt flag bit (IBCR:INT) to 
0  
INT IBCR 
Receive FIFO being full during 
reception as a slave 
(When SSR:DMA=0)  IBCR:INTE 
Setting IBCR:INT to 0 after reading 
received data until receive FIFO is emptied 
SPC  Stop condition  Setting SPC to 0 
Status 
RSC IBSR 
Detection of iteration start  IBCR:CNDE 
Setting RSC to 0 
Reception of reserved address 
Completion of data reception  Reading from the received data register 
(RDR) 
Reception of a data volume 
matching the value set for FBYTE. RDRF SSR 
Detection of reception idling when 
FRIIE=1  Reading from the Received Data Register 
(RDR) until receive FIFO is emptied 
Reception 
ORE SSR Overrun error  SMR:RIE 
Setting the reception error flag bit 
(SSR:REC) to 1 
The Transmit Data Register is 
empty. 
TDRE SSR  Setting the transmit buffer empty 
flag set bit (SSR:TSET) to 1  SMR:TIE Writing to the Transmit Data Register 
(TDR) or setting the transmit FIFO 
operation enable bit to 
1 when the transmit 
FIFO operation enable bit is set to 0 and 
valid data are present in transmit FIFO 
(re-transmitting data) 
*2 
FDRQ  FCR1 Transmit FIFO is empty.  FCR1:FTIE The FIFO transmit data request bit is set to 
0 or transmit FIFO is full. 
No transmission operation 
Transmission 
TBI 
(SSR: 
DMA=1)  SSR 
Setting the transmit buffer empty 
flag set bit (SSR:TSET) to 1  SCR:TBIE Writing to the Transmit Data Register 
(TDR) or setting the transmit FIFO 
operation enable bit to 
1 when the transmit 
FIFO operation enable bit is set to 0 and 
valid data are present in transmit FIFO 
(re-transmitting data) 
*3 
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*1 : If normal data can be transmitted/received and SSR:TDRE is 0, no interrupt is generated. This to support DMA transfers. 
To generate an IBCR:INT flag at a time of data tran smission/reception, the SSR:TDRE bit needs to be set to 
1 before the IBCR:INT flag is set. 
*2 : Be sure to check that the SSR:TDRE bit is set to 0 and then set the SMR:TIE bit to 1.   
*3 : Be sure to check that the SSR:TBI bit is set to 0 and then set the SSR:TBIE bit to 1.     
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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2.1. I2C interface operation 
The I2C interface performs communications using two two-way bus lines, a serial data line 
(SDA) and a serial clock line (SCL). 
 I2C bus start condition 
The following shows the I2C bus start condition. 
Figure 2-1 Start condition 
   SD A   
   SCL 
                             Start condition 
 
 
  I2C bus stop condition 
The following shows the I2C bus stop condition. 
Figure 2-2 Stop condition 
   SD A   
   SCL 
                 
                                              Stop condition 
 
 
 I2C bus iteration start condition 
The following shows the I2C bus iteration start condition. 
Figure 2-3 Iteration start condition 
   SD A   
   SCL 
                   ACK  
                                         Iteration start condition        ACK: Acknowledge
  
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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2.2. Master mode 
Master mode generates the start condition on the I2C bus and outputs clocks to the I2C bus. 
When the MSS bit in the IBCR register is set to 1 while the I2C bus is in idle state 
(SCL=HIGH, SDA=HIGH), master mode is activat ed, causing the ACT bit in the IBCR register 
to be set to 1. 
 Generating start condition 
The start condition is generated under the following condition. 
   When SDA=H, SCL=H, ISMK :EN=1 and IBSR:BB=0, the IBCR:MSS bit is set to 1. 
 
Outputting the start condition to the I
2C bus causes the IBCR:ACT bit to be set to 1. After that, when the 
start condition is received, the IBSR:BB b it is set to 1 to indicate that the I2C bus is carrying out 
communications. (See Figure 2-4 .) 
Figure 2-4 Start condition output and relationships with respective bits 
                    Start condition 
    SDA                                                                  A6             A5 
    SCL                                                                  
 1               2 
    BB bit 
  
    MSS bit 
                                    Set to 1. 
    ACT bit 
    TRX bit 
    FBT bit 
 
    TDRE bit 
                                                                                        A6: Address bit 6
                                                                                        A5: Address bit 5
 
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 In operation mode 4 (I
2C mode), the bus clock is used at a frequency no lower than 8 MHz. Also note that 
setting of a baud rate generator that exceeds 400 kbps is prohibited.   
 
 Slave address output 
Outputting the start condition causes data that are set  in the TDR register to be output as the address, 
starting with bit 7. When FIFO is enabled, the datum in  the TDR register that is written the earliest is output. 
Bit 0 is used as the data direction bit (R/W). When the  data direction bit (R/W) is 0, it indicates that data 
flow in the write direction (from the master to a slav e). Set the address to the TDR register before setting 
the IBCR:MSS to 1 or IBCR:SCC to 1. 
For the output timing of the address and the data output direction, see  Figure 2-5, Figure 2-6 . 
Figure 2-5 Address and data direction (when FIFO is disabled) 
                             1       2      3       4       5        6       7      8 
SCL 
 
SDA  A6( D7)  A5( D6)  A4(D5)   A3( D4)  A2(D3)   A1(D2)   A0(D1)  R/W( D0)  ACK   
BB bit 
 
MSS  b i t  ( * 1)  
 
TDRE bit  
 
INT bit 
 
 
RSA b i t  
 
RDRF bi t 
 
INT bit 
                  
A6 to A0:  Address  bits 
D7 to  D0: TDR regi ster  bi ts 
R/W: Data di recti on (writ ing if L) 
ACK: Acknowl edge (Acknowl edged if  L and out put  in Sl ave mode) 
*1  : An address must  be set  in  the TDR  regist er  before  set ti ng  the MSS bit  t o 1. 
SCL i s kept L when I NT bi t i s 1.
 
 
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Figure 2-6 Address and data direction (when transmit/receive FIFO is enabled) 
                             1        2      3       4       5       6       7       8 
SCL  
SDA  A6( D7)  A5( D6)  A4(D5)   A3( D4)  A2(D3)   A1(D2)   A0(D1)  R/W( D0)  ACK 
 
BB bit 
 
MSS bit  ( *1)  
 
INT bit (*2) 
 
 
R SA b i t  
 
RDRF bi t 
 
INT bit 
 
A6 to A0: Address bits 
D 7 t o  D0 :  T D R r e gi s t e r  bi t s  
R/W: Data di recti on (writ ing i f L) 
ACK: Acknowl edge  (Acknowl edged  if  L and  out put  in Sl ave mode) 
*1 : An address must be set i n the TDR r egister bef ore sett ing t he MSS bit to “1”. 
*2 :  If  acknowledged wit h L and if  R/W=L, the Send FIFO buff er has dat a.  I f acknowledged wi th L and the Recei ve  FI FO buff er  has no data,  the I NT bit  i s not set  to  1. 
SCL is kept  L when INT bi t is 1.  
 
 
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