Fujitsu Series 3 Manual

							 
4. Registers of Multifunction Timer 
 
 Always follow the procedure below and perform control when starting PWM signal output by OCU. 
1. Initial setting 
Set FRT 

operation mode (FRT control register other than TCSA.STOP). 
Set OCU operation mode and initialize the output leve l (OCU control register other than OCSA.CST0 
and OCSA.CST1). 
Set the OCCP compare value (writing the OCCP value). 
2.  Start FRT count operation (writing 0 to TCSA.STOP). 
3.  Enable OCU’s operation (writing 1 to OCSB.CST0 and OCSB.CST1). 
 
Always follow the procedure below and perform control when finishing PWM signal output by OCU. 
1.  Disable OCU’s operation (writing 0 to OCSB.CST0 and OCSB.CST1). 
2.  Reset the output level of the OCU output pins (writing to OCSB.OTD0 and OCSB.OTD1, if necessary). 
3.  Stop FRT’s count operation (writing 1 to TCSA.STOP and TCSA.SCLR, writing 0x0000 to TCDT). 
 
[bit2] OCSA.BDIS0 
Process Value  Function 
0 Enables the buffer function of the OCCP(0) register. Write 
1 Disables the buffer function of the OCCP(0) register. 
Read - Reads the register setting. 
 
[bit3] OCSA.BDIS1 
Process Value  Function 
0 Enables the buffer function of the OCCP(1) register. Write 
1 Disables the buffer function of the OCCP(1) register. 
Read - Reads the register setting. 
 
OCSA.BDIS0 is a register that specifies whether to  enable or disable the buffer register function of 
OCCP(0). 
OCSA.BDIS1 is a register that specifies whether to  enable or disable the buffer register function of 
OCCP(1). 
Change the setting of these registers,  while OCU’s operation is disabled. 
See  4.3.9 OCU Compare Value Store Register (OCCP) . 
 
When  

using FRT in Up/Down-count mode, make sure to enable the buffer function of OCCP and use it as 
the transfer mod e

 at Zero value detection. 
 
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[bit4] OCSA.IOE0 
Process Value Function 
0 Does not generate interrupt, when 1 is set to OCSA.IOP0. Write 
1 Generates interrupt, when 1 is set to OCSA.IOP0. 
Read - Reads the register setting. 
 
[bit5] OCSA.IOE1 
Process Value  Function 
0 Does not generate interrupt, when 1 is set to OCSA.IOP1. Write 
1 Generates interrupt, when 1 is set to OCSA.IOP1. 
Read - Reads the register setting. 
 
OCSA.IOE0 is a register that specifies whether to notif y CPU of the event that 1 is set to OCSA.IOP0 as 
an interrupt (enabling interrupt) or  not to notify it (disabling interrupt). 
OCSA.IOE1 is a register that specifies whether to notif y CPU of the event that 1 is set to OCSA.IOP1 as 
an interrupt (enabling interrupt) or  not to notify it (disabling interrupt). 
See  5.2 Treatment of Event Detect Register and Interrupt . 
[bit6] OCSA.I OP0 
Process Value 
Function 
0 Clears this register to 0.  Write 
1 Does nothing. 
0 Indicates that no match has been de
tected between FRT’s count value and 
OCCP(0) value at OCU ch.(0). 
Read 
1 Indicates that a match has already been
 detected between FRT’s count value 
and OCCP(0) value at OCU ch.(0). 
Read at RMW access  1 is always read. 
 
[bit6] OCSA.IOP1 
Process Value  Function 
0 Clears this register to 0. Write 
1 Does nothing. 
0 Indicates that no match has been de
tected between FRT’s count value and 
OCCP(1) value at OCU ch.(1). 
Read 
1 Indicates that a match has already been
 detected between FRT’s count value 
and OCCP(1) value at OCU ch.(1). 
Read at RMW access  1 is always read. 
 
OCSA.IOP0 is a register that is  set to 1 when a match is detected between FRT’s count value and 
OCCP(0) value when the operatio n of OCU-ch.(0) is enabled. 
OCSA.IOP1 is a register that is  set to 1 when a match is detected between FRT’s count value and 
OCCP(1) value when the operatio n of OCU-ch.(1) is enabled. 
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4. Registers of Multifunction Timer 
 
By reading from this register, whether FRT’s count value has reached the OCCP value or not can be 
determined. 
This register can be cleared by writing 0. 
This register does nothing, if 1 is written. Always  write 1 to the register when rewriting to another 
register in the same address area. 
1 is always read from this register at RMW access. 
See  5.2 Treatment of Event Detect Register and Interrupt . 
 
When  

FRT is in Up/Down-count mode, these registers are not set, even if FRT’s count value has matched 
the OCCP v a

lue at its peak. 
 
 
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4. Registers of Multifunction Timer 
 
4.3.7. OCU Control Register B (OCSB) 
OCSB is an 8-bit register that controls OCU’s operation. 
Each mounted channel has three registers: OCSB10, OCSB32 and OCSB54. 
OCSB10 controls OCU ch1 and OCU ch0. 
OCSB32 controls OCU ch3 and OCU ch2. 
OCSB54 controls OCU ch5 and OCU ch4. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field Reserved BTS1 BTS0 CMODReservedReserved OTD1 OTD0 
Attribute  - R/W  R/W R/W -  - R/W  R/W 
Initial Value  - 1  1 0 -  - 0  0 
 Functions of Register 
[bit8] OCSB.OTD0 
Process Value  Function 
0 Sets the output level of the RT(0) pin to the Low level, when OCSA.CST0=0. 
Does nothing, when OCSA.CST0=1. 
Write 
1 Sets the output level of the RT(0) pin to the High level, when OCSA.CST0=0. 
Does nothing, when OCSA.CST0=1. 
0 
Indicates that the RT(0) output pin is in the Low-level output state. Read 
1 Indicates that the RT(0) output pin is  in the High-level output state. 
 
[bit9] OCSB.OTD1 
Process Value  Function 
0 Sets the output level of the RT(1) pin to the Low level, when OCSA.CST1=0. 
Does nothing, when OCSA.CST1=1. 
Write 
1 Sets the output level of the RT(1) pin to the High level, when OCSA.CST1=0. 
Does nothing, when OCSA.CST1=1. 
0 
Indicates that the RT(1) output pin is in the Low-level output state. Read 
1 Indicates that the RT(1) output pin is  in the High-level output state. 
 
OCSA.OTD0 is a register that reads the state of the RT(0) output pin of OCU-ch.(0) and sets its output 
level. 
OCSA.OTD1 is a register that reads the state of the RT(1) output pin of OCU-ch.(1) and sets its output 
level. 
The output level of the OCU output pins (RT0 to RT5) can be set by writing to these registers when OCU’s 
operation is disabled. When OCU’s operation is enabled,  the writing to these registers is ignored. The read 
value of these registers indicates the output level of the OCU output pins, irrespective of OCU’s operation 
state. 
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   After being processed by WFG, OCU’s output pins (RT0 to RT5) become LSI’s external output pins 
(RTO0 to

 RTO5). For this reason, the level of OCU’s output pins does not match the level of LSI’s 
external output pins in some of WFG’s operation modes; therefore care must be taken. The state of LSI’s 
external output pins can be read from the PDIR register of the I/O port block. 
   Follow the procedure below to set the output level to Low by stopping OCU’s operation when CST0=1 
(OCU operation enabled) and OTD0=1 (High-level output). 
   No value can be written to OTD0 while OCU’s operatio n is enabled; therefore, first write 0 to CST0 
to stop OCU’s operation. 
   Then, write 0 to OTD0 to set the output level to Low. 
It should be noted that if the above steps were reversed, the value written to OTD0 would be ignored. It 
should also be noted that if CST0=0 and OTD0=0 were written to the OCSA and OCSB registers by 
half-word access, the value written to OTD0 would be ignor ed because OCU’s operation is enabled. 
Similarly, care must be taken to writing to OTD1.   
 
[bit11:10] Reserved 
Process Function 
Write  0 must be written at write access. 
Read 0 is read. 
 
[bit12] OCSB.CMOD 
Process Value  Function 
0 Writes 0 to this register. Write 
1 Writes 1 to this register. 
Read - Reads the register setting. 
 
OCSB.CMOD is a register that se lects OCU’s operation mode in combination with OCSC.MOD0 to 
MOD5. 
Change the setting of this register, while OCU’s operation is disabled. 
For details of operation modes by this register setting, see  4.4 Details of OCU Output Waveform . 
Wh en setting
 

OCSB10.CMOD, the common setting applies to ch.1 and ch.0. 
When setting OCSB32.CMOD, the common setting applies to ch.3 and ch.2. 
When setting OCSB54.CMOD, the common setting applies to ch.5 and ch.4. 
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4. Registers of Multifunction Timer 
 
[bit13] OCSB.BTS0 
Process Value Function 
0 Performs buffer transfer of the OCCP(0) register upon Zero value detection 
by FRT. 
Write 
1 Performs buffer transfer of the OCCP(0) register upon Peak value detection 
by FRT. 
Read 
- Reads the register setting. 
 
[bit14] OCSB.BTS1 
Process Value  Function 
0 Performs buffer transfer of the OCCP(1) register upon Zero value detection 
by FRT.     
Write 
1 Performs buffer transfer of the OCCP(1) register upon Peak value detection 
by FRT. 
Read 
- Reads the register setting. 
 
OCSB.BTS0 is a register that speci fies the timing of transfer from the buffer register to the OCCP(0) 
register when the buffer function of the OCCP(0) register is enabled. 
OCSB.BTS1 is a register that speci fies the timing of transfer from the buffer register to the OCCP(1) 
register when the buffer function of the OCCP(1) register is enabled. 
Change the setting of these registers while OCU’s operation is disabled. 
The setting of these registers has no meaning, when  the buffer function is disabled (OCSA.BDIS1=1, 
OCSA.BDIS0=1). 
See  4.3.9 OCU Compare Value Store Register (OCCP) . 
 
When  

using FRT in Up/Down-count mode, make sure to enable OCCP’s buffer function and select the 
transfer m ode 

for Zero value detection. 
 
[bit15] Reserved 
Process Function 
Write  The written value is ignored. 
Read An undefined value is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.8. OCU Control Register C (OCSC) 
OCSC is an 8-bit register that controls OCU’s operation. 
This register controls all of OCU ch0 to ch.5. 
 Configuration of Register 
B i
t 
15  14 
13 12 
1
 1 
10  9 8 
Field  ReservedReserved  MOD5 MOD4  MOD3 MOD2 MOD1  MOD0 
Attribute - - R/W R/W  R/W R/W R/W  R/W 
Initial Value - - 0 0  0 0 0  0 
 
  Functions of Register 
[bit5:0] OCSC.MOD5, OCSC.M OD4, OCSC.MOD3, OCSC.MOD 2, OCSC.MOD1, OCSC.MOD0 
Process Value  Function 
0 Writes 0 to this register. Write 
1 Writes 1 to this register. 
Read - Reads the register setting. 
 
OCSC.MOD0 and OCSC.MOD1 determines the operation mode of OCU ch.0/ch.1 in combination with 
OCSB10.CMOD. 
OCSC.MOD2 and OCSC.MOD3 determines the operation mode of OCU ch.2/ch.3 in combination with 
OCSB32.CMOD. 
OCSC.MOD4 and OCSC.MOD5 determines the operation mode of OCU ch.4/ch.5 in combination with 
OCSB54.CMOD. 
Change the setting of this register while OCU’s operation is disabled. 
For the operation modes by this register setting, see  4.4 Details of OCU Output Waveform . 
[bit7:6] Rese rved 
Process Function 
Write 
The written value is ignored. 
Read An undefined value is read. 
 
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4. Registers of Multifunction Timer 
 
4.3.9. OCU Compare Value Store Register (OCCP) 
OCCP is a 16-bit register that specifies the timing of changing OCU’s output signal as the 
compare value of FRT’s count value. 
Each mounted channel has six registers: OCCP0 to OCCP5. 
OCCP0 stores the compare value of OCU ch.0 (2-change mode, ch.1 compare value). 
OCCP1 stores the compare value of OCU ch.1. 
OCCP2 stores the compare value of OCU ch.2 (2-change mode, ch.3 compare value). 
OCCP3 stores the compare value of OCU ch.3. 
OCCP4 stores the compare value of OCU ch.4 (2-change mode, ch.5 compare value). 
OCCP5 stores the compare value of OCU ch.5. 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field OCCP[15:0] 
Attribute R/W 
Initial  Va l u e   0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Functions of Register 
[bit15:0] OCCP.OCCP[15:0] 
Process Function 
Write  Specifies the timing of changing OCU’s output signal. Stores the written value to the 
buffer register. 
Read 
Reads the value in the OCCP register ( not the value in the OCCP buffer register). 
 
OCCP is a 16-bit register that speci fies the timing of changing OCU’s output signal as the compare value of 
FRT’s count value. 
When data is written to this address area, the data is fi rst stored in the buffer register. And then, the data is 
transferred from the buffer register to the OCCP register under the following conditions. 
When the buffer function is disabled: 
Data is transferred immediately after  it is written to the buffer register. 
When the buffer function is enabled and the tran sfer upon Zero value detection is enabled: 
Data is transferred, when FRT’s counter is stopped or when FRT’s count value has reached 0x0000. 
When the buffer function is enabled and the tran sfer upon Peak value detection is enabled: 
Data is transferred, when FRT’s counter is stopped or when FRT’s count value has matched the TCCP 
value. 
The enabling/disabling of the buffer function and the timin g of data transfer are determined by the value of 
the corresponding register OCSA.BDIS1/BDSI0 or OCSB.BTS1/BTS0. 
When OCU’s operation is enabled, the pulse width of OCU’s output signal can be changed by rewriting to 
this register. When the buffer function is disabled,  the written value can be immediately reflected on the 
OCCP register. When the buffer functio n is enabled, the settings in the OCCP register for multiple channels 
can be synchronized. 
If data is read from this address area, the value in th e OCCP register is read, rather than the value in the 
buffer register. Therefore, it shoul d be noted that no bit can be rewritten by RMW access to this address 
area when the buffer function is enabled. 
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If 0x0000 or 0xFFFF is written to this register when FRT is in Up/Down-count mode, a fixed value can 
be output. For details, see  4.4 Details of OCU Output Waveform . 
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4.3.10.  WFG Control Register A (WFSA) 
WFSA is a 16-bit register that controls WFG’s operation. 
Each mounted channel has three registers: WFSA10, WFSA32 and WFSA54. 
WFSA10 controls WFG ch.10 (the output processing block of OCU ch.1 and OCU ch.0). 
WFSA32 controls WFG ch.32 (the output processing block of OCU ch.3 and OCU ch.2). 
WFSA54 controls WFG ch.54 (the output processing block of OCU ch.5 and OCU ch.4). 
It should be noted that this register does not allow for byte access. 
 Configuration of Register 
 
Bit 15 14 13 12 11 10 9 8 
Field Reserved Reserved ReservedDMODPGEN[1:0] PSEL[1:0] 
Attribute  - - -  R/W R/W  R/W 
Initial Value - - 0  0 0 0  0 0 
           
Bit  7 6 5  4 3 2 1 0 
Field GTEN[1:0]  TMD[2:0] DCK[2:0] 
Attribute R/W  R/W R/W 
Initial Value 0 0 0  0 0 0 0 0 
 Functions of Register 
[bit2:0] WFSA.DCK[2:0] 
Process Value  Function 
000 Sets the count clock cycle of the  WFG timer to the same value as PCLK. 
001 Sets the count clock cycle of the WFG timer to PCLK multiplied by 2. 
010 Sets the count clock cycle of the WFG timer to PCLK multiplied by 4. 
011 Sets the count clock cycle of the WFG timer to PCLK multiplied by 8. 
100  Sets the count clock cycle of the WFG timer to PCLK multiplied by 16. 
101 Sets the count clock cycle of the WFG timer to PCLK multiplied by 32. 
110 Sets the count clock cycle of the WFG timer to PCLK multiplied by 64 
Write 
Other than 
above  Setting prohibited 
Read 
- Reads the register setting. 
 
WFSA.DCK[2:0] is a register that sets  the count clock cycle of the WFG timer. 
Change the setting of this register, while the WFG timer is stopping. 
The count clock of the WFG timer is generated by dividing the PCLK in LSI by the pre-scaler. This register 
sets the division ratio of the pre-scaler. 
The count clock cycle of the WFG timer is determined  according to PCLK cycle and the clock division 
ratio set by this register. 
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