Fujitsu Series 3 Manual
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3. Functions and Operations of DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 16 3.5. Channel Priority Control This section describes the channel priority control. Channel Priority Control If multiple channels have transfer requests, DMAC switches the channel subject to the transfer among them at the timing of the Transfer Gap of each channel. At this point, the next channel to which the tr ansfer will be performed is determined according to the priority control. The priority control can be selected from either fixed priority or rotated priority. Figure 3-6 shows an explanatory diagram. In this figure , the right axis indicates the time axis. The arrows indicate transfer timings of each channel to perform its transfer operation when all of the channels issue transfer requests simultaneously. Operation in Fixed Priority Mode ( PR=0) In fixed priority mode , the channel with the smallest channel number among all the channels with a transfer request has the priority to perform transfer operation. (Priority order: ch.0 > ch.1 > ch.2 > ch.3 > ch.4 > ch.5 > ch.6 > ch.7) First, the channel with the highest priority performs its transfer (ch.0 in the figure). As the channel with the highest priority halts the transfer operation at the timing of a Transfer Gap, then, the channel with the second highest priority performs its transfer operation (ch.1 in the figure). F or this reason, the channels with the highest and the second highest priority perform the transfer operations alternately. After that, when the channel with higher priority completes its transfer, the channel with lower priority starts its transfer operati on (ch.3 in the figure). Operation in Rotated Priority Mode (PR=1) In rotate priority mode, all channels perform their transfer operations equally. Figure 3-6 Explanatory Diagram of Channel Priority Control Ch.0Ch.1Ch.2Ch.3Ch.4Ch.5Ch.6Ch.7 Fixed Priority mode Rotated Priority mode Ch.0Ch.1Ch.2Ch.3Ch.4Ch.5Ch.6Ch.7 CHAPTER 8: DMAC MN706-00002-1v0-E 195 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 17 4. DMAC Control This chapter describes DMAC control methods in details. 4.1 Overview of DMAC Control 4.2 DMAC Operation and Control Procedure for Software Transfer 4.3 DMAC Operation and Control Procedure for Hard ware (EM=0) Transfer 4.4 DMAC Operation and Control Procedure for Hardware (EM=1 ) Transfer CHAPTER 8: DMAC MN706-00002-1v0-E 196 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 18 4.1. Overview of DMAC Control This section provides an overview of DMAC control. The control register of each channel of DMAC has EB (individual -channel operation enable bit) and PB (individual -channel pause bit). By manip ulating these bits, the start of DMA transfer operation (operation enabled), the forced termination of transfer operation (operation disabled) and the pause of transfer operation can be controlled by channel. The control register also has DE (all -channel o peration enable bit) and DH (all -channel pause bit), which allow the transfer operations of all channels to be controlled at once. Each channel is originally in the operation- prohibited state (Disable state) in which the transfer content (the address of th e transfer source, the address of the transfer destination, the transfer data width, the number of transfers, the transfer mode, etc.) are specified for each channel to its configuration register. Then, the transfer operations are controlled by writing to EB, PB, DE and DH to instruct the transfer operations to be started or paused. Once each channel completes its transfer, it sets the end code to SS (Stop Status) to give the notification of its stop state. An interrupt can be generated upon the completion of transfer. After the transfer ends, each channel clears EB and PB and returns to the operation -prohibited state (Disable state). The following sections describe the operations of and control procedures for DMA transfer by software request and hardware DMA transfer by transfer request from Peripherals. The following terms are used in the explanations as instructions from CPU, which refer to writing the following values to the EB, PB, DE and DH bits. ⋅ Instruction to enable individual -channel operation (write EB=1, PB=0 ) ⋅ Instruction to disable individual- channel operation (write EB=0) ⋅ Instruction to pause individual -channel operation (write EB=1, PB=1 ) ⋅ Instruction to enable all -channel operation (write DE=1, DH=0000 ) ⋅ Instruction to disable all -channel operatio n (write DE=0) ⋅ Instruction to pause all -channel operation (write DE=1, DH!=0000) CHAPTER 8: DMAC MN706-00002-1v0-E 197 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 19
4.2. DMAC Operation and Control Procedure for Software
Transfer
This section describes DMAC operation and control procedure for software transfer.
Figure 4-1 Transitional Diagram of Software Transfer State
Software DMA operationTransition by CPU
Transition by DMAC
2 4,5
3
Disable
DE
=0 or EB =0 or
DH !=0000 or PB=1
initial : SS=000
after stop :SS=code
Transfer
DE =1 EB=1
DH =0000 PB=0
SS=000
Pause
DE =1 EB=1
DH !=0000 or PB=1
SS=111
6
6
1 ,7,11
Reset
8
9
10
Figure 4-1 shows a transitional diagram of the states of the channel to be controlled for software transfer.
T he numbers next to the transitional lines in the figure correspond to the numbers which appear in the
following control procedures. The solid transitional lines indicate transitions of state instructed by CPU,
while the broken transitional lines indicate transitions of state due to DMAC operation.
CHAPTER 8: DMAC
MN706-00002-1v0-E
198
MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 20 Description of Each State Disable state In this state, the transfer of the channel to be controlled is prohibited. Channels in this state do nothing and wait for instruction from CPU. At the system reset, DE=0, EB=0, DH=0000 and PB=0 apply to this Disable state. Transfer state In this state, the transfer of the channel to be controlled is enabled. Channels in this state perform transfer operation as specified. Once all of the transfer operations are completed, the y return to the Disable state. The state is also changed as instructed by CPU. Pause state In this state, the channel to be controlled has its transfer operation on pause due to an instruction to pause, issued by CPU, and is waiting for another instruction from CPU. Explanation of Control Procedure 1. Disable state / Preparation for transfer Specify via CPU the transfer content for the channel to be controlled (writing to DMACSA, DMACDA, DMACA and DMACB ). For details of transfer content to be specified, see th e section describing register functions. When generating an interrupt from DMAC upon the completion of transfer, set EI and CI. The following restrictions apply to software transfer. Specify ST=1 and IS=000000 . Demand transfer mode cannot be specified to M S. Always set "0" to EM. Give an instruction to enable all- channel operation and set PR. Data can also be written to DMACA at the same time in Step 2. 2. Disable state => Transfer state / Start of transfer Give an instruction to enable individual -channel oper ation from CPU. When DE=1, EB=1, DH=0000 and PB=0 are set, the channel to be controlled moves to Transfer state. 3. Transfer state When the channel in Transfer state becomes enabled to access the system bus, it performs a transfer according to the transfer co ntent (it may take time to start the transfer, depending on the status of other channels). In the case of Block transfer, a Transfer Gap is generated every time TC is updated. In the case of Burst transfer, no Transfer Gap is generated. During the transfer operation, BC, TC, DMACSA and DMACDA indicate the remaining number of transfers and the transfer address at that time point. The transfer status can be checked by reading from CPU. The specified transfer content cannot be changed via CPU to the channel in Transfer state ( rewriting to DMACSA, DMACDA, DMACA[29:0], DMACB[31:1] ). (However, EB, PB and EM can be rewritten.) 4. Transfer state => Disable state / Successful completion of transfer When transfers are successfully completed for the number of times calculated by (BC+1) x (TC+1) , the channel in Transfer state clears EB, PB and ST and moves to Disable state. It sets SS=101 to provide the notification of the successful completion. See Example 1 in Figure 4-2. If successful transfer completion interrupt has been enabled, an interrupt occurs. If reload has been specified to BC, TC, DMACSA and DMACDA , such reload is executed according to the specified transfer content. CHAPTER 8: DMAC MN706-00002-1v0-E 199 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 21 Figure 4-2 Example of Operation of Software- Block Transfer DMA status Transfer Example of Block transfer mode (software DMA operation) start / normal end / error stop / force stop Transfer action Disable Example 1 :normal end Disable TC(no reload) 3210 SS 000101 ( normal end) Start request from CPUTransfer normal end BC Transfer Example 2 : error stop Disable 32 000011 (Source access error ) Transfer Example 3 : enforced stop from CPU Disable 32 000010 (Stop request ) DMA status Transfer action Disable TC(no reload) SS BC DMA status Transfer action Disable TC(no reload) SS BC Transition state Start request from CPUTransfer error stop Start request from CPU Stop request from CPU Transfer enforced stop 5. Transfer state => Disable state / Transfer error stop The channel in Transfer state suspends the transfer process, if an address overflow, transfer source access error or transfer destination access error occurs. It clears EB, PB and ST and moves to Disable state. It sets the value that indicates the error content to SS to give the notification of the error stop. See Example 2 in Figure 4-2. If unsuccessful transfer completion interrupt has been enabled by EI, an interrupt occurs. BC, TC, DMACSA and DMACDA to which reload has not been specified hold the values set at the time of the transfer suspension. Normally, a transfer error occurs, when an attempt is made to access an address area that does not exist in the system bus or an address area that prohibits access from DMAC. No such error occurs in general applications. CHAPTER 8: DMAC MN706-00002-1v0-E 200 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 22 6. Transfer state, Pause state => Disable state / Forced transfer stop If an instruction to disable i ndividual-channel operation or an instruction to disable all- channel operation is issued from CPU to a channel in Transfer state or Pause state, the transfer operation of that channel can be forced to stop (for the operation when an instruction to disable operation is issued to a channel in Disable state, see Step 11 in the software procedure). If an instruction is given from CPU, the relevant channel suspends its transfer process. It clears EB, PB and ST and moves to Disable state. It sets SS=010 and gives the notification that the transfer of that channel has been forced to stop. If unsuccessful transfer completion interrupt has been enabled by EI, an interrupt occurs. BC, TC, DMACSA and DMACDA to which reload has not been specified hold the values set at the time of the transfer suspension. After instructed from CPU, the transfer stops at the timing when the relevant channel is not performing transfer (in Transfer Gap before the transfer starts), as shown in the Example 3 in Figure 4-2. In the case of a channel in Pause state, the transfer stops immediately. There is a time difference (Transition state) between the instruction and the stop. It may take some time, depending on the BC setting. As a new transfer cannot be set or started during this period, always make sure that the operation has stopped before setting the next transfer. In the case of an instruction to disable all -channel operation, the timing to stop varies depending on the channel. As DS is set when all of the channels are stopped, it can confirm that all of the channels have stopped. Even if instructed from CPU, the transfer may not be forced to stop, and instead, it may be successfully completed due to factors such as transfer mode (Burst/Block/Demand) and transfer status (the number of transfers performed, the timing of instruction to disable the operation). Also, if a transfer error occurs before the transfer stops, error stop applies to the transfer. 7. Disable state / Post -transfer process SS is read from CPU to check the state of completion of the transfer. CPU clears SS to prepare for the next transfer. If interrupts have been enabled, the interrupt signal from DMAC is deasserted by clearing SS. In the case of successful completion, CPU resets the transfer content, as required. If each reload has been specified, the values set before the start of the transfer are reloaded to BC, TC, DMACSA and DMACDA . If each reload has not been specified, BC and TC are initialized to "0" . DMACSA and DMACDA show the address for the next transfer. In the cases of error stop and forced stop, BC, TC, DMACSA and DMACDA must always be reset, because they may have the values set at the time of the suspension. If the transfer is stopped due to an instruction to disable all -channel operation , DE is set to "0"; therefore, the next transfer will require an instruction to enable all -channel operation and an instruction to enable individual -channel operation. 8. Transfer state / Transfer pause If an instruction to put individual-channel operation on pause or an instruction to put all -channel operation on pause is issued from CPU to a channel in Transfer state, the transfer operation of the relevant channel (s) can be put on pause (for the operation when an instruction to put the operation on pause is issued to a channel in Disable state, see Step 11 in the software procedure). If an instruction is given from CPU, the relevant channel (s) temporarily suspends the transfer process. It sets SS=111 and gives the notification that it is in Pause state. In th is case, no interrupt can be generated. After instructed from CPU, the transfer stops at the timing when the relevant channel is not performing transfer (in Transfer Gap before the start of the transfer). There is a time difference (Transition state) betwe en the instruction and the stop. It may take some time, depending on the BC setting. See Figure 4-3. In the case of an instruction to put all -channel operation on pause, the timing to stop varies depending on the channel. As DS is set when all of the channels are stopped, it can confirm that all of the channels have stopped. See Figure 4-3. CHAPTER 8: DMAC MN706-00002-1v0-E 201 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 23 Even if instructed from CPU, the transfer may not be put on pause , and instead, it may be successfully completed due to factors such as transfer mode (Burst/Block/Demand) and transfer status (the number of transfers performed, the timing of instruction to put the operation on pause ). Also, if a transfer error occurs before the transfer stops, error stop applies to the transfer . Figure 4-3 Operation when All -channel Pause is Instructed Behavior of all ch.pause request DMA status Transfer Transfer actionPause TC 7654 SS 000000 All ch . pause request from CPU All ch . pause cancel request from CPU DMA status T ra n sfe r Transfer action Pause TC 432 SS 000000 DMA status Transfer Transfer action Disable TC (reload) 03 SS 000101 (normal end) 111 (Pause ) 111(Pause ) Transfer Transfer DS Ch.2 normal end All ch . pause Ch .0 Ch .1 Ch .2 9. Pause state SS is read from CPU to confirm the pause of the transfer. The SS of a channel in Pause state is " 111". While in this state, it cannot be cleared from CPU. Even during the pause, the transfer content cannot be specified or changed (writing DMACSA, DMACDA, DMACA[29:0] or DMACB[31:1] ). Also, when a channel in Pause state is instructed to pause, it continues to remain in the Pause state. 10. Pause state / Cancellation of transfer pause If an instruction to enable individual -channel operation is issued to a channel that has been in Pause state due to an instruction to put individual- channel operation on pause, that channel returns to Transfer state. If an instruction to enable all -channel operation is issued to channels that have been in Pause state due to an instruction to put all -channel operation on pause, those channels return to Transfer state. If both of the pause instructions have been given, issue an instruction to cancel both of them. After the instruction, SS is cleared to "000" via DMAC. If an instruction to enable individual -channel operation and an instruction to enable all -channel operation are issued i n Pause state, they instruct the pause to be cancelled. If they are issued in Disable state, attention must be paid, as they may instruct a new transfer to be started. See Step 11 in the software procedure. CHAPTER 8: DMAC MN706-00002-1v0-E 202 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 24 Figure 4-3 shows an example of the case where an instruction to put all -channel operation on pause. The explanation of the figure is as follows. At the beginning, three channels, namely ch.0, ch.1 and ch.2 , perform their transfer operations in Block transfer mode. ch.2 successfully completes its transfer, moves to Disable state and sets SS=101. Then, ch.0 and ch.1 perform transfers alternately. If an instruction to put all -channel operation on pause is issued from CPU at this point, the following operation applies . As ch.0 is subject to the Transfer Gap timing, it immediately moves to Pause state and sets SS=111 . As ch.1 is in the middle of transfer operation, it performs the transfer until the timing of the next Transfer Gap, and then moves to Pause state and sets SS=111 . As ch.2 is in Disable state, it remains in the Disable state without changing SS. DS is set, when all of the channels stop their operations. Next, if an instruction to enable all- channel operation (instruction to cancel the pause) is issued from C PU, the following operation applies. ch.0 and ch.1 return to Transfer state and clear SS to " 000". As ch.2 is in Disable state (DE=1, EB=0), it remains in that sate without starting the operation. Because the pause of all of the channels has been cancelled now, DS is reset. 11. Operation in Disable state A channel in Disable state remains in the Disable state, unless the conditions such as DE=1, DH=0000, EB=1, and PB=0 are established. Although in 1- 2 of the software procedure, DE is set from the conditions of DE=0 and EB=0 , and then, EB is set, there is no problem to set EB before DE. DE can be set last after all of the transfer settings of multiple channels subject to transfer are completed. In this case, an instruction can be issued to allow the multiple channels subject to transfer to start their transfer operations simultaneously. If such instruction for simultaneous start of transfers is issued, DMAC selects the channels to which transfers are to be started, according to the PR setting (PR can be set or cha nged, only when all -channel operation is disabled). If an instruction to disable individual -channel operation, an instruction to put individual -channel operation on pause, an instruction to disable all -channel operation or an instruction to put all- channel operation on pause is issued, only the settings of DE, DH, EB and PB are changed, but the conditions of DE=1, DH=0000, EB=1 and PB=0 are not established. Therefore, the relevant channels do nothing and do not change SS. If an instruction to put all -channe l operation on pause is issued from CPU to a channel in Disable state, as shown in the example of ch.2 operation in Figure 4-3, that channel does not change its state with SS indicating the completion of the previo us transfer. If an instruction to put individual - or all- channel operation on pause is issued to a channel in Disable state, it may be put in Disable state with DE=1, EB=1, (DH!=0000 or PB=1). Although the bit values in this state are the same as DE, EB, D H and PB , they can be distinguished because SS has a different value. Figure 4-4 shows such an example. Figure 4-4 Example of Operation when Instruction to Put Individual -channel Operation on Pause is Issued in Disabled State Example of pause request during disable state DMA status Tr a nsfe r Transfer action Disable SS 000 Ch . pause request from CPU Ch . pause cancel request from CPU ( same as new transfer start request ) 101 (normal end ) Transfer Transfer normal end RegisterDE=1, EB=1 DH =0000, PB=0DE =1, EB=0 DH=0000, PB=0DE=1, EB=1 DH =0000, PB=1DE=1, EB=1 DH =0000, PB=0 CHAPTER 8: DMAC MN706-00002-1v0-E 203 MB9Axxx/MB9Bxxx Series
4. DMAC Control FUJITSU SEMICONDUCTOR LIMITED CHAPTER: DMAC FUJITSU SEMICONDUCTOR CONFIDENTIAL 25 A certain channel is performing transfer operation. CPU issues an instruction to put in dividual-channel operation on pause to that channel. The instruction is issued after the transfer is completed and it moves to Disable state (DE=1, DH=0000, EB=0, PB=0) . This phenomenon can occur, because the channel currently performing transfer operation changes its state outside CPU ’s intention. In this case, the bit values of the relevant channel change to (DE=1, DH=0000, EB=1, PB=1) due to instruction from CPU, but SS remains " 101" , the value set upon the completion. If the operation is stopped by a pa use instruction, SS will be " 111 "; therefore, it will be possible to distinguish between the pause state and the state in which the transfer has been completed. It should be noted that if an instruction to cancel the pause is issued without checking the st ate of the channel by SS, a new transfer will accidentally start, as shown in Figure 4-4. Additional Matter 1 As ST is cleared upon the completion of a transfer, the read value of ST is "0" after the completion of the transfer. I n the case of software transfer, it should be noted that "1" must always be written to ST, regardless of its read value. Additional Matter 2 An instruction to enable individual -channel operation cannot be issued during the period after the previous instruc tion to enable individual -channel operation instructs the start of transfer and before the completion of the transfer is confirmed. This is because the channel to be controlled may change its state outside CPU ’s intention and an instruction to start a new transfer may be issued when DMAC has moved to Disable state (EB=0). Even if the SS value confirms that the channel to be controlled is in Transfer state, the channel to be controlled may move to Disable state during the period between that point and the wr ite operation. Additional Matter 3 The DE and DH values can only be rewritten from CPU and these registers are never cleared from DMAC. Therefore, there is no problem to write DE=1 and DH=00000 during the transfer operation. DH is not cleared, if an instruction to disable individual -channel operation is issued to a channel in all- channel Pause state (DE=1, DH!=0000, EB=1, PB=0). After the instruction, the relevant channel moves to Disable state (DE=1, DH!=0000, EB=0, PB=0) . To start a new transfer of the relevant channel, write DE=1 and DH=0000. This indicates that the cancellation of the pause of all -channel operation is required in order to start a new transfer of the individual channel. Additional Matter 4 The SS value is set from DMAC upon the completion of a transfer and it is never rewritten from DMAC as long as it is in Disable state. Even if the SS value is not cleared, the next transfer can be started. However, if it moves to Transfer state, the SS value may be cleared from DMAC (or may not be cleared). When an interrupt from DMAC is used, it should be noted that the interrupt signal is deasserted at a timing which is not intended by CPU, if it moves to Transfer state without clearing SS. CHAPTER 8: DMAC MN706-00002-1v0-E 204 MB9Axxx/MB9Bxxx Series