Fujitsu Series 3 Manual

							 
5. USB host registers 
 
[bit 10] STUFF (STUFFing error) 
This is a stuffing error flag. 
If this bit is set to 1, it means that a bit stuffing error is detected. When this bit is 0, it means that no 
stuffing error is detected. If a stuffing error is detected, bit 5 (Timeout) of this register is also set to 1. If 
this bit is written with 0, it is set to 0. However,  if this bit is written with 1, its value is ignored. 
Bit Description 
0 No stuffing error. 
1 Stuffing error occurs. 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
[bit 9:8] HS (Hand Shake status) 
These are handshake status flags. 
These flags indicate the status of a handshake packet to be sent or received. 
These flags are set to NULL when  no handshake occurs due to an error or when a SOF token has been 
ended with the TKNEN bit of the Host Token Endpoint Register (HTOKEN). 
These bits are updated when sending or receiving has been ended. 
Table 5-1 Handshake 
Bit 9 Bit 8 Handshake 
0 0  ACK 
0 1 NAK 
1 0 STALL 
1 1  NULL 
 
 
This  b

it is set to the initial value when 1 is set to the RST b it of th
 e UDC Control Register (UDCC). 
 
 
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5.4.  Host Status Register (HSTATE) 
The Host Status Register (HSTATE) indicates the state of the USB circuit such as a device 
connection or transfer mode. Note that the setting of the CLKSEL bit is also effective in the 
function mode. 
 bit 7 6 5 4 3 2 1 0 
Field ReservedReserved ALIVECLKSELSOFBUSYSUSP TMODE CSTAT 
Attribute  - R/W R/W R/W R/W  R R 
Initial value  X 0 1 0 0  1 0 
Reset enabled    or not*  - x 
x  x x 
      
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 7:6] Reserved bits 
These are reserved bits. These bits are undefined in read mode. Even if 0  or 1 is written to these bits, it 
has no effect on LSI operations. 
 
[bit 5] ALIVE (keep-ALIVE) 
This bit is used to specify the keep-alive function in the low-speed mode. If this bit it set to 1 while the 
CLKSEL bit of the Host Status Register (HSTATE) is 0,  SE0 is output instead of SOF. This bit is effective 
when the CLKSEL bit of the Host Status Register (H STATE) is 0. If the CLKSEL bit is 1, SOF is 
output regardless of the se tting of the ALIVE bit. 
Bit Description 
0 SOF output 
1 SE0 output (Keep-alive) 
 
[bit 4] CLKSEL (CLocK SELect) 
This is a USB operation clock selection bit. 
Bit Description 
0 Low-speed clock 
1 Full-speed clock 
 
 

 This bit is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Change the value of this bit while the RST bit  of the UDC Control Register (UDCC) is 1. 

 This bit must always be set to 1. It must not be set to 0. 

 Use the on-chip bus (HCLK) clock with 13 MHz or more. 
 
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[bit 3] SOFBUSY (SOF BUSY) 
This is a SOF busy flag. 
When a SOF token is sent using the Host Token Endpoint Register (HTOKEN), this bit is set to 1, which 
means that the SOF timer is active. When this bit is 0, it means that the SOF timer is under suspension. To 
stop the active SOF timer, write 0 to this bit. However,  if this bit is written with 1, its value is ignored. 
Bit Description 
0 The SOF timer is stopped. 
1  The SOF timer is active. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 The SOF timer does not stop immediately after 0 has been set to this bit to stop the SOF timer. To 
check whether or not the SOF timer is stopped, read this bit. 
 
[bit 2] SUSP (SUSPend) 
This is a suspend setting bit. 
If this bit is set to 1, the USB circu it is placed into the suspend state. If this bit is set to 0 while it is 1 
or the USB bus is placed into the k-state mode, the susp end state is released, and the RWIRQ bit of the Host 
Interrupt Register (HIRQ) is set to 1. 
Table 5-2 Suspend setting 
Bit 10 Operation 
Set to 1.  Suspend 
Set 0 while this bit is 1.  Resume 
Others Holds the status. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Do not set this bit to 1 while the USB is active (during USB bus resetting, data transfer, or SOF timer 
running). 

 USB clock must not be stopped in the suspend state. 

 If the value of this bit is changed, it is not immediat ely reflected on the state of the USB bus. To check 
whether or not the state is updated, read this bit. 
 
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[bit 1] TMODE (Transmission MODE) 
This is a transmission mode flag. 
If this bit is 1, it means that the device is connected in the full-speed mode. When this bit is 0, it means 
that the device is connected in the low-speed mode. This bit is valid when the CSTAT bit of the Host Status 
Register (HSTATE) is 1. 
Bit Description 
0 Low Speed 
1 Full Speed 
 
 
 This bit is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Use the base clock (HCLK) with 13 MHz or more. 
 
[bit 0] CSTAT (Connect STATus) 
This is a connection status flag. 
When this bit is 1, it means that the device is connected. When this bit is 0, it means that the device is 
disconnected. 
Bit Description 
0  Device is disconnected. 
1 Device is connected. 
 
 
This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
  
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5.5.  SOF Interrupt Frame Compare Register (HFCOMP) 
The SOF Interrupt Frame Compare Register (HFCOMP) is used to specify the data to be 
compared with the low-order eight bits of a frame number when sending a SOF token. When 
the SOFSTEP bit of Host Control Register 0 (HCNT0) is 0, the value of this register is 
comp
ared with that of the low-order eight bits of a frame number. If they match, the SOFIRQ 
bit of the Host interrupt Register (HIRQ) is set to 1 when starting SOF sending. When the 
SOFIRE bit of Host Control Register 0 (HCNT0) is 1, an interrupt occurs. 
 
bit 15 14 13 12 11 10 9 8 
Field FRAMECOMP 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with the RST bit of  UDCC. x: Not to be reset. o: To be reset. 
 
[bit 15:8] FRAMECOMP 
These are frame compare data. 
These bits are used to specify the data to be compared  with the low-order eight bits of a frame number when 
sending a SOF token. 
If the SOFSTEP bit of Host Control Register 0 (HCNT0) is 0, the frame number of SOF is compared with 
the value of this register when sending a SOF token. If  they match, 1 is set to the SOFIRQ bit of the Host 
Interrupt Register (HIRQ). 
The setting of this register is invalid when the SOFST EP bit of Host Control Register 0 (HCNT0) is 0. 
 
    This b

it is not initialized even if 1 is set to  the RST bit of the UDC C
 ontrol Register (UDCC). 
 
 
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5.6.  Retry Timer Setup Register (HRTIMER) 
The Retry Timer Setup Register (HRTIMER) is used to specify the token retry time. 
 bit 15 14 13 12 11 10 9 8 
Field RTIMER1 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
  bit  7 6 5  4 3 2 1 0 
Field RTIMER0 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
  bit  7(23) 6(22) 5(21)  4(20) 3(19) 2(18) 1(17) 0(16) 
Field Reserved  RTIMER2 
Attribute -  R/W 
Initial value X 00 
Reset enabled    or not*  - x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 23:18] Reserved bits 
These are reserved bits. These bits are undefined in read mode. Even if 0  or 1 is written to these bits, it 
has no effect on LSI operations. 
 
[bit 17:0] HRTIMER0, 1, 2 
These are retry timer setting bits. 
These bits are used to specify the retry time in this re gister. The retry timer is activated when token sending 
starts while the RETRY bit of Host Control Register  1 (HCNT1) is 1. The retry time is then decremented 
by one when a 1-bit transfer clock (12 MHz in the full-speed mode) is output. When the retry timer reaches 
0, the target token is sent, and processing is ended. 
If a token retry occurs in the EOF area, the retry timer is stopped until SOF sending is ended. After SOF 
sending has been completed, the retry timer restarts  with the value that is set when the timer stopped. 
 

 This bit is not initialized even if 1 is set to the RS T bit of the UDC Control Register (UDCC). If data is 
written while the RST bit of the UDC Control Register (UDCC) is 1, the written data is ignored. 

 Write this register in the host mode. Bit 15 to 0 of this  register are set to 0 in the function mode. Even if 
data is written to bits 15 to 0 of this register, it is ignored. 
 
 
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5.7. Host Address Register (HADR) 
The Host Address Register (HADR) is used as an address field to send a token. 
 bit 15 14 13 12 11 10 9 8 
Field ReservedAddress 
Attribute -  R/W 
Initial value X  0000000 
Reset enabled    or not*  - x 
* : Enables or disables a reset with the RST bit of  UDCC. x: Not to be reset. o: To be reset. 
 
[bit 15] Reserved bit 
This is a reserved bit. This bits is undefined in read  mode. Even if 0 or 1 is written to this bit, it has no 
effect on LSI operations. 
 
[bit 14:8] Address 
These are address bits. 
These bits are used to specify a token address. 
 

 
Th is 
b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
  
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5.8.  EOF Setup Register (HEOF) 
The EOF Setup Register (HEOF) is used to specify the token disable time before sending a 
SOF token. If both the following conditions are satisfied, a request token is sent after a SOF 
token has been transferred. 
- When the value of the SOF timer is comp

ared with that of this register, it is less than the 
value of this register. 
- An IN, OUT, or SETUP token sending request has been issued. 
This is a function to prevent a SOF token generated by hardware from being sent together 
with other tokens. The time unit of this register is the 1-bit transfer time. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved EOF1 
Attribute -  R/W 
Initial value X  000000 
Reset enabled    or not*  - x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
  bit  7 6 5  4 3 2 1 0 
Field EOF0 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*  x 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 15:14] Reserved bits 
These are reserved bits. These bits are undefined in read mode. Even if 0  or 1 is written to these bits, it 
has no effect on LSI operations. 
 
[bit 13:0] EOF1, EOF0 (End Of Frame) 
These are EOF bits. 
These bits are used to specify the time to disable to ken sending before transferring SOF. Specify the time 
with a margin, which is longer than the one-packet length. The time unit is the 1-bit transfer time. 
Setting example:  MAXPKT = 64 bytes, full-speed mode 
  (Token_length + packet_length + header + CRC)*7/6 + Turn_around_time 
    =(34 bit + 546 bit)*7/6 + 36 bit = 712.7 bit 
 Therefore, set (2C9)h. 
 
  This  b

it is not initialized even if 1 is set to the RST bit of the UDC Control Register (UDCC). 
  
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5.9.  Frame Setup Register (HFRAME) 
The Frame Setup Register (HFRAME) is used to specify a frame number when sending a 
SOF token. If SOF sending is set to the TKNEN bit of the Host Token Endpoint Register 
(HTOKEN), the SOF timer is activated. Af
ter this, SOF is sent automatically every 1 ms. The 
Frame Setup Register is automatically incremented by one each time SOF is ended. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved FRAME1 
Attribute -  R/W 
Initial value X  000 
Reset enabled    or not*  - 
  
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
  bit  7 6 5  4 3 2 1 0 
Field FRAME0 
Attribute R/W 
Initial value  00000000 
Reset enabled    or not*   
 
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 15:11] Reserved bits 
These are reserved bits. These bits are undefined in read mode. Even if 0  or 1 is written to these bits, it 
has no effect on LSI operations. 
 
[bit 10:0] FRAME1, FRAME0 
These are frame setting bits. 
These bits are used to specify a frame number of SOF. 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Specify a frame number in this register before setting SOF in the TKNEN bit of the Host Token Endpoint 
Register (HTOKEN). 

 This register cannot be written while the SOFBUSY bit  of the Host Status Register (HSTATE) is 1 and 
a SOF token is in process. 
 
 
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5.10.  Host Token Endpoint Register (HTOKEN) 
The Host Token Endpoint Register (HTOKEN) is used to specify toggle, endpoint, and token. 
 bit 7 6 5 4 3 2 1 0 
Field TGGL TKNEN ENDPT 
Attribute R/W  R/W  R/W 
Initial value 0  000  0000 
Reset enabled    or not*   
       
* : Enables or disables a reset with the  RST bit of UDCC. x: Not to be reset.  : To be reset. 
 
[bit 7] TGGL (ToGGLe) 
This is a toggle bit. 
This bit is used to set toggle data. Toggle data is sent depending on the setting of this bit. When receiving 
toggle data, received toggle data is compared with th e toggle data of this bit to verify whether or not an 
error occurs. 
Bit Description 
0 DATA0 
1 DATA1 
 
 

 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 Set this bit when the TKNEN bit of the Host Token Endpoint Register (HTOKEN) is 000. 
 
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